Features
Description
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Industry-Standard Pin-out with Enable Input
The FAN3121 and FAN3122 MOSFET drivers are
designed to drive N-channel enhancement MOSFETs in
low-side switching applications by providing high peak
current pulses. The drivers are available with either TTL
input thresholds (FAN312xT) or VDD-proportional CMOS
input thresholds (FAN312xC). Internal circuitry provides
an under-voltage lockout function by holding the output
low until the supply voltage is within the operating range.
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Internal Resistors Turn Driver Off If No Inputs
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Rated from –40°C to +125°C
4.5-V to 18-V Operating Range
11.4 A Peak Sink at VDD = 12 V
9.7-A Sink / 7.1-A Source at VOUT = 6 V
Inverting Configuration (FAN3121) and
Non-Inverting Configuration (FAN3122)
23-ns / 19-ns Typical Rise/Fall Times (10 nF Load)
18 ns to 23 ns Typical Propagation Delay Time
Choice of TTL or CMOS Input Thresholds
MillerDrive™ Technology
Available in Thermally Enhanced 3x3 mm 8-Lead
MLP or 8-Lead SOIC Package (Pb-Free Finish)
Automotive Qualified to AEC-Q100 (F085 Versions)
Applications
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Synchronous Rectifier Circuits
FAN312x drivers incorporate the MillerDrive™
architecture for the final output stage. This bipolar /
MOSFET combination provides the highest peak current
during the Miller plateau stage of the MOSFET turn-on /
turn-off process.
The FAN3121 and FAN3122 drivers implement an
enable function on pin 3 (EN), previously unused in the
industry-standard pin-out. The pin is internally pulled up
to VDD for active HIGH logic and can be left open for
standard operation.
The commercial FAN3121/22 is available in a 3x3 mm
8-lead thermally-enhanced MLP package or an 8-lead
SOIC package. The AEC-Q100 automotive-qualified
versions are available in the 8-lead SOIC package.
High-Efficiency MOSFET Switching
Switch-Mode Power Supplies
DC-to-DC Converters
Motor Control
Automotive-Qualified Systems (F085 Versions)
VDD 1
8
VDD
VDD 1
8 VDD
IN
2
7
OUT
IN
2
7 OUT
EN
3
6
OUT
EN
3
6 OUT
GND 4
5
GND
GND 4
5 GND
Figure 1.
FAN3121 Pin Configuration
© 2008 Semiconductor Components Industries, LLC.
October-2017, Rev. 2
Figure 2.
FAN3122 Pin Configuration
Publication Order Number:
FAN3122T-F085/D
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
FAN3121 / FAN3122
Single 9-A High-Speed, Low-Side Gate Driver
Part Number
Logic
Input
Threshold
FAN3121CMPX
FAN3121CMX
CMOS
FAN3121CMX-F085
FAN3121TMPX
Inverting
Channels +
Enable
(1)
FAN3121TMX
TTL
(1)
FAN3121TMX-F085
FAN3122CMPX
FAN3122CMX
CMOS
FAN3122CMX-F085
Non-Inverting
Channels +
Enable
(1)
FAN3122TMPX
FAN3122TMX
TTL
FAN3122TMX-F085
Packing
Method
Quantity
per Reel
3x3 mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
SOIC-8
Tape & Reel
2,500
3x3 mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
SOIC-8
Tape & Reel
2,500
3x3 mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
SOIC-8
Tape & Reel
2,500
3x3 mm MLP-8
Tape & Reel
3,000
SOIC-8
Tape & Reel
2,500
SOIC-8
Tape & Reel
2,500
Package
(1)
Note:
1. Qualified to AEC-Q100.
Package Outlines
Figure 3.
1
8
2
7
3
6
4
5
3x3 mm MLP-8 (Top View)
1
8
2
7
3
6
4
5
Figure 4.
SOIC-8 (Top View)
Thermal Characteristics(2)
Package
Θ JL
(3)
Θ JT
(4)
Θ JA
(5)
Ψ JB
(6)
Ψ JT
(7)
Units
8-Lead 3x3 mm Molded Leadless Package (MLP)
1.2
64
42
2.8
0.7
°C/W
8-Pin Small Outline Integrated Circuit (SOIC)
38
29
87
41
2.3
°C/W
Notes:
2. Estimates derived from thermal simulation; actual values depend on the application.
3. Theta_JL (ΘJL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads
(including any thermal pad) that are typically soldered to a PCB.
4. Theta_JT (ΘJT): Thermal resistance between the semiconductor junction and the top surface of the package,
assuming it is held at a uniform temperature by a top-side heatsink.
5. Theta_JA (ΘJA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking,
and airflow. The value given is for natural convection with no heatsink, as specified in JEDEC standards
JESD51-2, JESD51-5, and JESD51-7, as appropriate.
6. Psi_JB (ΨJB): Thermal characterization parameter providing correlation between semiconductor junction
temperature and an application circuit board reference point for the thermal environment defined in Note 5. For
the MLP-8 package, the board reference is defined as the PCB copper connected to the thermal pad and
protruding from either end of the package. For the SOIC-8 package, the board reference is defined as the PCB
copper adjacent to pin 6.
7. Psi_JT (ΨJT): Thermal characterization parameter providing correlation between the semiconductor junction
temperature and the center of the top of the package for the thermal environment defined in Note 5.
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2
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Ordering Information
FAN3121
FAN3122
Name
Description
3
3
EN
Enable Input. Pull pin LOW to inhibit driver. EN has logic thresholds for both
TTL and CMOS IN thresholds.
4, 5
4, 5
GND
2
2
IN
6, 7
OUT
Gate Drive Output. Held LOW unless required input is present and VDD is
above the UVLO threshold.
OUT
Gate Drive Output (inverted from the input). Held LOW unless required
input is present and VDD is above the UVLO threshold.
VDD
Supply Voltage. Provides power to the IC.
P1
Thermal Pad (MLP only). Exposed metal on the bottom of the package;
may be left floating or connected to GND; NOT suitable for carrying current.
6, 7
1, 8
1, 8
VDD 1
Figure 5.
8
Ground. Common ground reference for input and output circuits.
Input.
VDD
VDD 1
8 VDD
IN
2
7
OUT
IN
2
7 OUT
EN
3
6
OUT
EN
3
6 OUT
GND 4
5
GND
GND 4
5 GND
FAN3121 Pin Assignments (Repeated)
Figure 6.
FAN3122 Pin Assignments (Repeated)
Output Logic
FAN3121
FAN3122
EN
IN
OUT
EN
0
0
0
0
0
(8)
0
0
1
(8)
0
1
(8)
1
(8)
1
1
Note:
8. Default input signal if no external connection is made.
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3
IN
OUT
(8)
0
0
1
0
1
(8)
(8)
0
1
(8)
1
1
0
0
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Pin Definitions
VDD
1
8
100k
Inverting
(FAN3121)
UVLO
VDD_OK
IN
VDD
OUT (FAN3121)
7 OUT (FAN3122)
2
100k
6
Non-Inverting
100k (FAN3122)
OUT (FAN3121)
OUT (FAN3122)
VDD
100k
EN
3
5
GND
GND 4
Figure 7.
Block Diagram
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
-0.3
20.0
V
VDD
VDD to GND
VEN
EN to GND
GND - 0.3 VDD + 0.3
V
VIN
IN to GND
GND - 0.3 VDD + 0.3
V
OUT to GND
GND - 0.3 VDD + 0.3
V
VOUT
TL
Lead Soldering Temperature (10 Seconds)
TJ
Junction Temperature
TSTG
Storage Temperature
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4
+260
°C
-55
+150
°C
-65
+150
°C
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Block Diagram
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. ON Semiconductor
does not recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Max.
Unit
4.5
18.0
V
VDD
Supply Voltage Range
VEN
Enable Voltage EN
0
VDD
V
VIN
Input Voltage IN
0
VDD
V
TA
Operating Ambient Temperature
-40
+125
ºC
Electrical Characteristics
Unless otherwise noted, VDD=12 V and TJ=-40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter
Conditions
Min. Typ.
Max.
Unit
18.0
V
Supply
VDD
Operating Range
4.5
IDD
Supply Current, Inputs / EN Not Connected
VON
Device Turn-On Voltage (UVLO)
3.5
4.0
4.3
V
VOFF
Device Turn-Off Voltage (UVLO)
3.30
3.75
4.10
V
18.0
V
TTL
CMOS
(9)
0.65
0.90
0.58
0.85
mA
FAN3121-F085, FAN3122-F085 (Automotive-Qualified Versions)
VDD
Operating Range
4.5
IDD
Supply Current, Inputs / EN Not Connected
VON
Device Turn-On Voltage (UVLO)
VOFF
Device Turn-Off Voltage (UVLO)
Inputs (TTL, FAN312xT)
CMOS
0.65
1.00
0.58
0.85
3.5
4.0
4.3
V
3.25
3.75
4.15
V
0.8
1.0
1.7
2.0
V
0.40
0.70
0.85
V
(9)
(13)
mA
(10)
VIL_T
INx Logic Low Threshold
VIH_T
INx Logic High Threshold
VHYS_T
TTL
TTL Logic Hysteresis Voltage
V
FAN3121TMX, FAN3122TMX
IIN+
Non-Inverting Input Current
IN from 0 to VDD
-1
175
µA
IIN-
Inverting Input Current
IN from 0 to VDD
-175
1
µA
-1.5
1.5
µA
FAN3121TMX-F085, FAN3122TMX-F085 (Automotive-Qualified Versions)
Non-inverting Input Current
(13)
IN=0 V
IINx_T
Non-inverting Input Current
(13)
IN=VDD
90
120
175
µA
IINx_T
Inverting Input Current
(13)
IN=0 V
-175
-120
-90
µA
Inverting Input Current
(13)
IN=VDD
-1.5
1.5
µA
IINx_T
IINx_T
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5
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Recommended Operating Conditions
Parameter
Inputs (CMOS, FAN312xC)
VIL_C
INx Logic Low Threshold
VIH_C
INx Logic High Threshold
VHYS_C
Conditions
Min. Typ.
Max.
Unit
(10)
30
CMOS Logic Hysteresis Voltage
12
38
%VDD
55
70
%VDD
17
24
%VDD
FAN3121CMX, FAN3122CMX
IIN+
Non-Inverting Input Current
IN from 0 to VDD
-1
175
µA
IIN-
Inverting Input Current
IN from 0 to VDD
-175
1
µA
-1.5
1.5
µA
FAN3121CMX-F085, FAN3122CMX-F085 (Automotive-Qualified Versions)
Non-Inverting Input Current
(13)
IN=0 V
IINx_C
Non-Inverting Input Current
(13)
IN=VDD
90
120
175
µA
IINx_C
Inverting Input Current
(13)
IN=0 V
-175
-120
-90
µA
Inverting Input Current
(13)
IN=VDD
-1.5
1.5
µA
IINx_C
IINx_C
Electrical Characteristics (Continued)
Unless otherwise noted, VDD=12 V and TJ=-40°C to +125°C. Currents are defined as positive into the device and
negative out of the device.
Symbol
Parameter
Conditions
Min. Typ.
Max.
Unit
ENABLE (FAN3121, FAN3122)
VENL
Enable Logic Low Threshold
EN from 5 V to 0 V
1.2
1.6
2.0
V
VENH
Enable Logic High Threshold
EN from 0 V to 5 V
1.8
2.2
2.6
V
VHYS_T
TTL Logic Hysteresis Voltage
0.2
0.6
0.8
V
Enable Pull-up Resistance
68
100
134
k
8
17
27
ns
14
21
33
ns
RPU
tD1, tD2
Propagation Delay, CMOS EN
tD1, tD2
(11)
Propagation Delay, TTL EN
(11)
ENABLE (FAN3121-F085, FAN3122-F085) (Automotive-Qualified Versions)
VENL
Enable Logic Low Threshold
EN from 5 V to 0 V
1.2
1.6
2.0
V
VENH
Enable Logic High Threshold
EN from 0 V to 5 V
1.8
2.2
2.6
V
VHYS_T
TTL Logic Hysteresis Voltage
0.20
0.60
0.85
V
68
100
134
k
6
17
35
ns
8
22
34
ns
RPU
Enable Pull-up Resistance
tD1, tD2
Propagation Delay, CMOS EN
tD1, tD2
(11)
Propagation Delay, TTL EN
(11)
Outputs
ISINK
OUT Current, Mid-Voltage, Sinking
(12)
ISOURCE
OUT Current, Mid-Voltage, Sourcing
IPK_SINK
OUT Current, Peak, Sinking
(12)
IPK_SOURCE OUT Current, Peak, Sourcing
tRISE
Output Rise Time
tFALL
Output Fall Time
(12)
(12)
(11)
Output Propagation Delay, CMOS Inputs
tD1, tD2
Output Propagation Delay, TTL Inputs
Output Reverse Current Withstand
9.7
A
OUT at VDD/2,
CLOAD=1.0 µF, f=1 kHz
7.1
A
CLOAD=1.0 µF, f=1 kHz
11.4
A
CLOAD=1.0 µF, f=1 kHz
(11)
tD1, tD2
IRVS
OUT at VDD/2,
CLOAD=1.0 µF, f=1 kHz
(11)
(11)
10.6
A
CLOAD=10 nF
18
23
29
ns
CLOAD=10 nF
11
19
27
ns
0 – 12 VIN, 1 V/ns Slew Rate
9
18
28
ns
0 – 5 VIN, 1 V/ns Slew Rate
9
23
35
ns
(12)
1500
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6
mA
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Symbol
Parameter
Conditions
Min. Typ.
Max.
Unit
FAN3121-F085, FAN3122-F085 (Automotive-Qualified Versions)
tRISE
tFALL
Output Rise Time
Output Fall Time
(11)
(11)
tRISE
Output Rise Time
tFALL
Output Fall Time
CMOS Inputs
(11)
(11)
CMOS Inputs
TTL Inputs
TTL Inputs
tD1, tD2
Output Propagation Delay, CMOS Inputs
tD1, tD2
(11)
Output Propagation Delay, TTL Inputs
VOH
High Level Output Voltage
VOL
Low Level Output Voltage
(13)
(13)
(13)
CLOAD=10 nF
12
23
31
ns
CLOAD=10 nF
12
19
27
ns
CLOAD=10 nF
18
23
36
ns
CLOAD=10 nF
10
19
28
ns
0 – 12 VIN, 1 V/ns Slew Rate
6
18
35
ns
0 – 5 VIN, 1 V/ns Slew Rate
9
23
36
ns
VOH=VDD–VOUT, IOUT=–1 mA
15
35
mV
IOUT=1 mA
10
25
mV
Notes:
9. Lower supply current due to inactive TTL circuitry.
10. EN inputs have modified TTL thresholds; refer to the ENABLE section.
11. See Timing Diagrams of Figure 8 and Figure 9.
12. Not tested in production.
13. Automotive-qualified F085 version specifications.
Timing Diagrams
Input V IH
or
Enable V IL
Input V
IH
or
Enable V IL
tD1
tD2
t RISE
t D1
t FALL
t D2
t FALL
90%
90%
Output
Output
10%
10%
Figure 8.
Non-Inverting
Figure 9.
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7
Inverting
t RISE
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Symbol
Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted.
Figure 10. IDD (Static) vs. Supply Voltage
(14)
Figure 11. IDD (Static) vs. Supply Voltage
(14)
Figure 12. IDD (No-Load) vs. Frequency
Figure 13. IDD (No-Load) vs. Frequency
Figure 14. IDD (10 nF Load) vs. Frequency
Figure 15. IDD (10 nF Load) vs. Frequency
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FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted.
Figure 16. IDD (Static) vs. Temperature
(14)
Figure 17. IDD (Static) vs. Temperature
(14)
Figure 18. Input Thresholds vs. Supply Voltage
Figure 19. Input Thresholds vs. Supply Voltage
Figure 20. Input Thresholds % vs. Supply Voltage
Figure 21. Enable Thresholds vs. Supply Voltage
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9
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted.
Figure 22. CMOS Input Thresholds vs. Temperature
Figure 23. TTL Input Thresholds vs. Temperature
Figure 24. Enable Thresholds vs. Temperature
Figure 25. UVLO Thresholds vs. Temperature
Figure 26. UVLO Hysteresis vs. Temperature
Figure 27. Propagation Delay vs. Supply Voltage
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10
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted.
Figure 28. Propagation Delay vs. Supply Voltage
Figure 29. Propagation Delay vs. Supply Voltage
Figure 30. Propagation Delay vs. Supply Voltage
Figure 31. Propagation Delay vs. Supply Voltage
Figure 32. Propagation Delays vs. Temperature
Figure 33. Propagation Delays vs. Temperature
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FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted.
Figure 34. Propagation Delays vs. Temperature
Figure 35. Propagation Delays vs. Temperature
Figure 36. Propagation Delays vs. Temperature
Figure 37. Fall Time vs. Supply Voltage
Figure 38. Rise Time vs. Supply Voltage
Figure 39. Rise and Fall Time vs. Temperature
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12
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
Typical characteristics are provided at 25°C and VDD=12 V unless otherwise noted.
Figure 40. Rise / Fall Waveforms with 10 nF Load
Figure 42. Quasi-Static Sink Current with VDD=12 V
(15)
Figure 41. Quasi-Static Source Current with VDD=12V
(15)
Figure 43. Quasi-Static Source Current with
(15)
VDD=8 V
V DD
(2) x 4.7µF
ceramic
Current Probe
LECROY AP015
FAN3121/22
IN
1kHz
Figure 44. Quasi-Static Sink Current with VDD=8 V
(15)
470µF
Al. El.
IOUT
1µF
ceramic
VOUT
C LOAD
1µF
Figure 45. Quasi-Static IOUT / VOUT Test Circuit
Notes:
14. For any inverting inputs pulled LOW, non-inverting inputs pulled HIGH, or outputs driven HIGH; static IDD
increases by the current flowing through the corresponding pull-up/down resistor, shown in Figure 7.
15. The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the
current-measurement loop.
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FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Typical Performance Characteristics
The FAN3121 and FAN3122 family offers versions in
either TTL or CMOS input configuration. In the
FAN3121T and FAN3122T, the input thresholds meet
industry-standard TTL-logic thresholds independent of
the VDD voltage, and there is a hysteresis voltage of
approximately 0.7 V. These levels permit the inputs to
be driven from a range of input logic signal levels for
which a voltage over 2 V is considered logic HIGH. The
driving signal for the TTL inputs should have fast rising
and falling edges with a slew rate of 6 V/µs or faster, so
the rise time from 0 to 3.3 V should be 550 ns or less.
For applications with zero voltage switching during the
MOSFET turn-on or turn-off interval, the driver supplies
high peak current for fast switching, even though the
Miller plateau is not present. This situation often occurs
in synchronous rectifier applications because the body
diode is generally conducting before the MOSFET is
switched on.
The output pin slew rate is determined by VDD voltage
and the load on the output. It is not user adjustable, but
a series resistor can be added if a slower rise or fall time
at the MOSFET gate is needed.
The FAN3121 and FAN3122 output can be enabled or
disabled using the EN pin with a very rapid response
time. If EN is not externally connected, an internal pullup resistor enables the driver by default. The EN pin has
logic thresholds for parts with either TTL or CMOS IN
thresholds.
In the FAN3121C and FAN3122C, the logic input
thresholds are dependent on the VDD level and, with VDD
of 12 V, the logic rising edge threshold is approximately
55% of VDD and the input falling edge threshold is
approximately 38% of VDD. The CMOS input
configuration
offers
a
hysteresis
voltage
of
approximately 17% of VDD. The CMOS inputs can be
used with relatively slow edges (approaching DC) if
good decoupling and bypass techniques are
incorporated in the system design to prevent noise from
violating the input voltage hysteresis window. This
allows setting precise timing intervals by fitting an R-C
circuit between the controlling signal and the IN pin of
the driver. The slow rising edge at the IN pin of the
driver introduces a delay between the controlling signal
and the OUT pin of the driver.
Static Supply Current
In the IDD (static) Typical Performance Characteristics,
the curves are produced with all inputs / enables floating
(OUT is LOW) and indicates the lowest static IDD current
for the tested configuration. For other states, additional
current flows through the 100 kΩ resistors on the inputs
and outputs, as shown in the block diagram (see Figure
7). In these cases, the actual static IDD current is the
value obtained from the curves, plus this additional
current.
MillerDrive™ Gate-Drive Technology
FAN312x gate drivers incorporate the MillerDrive™
architecture shown in Figure 46. For the output stage, a
combination of bipolar and MOS devices provide large
currents over a wide range of supply voltage and
temperature variations. The bipolar devices carry the
bulk of the current as OUT swings between 1/3 to 2/3
VDD and the MOS devices pull the output to the HIGH or
LOW rail.
The purpose of the Miller Drive™ architecture is to
speed up switching by providing high current during the
Miller plateau region when the gate-drain capacitance of
the MOSFET is being charged or discharged as part of
the turn-on / turn-off process.
VDD
Input
stage
VOUT
Figure 46. Miller Drive™ Output Architecture
Under-Voltage Lockout (UVLO)
The FAN312x startup logic is optimized to drive groundreferenced N-channel MOSFETs with an under-voltage
lockout (UVLO) function to ensure that the IC starts in
an orderly fashion. When VDD is rising, yet below the
4.0 V operational level, this circuit holds the output low,
regardless of the status of the input pins. After the part
is active, the supply voltage must drop 0.25 V before the
part shuts down. This hysteresis helps prevent chatter
when low VDD supply voltages have noise from the
power switching. This configuration is not suitable for
driving high-side P-channel MOSFETs because the low
output voltage of the driver would turn the P-channel
MOSFET on with VDD below 4.0 V.
VDD Bypassing and Layout Considerations
The FAN3121 and FAN3122 are available in either
8-lead SOIC or MLP packages. In either package, the
VDD pins 1 and 8 and the GND pins 4 and 5 should be
connected together on the PCB.
In typical FAN312x gate-driver applications, high-current
pulses are needed to charge and discharge the gate of
a power MOSFET in time intervals of 50 ns or less. A
bypass capacitor with low ESR and ESL should be
connected directly between the VDD and GND pins to
provide these large current pulses without causing
unacceptable ripple on the VDD supply. To meet these
requirements in a small size, a ceramic capacitor of
1 µF or larger is typically used, with a dielectric material
such as X7R, to limit the change in capacitance over the
temperature and / or voltage application ranges.
www.onsemi.com
14
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Applications Information
VDD
VDS
VDD
Turn-on threshold
IN-
IN+
(VDD)
CBYP
FAN3121/2
OUT
PWM
Figure 50. Inverting Startup Waveforms
Figure 47. Current Path for MOSFET Turn-On
Figure 48 shows the path the current takes when the gate
driver turns the MOSFET off. Ideally, the driver shunts the
current directly to the source of the MOSFET in a small
circuit loop. For fast turn-off times, the resistance and
inductance in this path should be minimized.
VDD
At power up, the FAN3122 non-inverting driver, shown
in Figure 51, holds the output LOW until the VDD voltage
reaches the UVLO turn-on threshold, as indicated in
Figure 52. The OUT pulses magnitude follow VDD
magnitude until steady-state VDD is reached.
VDD
VDS
IN
CBYP
OUT
FAN3121/2
Figure 51. Non-Inverting Driver
PWM
Figure 48. Current Path for MOSFET Turn-Off
VDD
Turn-on threshold
Operational Waveforms
At power up, the FAN3121 inverting driver shown in
Figure 49 holds the output LOW until the VDD voltage
reaches the UVLO turn-on threshold, as indicated in
Figure 50. This facilitates proper startup control of lowside N-channel MOSFETs.
IN+
VDD
IN
IN-
OUT
OUT
Figure 49. Inverting Configuration
The OUT pulses’ magnitude follows VDD magnitude with
the output polarity inverted from the input until steadystate VDD is reached.
Figure 52.
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15
Non-Inverting Startup Waveforms
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Figure 47 shows the pulsed gate drive current path
when the gate driver is supplying gate charge to turn the
MOSFET on. The current is supplied from the local
bypass capacitor CBYP and flows through the driver to
the MOSFET gate and to ground. To reach the high
peak currents possible with the FAN312x family, the
resistance and inductance in the path should be
minimized. The localized CBYP acts to contain the high
peak current pulses within this driver-MOSFET circuit,
preventing them from disturbing the sensitive analog
circuitry in the PWM controller.
Gate drivers used to switch MOSFETs and IGBTs at
high frequencies can dissipate significant amounts of
power. It is important to determine the driver power
dissipation and the resulting junction temperature in the
application to ensure that the part is operating within
acceptable temperature limits.
The total power dissipation in a gate driver is the sum of
two components, PGATE and PDYNAMIC:
PTOTAL = PGATE + PDYNAMIC
(1)
Gate Driving Loss: The most significant power loss
results from supplying gate current (charge per unit
time) to switch the load MOSFET on and off at the
switching frequency. The power dissipation that
results from driving a MOSFET at a specified gatesource voltage, VGS, with gate charge, QG, at
switching frequency, fSW, is determined by:
PGATE = QG • VGS • fSW
(2)
Dynamic Pre-drive / Shoot-through Current: A
power loss resulting from internal current
consumption under dynamic operating conditions,
including pin pull-up / pull-down resistors, can be
obtained using the “IDD (No-Load) vs. Frequency”
graphs in Typical Performance Characteristics to
determine the current IDYNAMIC drawn from VDD
under actual operating conditions:
PDYNAMIC = IDYNAMIC • VDD
(3)
Once the power dissipated in the driver is determined,
the driver junction rise with respect to circuit board can
be evaluated using the following thermal equation,
assuming ψ JB was determined for a similar thermal
design (heat sinking and air flow):
TJ
= PTOTAL • ψ JB + TB
(4)
TB = board temperature in location as defined in
the Thermal Characteristics table.
In a full-bridge synchronous rectifier application, shown
in Figure 53, each FAN3122 drives a parallel
combination of two high-current MOSFETs, (such as
FDMS8660S). The typical gate charge for each SR
MOSFET is 70 nC with VGS = VDD = 9 V. At a switching
frequency of 300 kHz, the total power dissipation is:
PGATE = 2 • 70 nC • 9V • 300 kHz = 0.378 W
(5)
PDYNAMIC = 2 mA • 9 V = 18 mW
(6)
PTOTAL = 0.396 W
(7)
The SOIC-8 has a junction-to-board thermal
characterization parameter of ψ JB = 42°C/W. In a
system application, the localized temperature around
the device is a function of the layout and construction of
the PCB along with airflow across the surfaces. To
ensure reliable operation, the maximum junction
temperature of the device must be prevented from
exceeding the maximum rating of 150°C; with 80%
derating, TJ would be limited to 120°C. Rearranging
Equation 4 determines the board temperature required
to maintain the junction temperature below 120°C:
TB,MAX = TJ - PTOTAL • ψ JB
(8)
TB,MAX = 120°C – 0.396 W • 42°C/W = 104°C
(9)
For comparison, replace the SOIC-8 used in the
previous example with the 3x3 mm MLP package with
ψ JB = 2.8°C/W. The 3x3 mm MLP package can operate
at a PCB temperature of 118°C, while maintaining the
junction temperature below 120°C. This illustrates that
the physically smaller MLP package with thermal pad
offers a more conductive path to remove the heat from
the driver. Consider tradeoffs between reducing overall
circuit size with junction temperature reduction for
increased reliability.
where:
TJ = driver junction temperature;
ψ JB = (psi) thermal characterization parameter relating
temperature rise to total power dissipation; and
www.onsemi.com
16
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Thermal Guidelines
V IN
V OUT
B2
A2
B1
A1
BIAS
FAN3122
FAN3122
From A2
SR EN
VDD 1
8
2
7
3
6
4
5
IN
EN
From A1
VDD
OUT
OUT
8
2
7
IN
3
SR EN
EN
6
4
5
PGND
AGND
VDD 1
AGND
Figure 53. Full-Bridge Synchronous Rectification
VOUT
VIN
PWM
FAN3121
VDD
SR Enable
Active HIGH
IN
EN
AGND
VBIAS
1
2
3
8
P1
(AGND)
4
7
6
5
VDD
OUT
OUT
PGND
Figure 54. Hybrid Synchronous Rectification in a Forward Converter
www.onsemi.com
17
VDD
OUT
OUT
PGND
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Typical Application Diagrams
Part
Number
(16)
Type
Gate Drive
(Sink/Src)
Input
Threshold
Logic
Package
(18)
Single Channel of Dual-Input/Single-Output
SOT23-5,
MLP6
Single Non-Inverting Channel with External
Reference
SOT23-5,
MLP6
CMOS
Single Channel of Two-Input/One-Output
SOT23-5,
MLP6
+2.5 A / -1.8 A
TTL
Single Channel of Two-Input/One-Output
SOT23-5,
MLP6
SOT23-5
FAN3111C Single 1 A
+1.1 A / -0.9 A
CMOS
FAN3111E Single 1 A
+1.1 A / -0.9 A
External
FAN3100C Single 2 A
+2.5 A / -1.8 A
FAN3100T Single 2 A
(17)
FAN3180
Single 2 A
+2.4 A / -1.6 A
TTL
Single Non-Inverting Channel + 3.3 V LDO
FAN3216T
Dual 2 A
+2.4 A / -1.6 A
TTL
Dual Inverting Channels
SOIC8
FAN3217T
Dual 2 A
+2.4 A / -1.6 A
TTL
Dual Non-Inverting Channels
SOIC8
FAN3226C
Dual 2 A
+2.4 A / -1.6 A
CMOS
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3226T
Dual 2 A
+2.4 A / -1.6 A
TTL
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3227C
Dual 2 A
+2.4 A / -1.6 A
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3227T
Dual 2 A
+2.4 A / -1.6 A
TTL
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3228C
Dual 2 A
+2.4 A / -1.6 A
CMOS
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
FAN3228T
Dual 2A
+2.4 A / -1.6 A
TTL
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
FAN3229C
Dual 2 A
+2.4 A / -1.6 A
CMOS
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
FAN3229T
Dual 2 A
+2.4 A / -1.6 A
TTL
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
FAN3268T
Dual 2 A
+2.4 A / -1.6 A
TTL
20 V Non-Inverting Channel (NMOS) and
Inverting Channel (PMOS) + Dual Enables
SOIC8
FAN3278T
Dual 2 A
+2.4 A / -1.6 A
TTL
30 V Non-Inverting Channel (NMOS) and
Inverting Channel (PMOS) + Dual Enables
SOIC8
FAN3223C
Dual 4 A
+4.3 A / -2.8 A
CMOS
FAN3213T
Dual 4 A
+4.3 A / -2.8 A
TTL
Dual Inverting Channels
FAN3214T
Dual 4 A
+4.3 A / -2.8 A
TTL
Dual Non-Inverting Channels
FAN3223T
Dual 4 A
+4.3 A / -2.8 A
TTL
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3224C
Dual 4 A
+4.3 A / -2.8 A
CMOS
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
Dual Inverting Channels + Dual Enable
SOIC8, MLP8
SOIC8
SOIC8
FAN3224T
Dual 4 A
+4.3 A / -2.8 A
TTL
Dual Non-Inverting Channels + Dual Enable
SOIC8, MLP8
FAN3225C
Dual 4 A
+4.3 A / -2.8 A
CMOS
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
FAN3225T
Dual 4 A
+4.3 A / -2.8 A
TTL
Dual Channels of Two-Input/One-Output
SOIC8, MLP8
CMOS
Single Inverting Channel + Enable
SOIC8, MLP8
FAN3121C Single 9 A +9.7 A / -7.1 A
FAN3121T Single 9 A +9.7 A / -7.1 A
TTL
Single Inverting Channel + Enable
SOIC8, MLP8
FAN3122C Single 9 A +9.7 A / -7.1 A
CMOS
Single Non-Inverting Channel + Enable
SOIC8, MLP8
FAN3122T Single 9 A +9.7 A / -7.1 A
TTL
Single Non-Inverting Channel + Enable
SOIC8, MLP8
FAN3240
Dual 12 A
> +12.0 A
TTL
Dual-Coil Relay Driver, Timing Config. 0
SOIC8
FAN3241
Dual 12 A
> +12.0 A
TTL
Dual-Coil Relay Driver, Timing Config. 1
SOIC8
Notes:
16. Typical currents with OUT at 6 V and VDD = 12 V.
17. Thresholds proportional to an externally supplied reference voltage.
18. Automotive-qualified F085 versions are only offered in SOIC8 packages.
www.onsemi.com
18
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Table 1. Related Products
2X
2X
0.8 MAX
RECOMMENDED LAND PATTERN
0.05
0.00
SEATING
PLANE
A. CONFORMS TO JEDEC REGISTRATION MO-229,
VARIATION VEEC, DATED 11/2001
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
D. FILENAME: MKT-MLP08Drev2
Figure 55. 3x3 mm, 8-Lead Molded Leadless Package (MLP)
www.onsemi.com
19
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Physical Dimensions
4.90±0.10
0.65
A
(0.635)
8
5
B
1.75
6.00±0.20
PIN ONE
INDICATOR
5.60
3.90±0.10
1
4
1.27
1.27
0.25
C B A
LAND PATTERN RECOMMENDATION
SEE DETAIL A
0.175±0.075
0.22±0.03
C
1.75 MAX
0.10
0.42±0.09
OPTION A - BEVEL EDGE
(0.86) x 45°
R0.10
GAGE PLANE
R0.10
OPTION B - NO BEVEL EDGE
0.36
NOTES:
8°
0°
SEATING PLANE
0.65±0.25
(1.04)
DETAIL A
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) LANDPATTERN STANDARD: SOIC127P600X175-8M
E) DRAWING FILENAME: M08Arev16
SCALE: 2:1
Figure 56. 8-Lead Small Outline Integrated Circuit (SOIC)
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20
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
Physical Dimensions (Continued)
FAN3121 / FAN3122 — Single 9-A High-Speed, Low-Side Gate Driver
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