DATA SHEET
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Synchronous TINYBOOST)
Regulator with Bypass
Mode, 2500 mA
WLCSP16 1.81 y 1.81 y 0.586
CASE 567QZ
FAN48623
Description
Features
• Maximum Continuous Load Current: 2500 mA at VIN of 2.5 V
Boosting VOUT to 3.3 V
• Maximum Pulse Load Current of 3.5 A for GSM PAs (1 Slot)
and PMIC Support Simultaneously, VIN = 3.1 V, VOUT = 3.4 V
• Up to 97% Efficient
• 4 External Components: 2520 case 0.47 mH Inductor and 0603 Case
Size Input and Output Capacitors
• Input Voltage Range: 2.5 V to 5.5 V
• Fixed Output Voltage Options: 3.0 V to 5.0 V
• True Bypass Operation when VIN > Target VOUT
• Integrated Synchronous Rectifier
• True Load Disconnect
• Forced Bypass Mode
• VSEL Control to Optimize Target VOUT
• Short−Circuit Protection (SCP)
• Low Operating Quiescent Current
• 16−Bump, 1.81 mm x 1.81 mm, 0.4 mm Pitch, WLCSP
• This is a Pb−Free Device
MARKING DIAGRAM
1
xx&K
&.&2&Z
xx
&K
&.
&2
&Z
= Specific Device Code
= 2−Digits Lot Run Traceability Code
= Pin One Dot
= 2−Digit Date Code Format
= Assembly Location
Battery
VIN
+
L1
The FAN48623 allows systems to take advantage of new battery
chemistries that can supply significant energy when the battery
voltage is lower than the required voltage for system power ICs. By
combining built−in power transistors, synchronous rectification,
and low supply current, this IC provides a compact solution
for systems using advanced Li−Ion battery chemistries.
The FAN48623 is a boost regulator designed to provide a minimum
output voltage from a single−cell Li−Ion battery, even when
the battery voltage is below system minimum. The output voltage
regulation is guaranteed up to a maximum load current of 2500 mA.
The regulator transitions smoothly between Bypass and normal Boost
Mode. The device can be forced into Bypass Mode to reduce quiescent
current.
The FAN48623 is available in a 16−bump, 0.4 mm pitch,
Wafer−Level Chip−Scale Package (WLCSP).
0.47 mH
VOUT
CIN
10 mF
SW
VSEL
EN
BYP
COUT
FAN48623
2x22 mF
PGND
SYSTEM
LOAD
AGND
PG
Figure 1. Typical Application
ORDERING INFORMATION
See detailed ordering and shipping information on page 16
of this data sheet.
Applications
• Boost for Low−Voltage Li−ion Batteries, Brownout Prevention,
System PMIC LDOs Supplies, and 2G/3G/4G RF PA Supplies
• Smart Phones, Tablets, Portable Devices
© Semiconductor Components Industries, LLC, 2013
April, 2022 − Rev. 3
1
Publication Order Number:
FAN48623/D
FAN48623
Typical Application
Q3B Q3A
VIN
Q3
CIN
L1
BYPASS
CONTROL
Q1B Q1A
SW
VOUT
Q2
GND
COUT
Q1
Synchronous
Rectifier
Control
VSEL
EN
BYP
MODULATOR
LOGIC
AND CONTROL
PG
Figure 2. Block Diagram
Table 1. RECOMMENDED COMPONENTS
Component
Description
Vendor
Parameter
Typical Value
Unit
L1
0.47 mH, 20%, 5.3 A, 2520
Toko: DFE252010P−R47M
L
0.47
mH
DCR (Series R)
27
mW
CIN
10 mF, 20%, 10 V, X5R, 0603
TDK: C1608X5R1A106M
C
10
mF
COUT
2 x 22 mF, 20%, 10 V, X5R, 0603
TDK: C1608X5R1A226M080AC
C
44
mF
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2
FAN48623
Pin Configuration
EN
PG
A1
A2
VSEL
NC
B1
B2
BYP
NC
C1
C2
AGND
D1
VIN
A4
A3
A2
A1
B4
B4
B3
B2
B1
C4
C4
C3
C2
C1
D4
D4
D3
D2
D1
A4
A3
VOUT
B3
SW
C3
PGND
D2
D3
Figure 4. Bottom View (Bumps Up)
Figure 3. Top−Through View (Bumps Down)
PIN DESCRIPTIONS
Pin #
Name
A1
EN
Enable. When this pin is HIGH, the circuit is enabled.
Description
A2
PG
Power Good. This is an open−drain output. PG is actively pulled LOW if output falls out
of regulation due to overload or if thermal protection threshold is exceeded.
A3, A4
VIN
Input Voltage. Connect to Li−Ion battery input power source.
B1
VSEL
Output Voltage Select. When boost is running, this pin can be used to select the output
voltage.
B3, B4
VOUT
Output Voltage. Place COUT as close as possible to the device.
C1
BYP
Bypass. This pin can be used to activate Forced Bypass Mode. When this pin is LOW,
the bypass switches (Q3 and Q1) are turned on and the IC is otherwise inactive.
C3, C4
SW
Switching Node. Connect to inductor.
D1
AGND
Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. AGND should be connected to PGND at a single point.
D2−D4
PGND
Power Ground. This is the power return for the IC. The COUT bypass capacitor should be
returned with the shortest path possible to these pins.
B2, C2
NC
No Internal Connection. Note: Bumps are present and should be tied to PGND.
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3
FAN48623
ABSOLUTE MAXIMUM RATINGS
Symbol
VIN
Parameter
Min
Max
Unit
−0.3
6.5
V
−
6.0
V
DC
−0.3
6.0
V
Transient: 10 ns, 3 MHz
−1.0
8.0
−0.3
6.5
(Note 1)
VIN Input Voltage
VOUT
VOUT Output Voltage
VSW
SW Node Voltage
Other Pins
ESD
Electrostatic Discharge Protection Level
Human Body Model,
ANSI/ESDA/JEDEC JS−001−2012
2.0
Charged Device Model, JESD22−C101
1.5
V
kV
TJ
Junction Temperature
−40
+150
°C
TSTG
Storage Temperature
−65
+150
°C
−
+260
°C
TL
Lead Soldering Temperature, 10 Seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Lesser of 6.5 V or VIN + 0.3 V.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VIN
Supply Voltage
2.5
5.5 (Note 2)
V
IOUT
Output Current
0
2500
mA
TA
Ambient Temperature
−40
+85
°C
TJ
Junction Temperature
−40
+125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
2. When VIN nears VOUT the part will go into Automatic Bypass, depending on load current.
THERMAL CHARACTERISTICS
Symbol
qJA
NOTE:
Characteristic
Junction−to−Ambient Thermal Resistance
Value
Unit
60
°C/W
Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with four−layer onsemi
evaluation boards (1 oz copper on all layers). Special attention must be paid not to exceed junction temperature TJ(max) at a given
ambient temperate TA.
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FAN48623
ELECTRICAL CHARACTERISTICS (Note 3)
Unless otherwise noted and per Figure 1 minimum and maximum values are from VIN = 2.5 V to 4.5 V and TA = −40°C to +85°C.
Typical values are at VIN = 3.0 V and TA = 25°C for all output voltage options.
Symbol
IQ
Parameter
VIN Quiescent Current
Min
Typ
Max
Unit
Automatic Bypass Mode,
VOUT_TARGET = 3.3 V, VIN = 3.6 V
Conditions
−
140
190
mA
Boost Mode, VOUT = 3.3 V, VIN = 3.0 V
−
135
180
Shutdown, EN = 0 V, VIN = 3.0 V
−
4.0
12.0
Forced Bypass Mode, VIN = 3.6 V
−
6.0
12.0
ILK
VOUT to VIN Reverse Leakage
VOUT = 5.0 V, EN = 0 V, VIN = 0 V
−
0.5
1.0
mA
ILK_OUT
VIN to VOUT Leakage Current
VOUT = 0 V, EN = 0 V, VIN = 4.2 V
−
0.1
1.5
mA
VUVLO
Under−Voltage Lockout
VIN Rising
−
2.20
2.35
V
VUVLO_HYS
Under−Voltage Lockout
Hysteresis
−
200
−
mV
VIH
Logic Level High EN, VSEL, BYP
1.05
−
−
V
VIL
Logic Level Low EN, VSEL, BYP
−
−
0.4
V
RLOW
Logic Control Pin Pull Downs
(LOW Active)
BYP, VSEL, EN
−
300
−
kW
Weak Current Source Pull−Down
BYP, VSEL, EN
−
100
−
nA
Output Voltage Accuracy
2.5 V ≤ VIN ≤ VOUT_TARGET −100 mV,
DC, 0 to 2500 mA
−1.0
−
4.0
%
2.5 V ≤ VIN ≤ VOUT_TARGET −100 mV,
DC, PWM (CCM) Operation
−1.0
−
2.5
Boost Valley Current Limit
VIN = 2.5 V, VOUT = 3.3 V
4.7
5.3
−
A
IV_LIM_SS
Boost Valley Current Limit During
Soft Start
VIN = 2.5 V, VOUT = 3.3 V
−
2.6
−
A
tSS
Soft−Start EN HIGH to Regulation
50 W Load, VOUT_TARGET = 3.3 V
(Time from EN Rising Edge to 90% of
VOUT_TARGET)
−
300
−
ms
tRST
FAULT Restart Timer
−
20
−
ms
IPD
VREG
IV_LIM
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. Minimum and Maximum limits are verified by design, test, or statistical analysis. Typical (Typ.) numbers are not verified, but represent typical
results.
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FAN48623
TYPICAL CHARACTERISTICS
98%
98%
96%
96%
94%
94%
Efficiency
Efficiency
Unless otherwise specified, TA = 25°C; circuit and components according to Figure 1.
92%
90%
2.5 VIN
2.7 VIN
3.0 VIN
88%
86%
0
500
1000
1500
2000
92%
90%
−40°C
+25°C
+85°C
88%
86%
2500
0
500
Load Current (mA)
98%
96%
96%
Efficiency
Efficiency
94%
92%
90%
88%
82%
2.5 VIN
2.7 VIN
3.0 VIN
0
500
1000
1500
2500
2000
94%
92%
90%
−40°C
+25°C
+85°C
88%
86%
2500
0
500
Load Current (mA)
1000
1500
2000
2500
Load Current (mA)
Figure 7. Efficiency vs. Load Current and Input
Voltage, VOUT = 3.3 V
Figure 8. Efficiency vs. Load Current and
Temperature, VIN = 3.0 V, VOUT = 3.3 V
98%
98%
96%
96%
94%
92%
Efficiency
Efficiency
2000
Figure 6. Efficiency vs. Load Current and
Temperature, VIN = 3.0 V, VOUT = 3.15 V
98%
84%
1500
Load Current (mA)
Figure 5. Efficiency vs. Load Current and Input
Voltage, VOUT = 3.15 V
86%
1000
90%
88%
2.5
2.7
3.0
3.3
86%
84%
82%
0
500
1000
1500
2000
VIN
VIN
VIN
VIN
94%
92%
90%
−40°C
+25°C
+85°C
88%
86%
0
2500
500
1000
1500
2000
2500
Load Current (mA)
Load Current (mA)
Figure 9. Efficiency vs. Load Current and Input
Voltage, VOUT = 3.5 V
Figure 10. Efficiency vs. Load Current and
Temperature, VIN = 3.0 V, VOUT = 3.5 V
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FAN48623
TYPICAL CHARACTERISTICS (continued)
Unless otherwise specified, TA = 25°C; circuit and components according to Figure 1.
96%
96%
94%
94%
90%
Efficiency
Efficiency
92%
88%
86%
84%
2.5
3.0
3.6
4.2
82%
80%
78%
0
500
1000
1500
2000
92%
90%
88%
VIN
VIN
VIN
VIN
−40°C
+25°C
+85°C
86%
84%
2500
0
500
Load Current (mA)
Figure 11. Efficiency vs. Load Current and Input
Voltage, VOUT = 5.0 V
4.0%
2500
0.0%
−40°C
+25°C
+85°C
3.0%
Output Regulation
Output Regulation
1.0%
2.0%
1.0%
0.0%
−1.0%
−1.0%
−2.0%
0
500
1000
1500
2000
2500
0
500
1000
1500
4.0%
4.0%
Output Regulation
2.5 VIN
2.7 VIN
3.0 VIN
2.0%
2500
Figure 14. Output Regulation vs. Load Current
and Temperature, VIN = 3.0 V, VOUT = 3.15 V
Figure 13. Output Regulation vs. Load Current
and Input Voltage, VOUT = 3.15 V
3.0%
2000
Load Current (mA)
Load Current (mA)
Output Regulation
2000
4.0%
2.0%
−2.0%
1500
Figure 12. Efficiency vs. Load Current and
Temperature, VIN = 3.6 V, VOUT = 5.0 V
2.5 VIN
2.7 VIN
3.0 VIN
3.0%
1000
Load Current (mA)
1.0%
0.0%
−1.0%
−40°C
+25°C
+85°C
3.0%
2.0%
1.0%
0.0%
−1.0%
−2.0%
0
500
1000
1500
2000
−2.0%
0
2500
500
1000
1500
2000
2500
Load Current (mA)
Load Current (mA)
Figure 15. Output Regulation vs. Load Current
and Input Voltage, VOUT = 3.3 V
Figure 16. Output Regulation vs. Load Current
and Temperature, VIN = 3.0 V, VOUT = 3.3 V
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FAN48623
TYPICAL CHARACTERISTICS (continued)
Unless otherwise specified, TA = 25°C; circuit and components according to Figure 1.
4.0%
Output Regulation
3.0%
Output Regulation
4.0%
2.5 VIN
2.7 VIN
3.0 VIN
3.3 VIN
2.0%
1.0%
0.0%
−40°C
+25°C
+85°C
3.0%
2.0%
1.0%
0.0%
−1.0%
−1.0%
−2.0%
0
500
1000
1500
2000
−2.0%
0
2500
500
2.5
3.0
3.6
4.2
3.0%
2.0%
0.0%
−1.0%
1000
1500
2000
2.0%
1.0%
0.0%
−1.0%
−2.0%
2500
0
500
1500
2000
2500
Figure 20. Output Regulation vs. Load Current
and Temperature, VIN = 3.6 V, VOUT = 5.0 V
Figure 19. Output Regulation vs. Load Current
and Input Voltage, VOUT = 5.0 V
220
200
−40°C
+25°C
+85°C
180
Quiescent Current (mA)
Quiescent Current (mA)
1000
Load Current (mA)
Load Current (mA)
160
140
120
100
2.5
2500
−40°C
+25°C
+85°C
3.0%
1.0%
500
2000
4.0%
VIN
VIN
VIN
VIN
Output Regulation
Output Regulation
4.0%
0
1500
Figure 18. Output Regulation vs. Load Current
and Temperature, VIN = 3.0 V, VOUT = 3.5 V
Figure 17. Output Regulation vs. Load Current
and Input Voltage, VOUT = 3.5 V
−2.0%
1000
Load Current (mA)
Load Current (mA)
3.0
3.5
4.0
180
160
140
120
2.5
4.5
−40°C
+25°C
+85°C
200
3.0
3.5
4.0
4.5
5.0
5.5
Input Voltage V)
Input Voltage V)
Figure 22. Quiescent Current vs. Input Voltage
and Temperature, VOUT = 5.0 V, Auto Bypass
Figure 21. Quiescent Current vs. Input Voltage
and Temperature, VOUT = 3.15 V, Auto Bypass
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FAN48623
TYPICAL CHARACTERISTICS (continued)
Unless otherwise specified, TA = 25°C; circuit and components according to Figure 1.
5
−40°C
+25°C
+85°C
10
Max Continuous Load (A)
Quiescent Current (mA)
12
8
6
4
2
0
2.5
3.5
3.0
4.0
4.5
4
3.3 VOUT, 25°C
3.3 VOUT, 60°C
3.3 VOUT, 85°C
5.0 VOUT, 25°C
5.0 VOUT, 60°C
5.0 VOUT, 85°C
5.2 VOUT, 25°C
5.2 VOUT, 60°C
5.2 VOUT, 85°C
3.5
3
2.5
2
1.5
1
0.5
0
2.5
4.5
3.0
2,500
Frequency (kHz)
Ripple (mV)
40
30
20
10
2.5 VIN
2.7 VIN
3.0 VIN
0
500
1000
1500
2000
2,000
1,500
1,000
2.5 VIN
2.7 VIN
3.0 VIN
500
0
2500
0
500
Load Current (mA)
1000
1500
2000
2500
Load Current (mA)
Figure 26. Frequency vs. Load Current and Input
Voltage, VOUT = 3.15 V
Figure 25. Output Ripple vs. Load Current and
Input Voltage, VOUT = 3.15 V
2,500
40
2,000
30
Frequency (kHz)
Ripple (mV)
4.5
Figure 24. Typical Maximum Continuous Load
vs. Input Voltage, Temperature and Output Voltage
Figure 23. Quiescent Current vs. Input Voltage
and Temperature, VOUT = 3.3 V, Forced Bypass
20
10
0
4.0
Input Voltage (V)
Input Voltage (V)
0
3.5
2.5 VIN
2.7 VIN
3.0 VIN
0
500
1000
1500
2000
1,500
1,000
2.5 VIN
2.7 VIN
3.0 VIN
500
0
2500
0
500
1000
1500
2000
2500
Load Current (mA)
Load Current (mA)
Figure 27. Output Ripple vs. Load Current
and Input Voltage, VOUT = 3.3 V
Figure 28. Frequency vs. Load Current and Input
Voltage, VOUT = 3.3 V
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FAN48623
TYPICAL CHARACTERISTICS (continued)
Unless otherwise specified, TA = 25°C; circuit and components according to Figure 1.
2.5
3.0
3.6
4.2
Ripple (mV)
40
3,000
VIN
VIN
VIN
VIN
2,500
Frequency (kHz)
50
30
2,000
1,000
2.5 VIN
10
500
3.0 VIN
3.6 VIN
0
0
20
4.2 VIN
0
500
1000
1500
2000
2500
0
500
Load Current (mA)
1000
1500
2000
2500
Load Current (mA)
Figure 30. Frequency vs. Load Current and Input
Voltage, VOUT = 5.0 V
Figure 29. Output Ripple vs. Load Current
and Input Voltage, VOUT = 5.0 V
VOUT (2 V/div)
VOUT (1 V/div)
IIN (500 mA/div)
IIN (500 mA/div)
EN (2 V/div)
EN (2 V/div)
PG (5 V/div)
100 ms/div
PG (5 V/div)
Figure 31. Startup, 50 W Load, VIN = 2.5 V,
VOUT = 3.15 V
100 ms/div
Figure 32. Startup, 50 W Load, VIN = 3.0 V,
VOUT = 5.0 V
VOUT (1 V/div)
IL (2 A/div)
IL (2 A/div)
VOUT (1 V/div)
PG (2 V/div)
5 ms/div
50 ms/div
PG (2 V/div)
Figure 33. Overload Protection, VIN = 3.0 V,
VOUT = 5.0 V
Figure 34. Output Fault, VIN = 3.0 V,
VOUT = 3.3 V
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FAN48623
TYPICAL CHARACTERISTICS (continued)
Unless otherwise specified, TA = 25°C; circuit and components according to Figure 1.
3.3 V
VOUT (200 mV/div)
VOUT (200 mV/div)
5.0 V
IOUT (1 A/div)
IOUT (1 A/div)
100 ms/div
100 ms/div
Figure 35. Load Transient, 150−2000 mA,
10 ms Edge, VIN = 3.0 V, VOUT = 3.3 V
Figure 36. Load Transient, 150−1000 mA,
10 ms Edge, VIN = 3.6 V, VOUT = 5.0 V
VOUT (50 mV/div)
VOUT (200 mV/div)
VIN (200 mV/div)
3.2 V
3.0 V
2.7 V
VIN (200 mV/div)
20 ms/div
20 ms/div
Figure 37. Line Transient, 3.0−3.6 VIN, 10 ms Edge,
500 mA Load, VOUT = 3.3 V
Figure 38. Line Transient, 2.7−3.0 VIN, 10 ms Edge,
500 mA Load, VOUT = 3.3 V
VOUT (100 mV/div)
3.3 V
VSEL (2 V/div)
20 ms/div
Figure 39. VSEL Step, VIN = 3 V, VOUT = 3.3 V,
500 mA Load
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FAN48623
CIRCUIT DESCRIPTION
FAN48623 is a synchronous boost regulator, typically
operating at 2.5 MHz in Continuous Conduction Mode
(CCM), which occurs at moderate to heavy load current and
low VIN voltages. At light load, the regulator operates at
Discontinuous Conduction Mode (DCM) to maintain high
efficiency.
FAN48623 uses a current−mode modulator to achieve
excellent transient response and smooth transitions between
CCM and DCM operation.
The regulator includes a Bypass Mode that automatically
activates when VIN is above the boost regulator’s set point.
Soft−Start Mode (SS)
Upon successful completion of the LIN Mode
(VOUT ≥VIN − 300 mV), SS Mode begins and the regulator
starts switching with boost valley current limited to 50% of
nominal level at Boost Mode.
During SS Mode, VOUT is ramped up by stepping the
internal reference. If VOUT fails to reach the voltage
required during the SS ramp sequence within 64 ms, a fault
state is declare
Boost Mode (BST)
This is a normal operating state of the regulator.
Bypass Mode (BPS)
If VIN is above VOUT_TARGET when the SS Mode
successfully completes, the device transitions directly to
BPS Mode.
Table 2. OPERATING STATES
Mode
Description
Invoked When
LIN
Linear Startup
VIN > VOUT
SS
Soft−Start Mode
VIN < VOUT < VOUT_TARGET
BST
Boost Operating Mode
VOUT = VOUT_TARGET
BPS
Bypass Mode
VIN > VOUT_TARGET
Table 4. EN AND BYP LOGIC TABLE
EN
BYP
Mode
VOUT
0
0
Shutdown
0
Startup and Shutdown (EN Pin)
If EN is LOW, all bias circuits are off and the regulator is
in Shutdown Mode. During shutdown, current flow is
prevented from VIN to VOUT, as well as reverse flow from
VOUT to VIN. During startup, keep DC current draw below
500 mA until the device successfully executes startup. It is
recommended not to connect EN directly to VIN but use a
GPIO voltage of 1.8 V to set the logic for the EN pin. The
following table describes the startup sequence.
1
LIN1
LIN2
SS
Exit
VIN > VUVLO,
EN = 1
VOUT > VIN − 300 mV
SS
TIMEOUT
LIN2
LIN1 Exit
VOUT > VIN − 300 mV
SS
TIMEOUT
FAULT
VOUT = VOUT_TARGET
BST
LIN1 or
LIN2 Exit
0
Forced Bypass
VIN
1
Auto Bypass
VOUT_TARGET or VIN
(if VIN > VOUT_TARGET)
The regulator enters the FAULT state under any of the
following conditions:
• VOUT fails to achieve the voltage required to advance
from LIN state to SS state.
• VOUT fails to achieve the voltage required to advance
from SS state to BST state.
• Boost valley current limit triggers for 2 ms during the
BST state.
• VIN to VOUT voltage drop exceeds 160 mV during BPS
state.
• VIN < VUVLO
If a fault is triggered, the regulator stops switching and
presents a high−impedance path between VIN and VOUT.
After waiting 20 ms, an automatic restart is attempted.
End Timeout
Mode
(ms)
Entry
Shutdown
0
FAULT State
Table 3. BOOST STARTUP SEQUENCE
Start
Mode
1
512
1024
Linear Startup (LIN)
When EN is HIGH and VIN > VUVLO, the regulator
attempts to bring VOUT within 300 mV of VIN using the
internal fixed current source from VIN (Q3). The current is
limited to the LIN1 (~1 A) set point.
If VOUT reaches VIN−300 mV during LIN1 Mode, SS
Mode is initiated. Otherwise, LIN1 times out after 512 ms
and LIN2 Mode is entered.
In LIN2 Mode, the current source is incremented to
approximately 2 A. If VOUT fails to reach VIN−300 mV after
1024 ms, a fault state is declared.
Power Good
Power good is defined as a 0−FAULT, 1−POWER GOOD,
open−drain output. The Power Good pin (PG) signals when
the regulator has successfully completed soft−start with no
faults occurring. Power Good also functions as a warning
flag for high die temperature.
• PG is released HIGH when the soft−start sequence is
successfully completed.
• Any FAULT state causes PG to be de−asserted.
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12
FAN48623
• PG is not asserted during Forced Bypass exit to Boost
hysteresis imposed at VOUT to prevent cycling between
modes. The corresponding input voltage at the transition
point is:
Mode until the soft−start sequence is successfully
completed.
Over−Temperature
ǒ
Ǔ
V IN v V OUT ) I LOAD @ DCR L ) R DS(ON)P ø R DS(ON)BYP * 50 mV
When the die temperature exceeds 125°C, PG de−asserts
(eq. 1)
and the output remains regulated. PG is re−asserted when the
device cools by approximately 20°C.
The regulator shuts down if the die temperature exceeds
150°C. Restart occurs when the IC has cooled by
approximately 20°C.
The Bypass Mode entry threshold has a 30 mV hysteresis
imposed at VOUT to prevent cycling between modes. The
transition from Boost Mode to Bypass Mode occurs at the
target VOUT + 30 mV. The corresponding input voltage is:
ǒ
Automatic Bypass
Ǔ
V IN v V OUT ) I LOAD @ DCR L ) R DS(ON)P ) 30 mV
In normal operation, the device automatically transitions
from Boost Mode to Bypass Mode if VIN goes above
VOUT_TARGET. In Bypass Mode, the device fully enhances
both Q1 and Q3 to provide a very low impedance path from
VIN to VOUT. Entry into the Bypass Mode is triggered
when VIN > VOUT_TARGET and no switching has occurred
during the past 10 ms. To soften the entry into Bypass Mode,
Q3 is driven as a linear current source for the first 5 ms.
Bypass Mode exit is triggered when VOUT reaches
VOUT_TARGET. During Automatic Bypass Mode, the device
is short−circuit protected by voltage comparator tracking the
voltage drop from VIN to VOUT; if the drop exceeds 160 mV,
a fault state is declared.
With sufficient load to enforce CCM operation, the
Bypass Mode to Boost Mode transition occurs at the target
VOUT. The Bypass Mode exit threshold has a 50 mV
(eq. 2)
Forced Bypass
Forced Bypass Mode is activated by pulling BYP pin
LOW. Forced Bypass Mode initiates with a current limit on
Q3 and then proceeds to the Bypass Mode with both Q1 and
Q3 fully enhanced. To prevent reverse current to the battery,
the device waits until output discharges below VIN before
entering Forced Bypass Mode.
After the transition is complete, most of the internal
circuitry is disabled to minimize quiescent current. OCP,
UVLO and OTP are inactive in Forced Bypass Mode.
By pulling BYP pin HIGH, the part transitions from
Forced Bypass Mode to Boost Mode. During the transition,
Q1 is off and Q3 is driven as a linear current source for the
first 5 ms before entering Boost Mode.
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13
FAN48623
APPLICATION INFORMATION
Output Capacitance (COUT)
current ripple to become higher under high loading as only
the valley of the inductor current ripple is controlled.
Stability
The effective capacitance (CEFF − Note 4) of small,
high−value, ceramic capacitors decrease as bias voltage
increases, as illustrated in Figure 40.
Startup Inrush Current Limit
Input current limiting is in effect during soft−start, which
limits the current available to charge COUT and any
additional capacitance on the VOUT line. If the output fails
to achieve regulation within the set limit, a FAULT occurs,
causing the circuit to shut down then restart after 20 ms. If
the total combined output capacitance is very high, the
circuit may not start on the first attempt, but eventually
achieves regulation if no load is present. If a high−current
load and high capacitance are both present during soft−start,
the circuit may fail to achieve regulation and continually
attempts soft−start, only to have the output capacitance
discharged by the load when in a FAULT state.
24
Capacitance (mF)
20
16
12
8
4
Output Voltage Ripple
Output voltage ripple is inversely proportional to COUT.
During tON, when the boost switch is on, all load current is
supplied by COUT. Output ripple is calculated as:
0
0
1
2
3
4
5
6
7
8
9
10
DC Bias (V)
Figure 40. CEFF for 22 mF, 0603, X5R, 10 V−Rated
Capacitor (TDK C1608X5R1A226M080AC)
V RIPPLE(P*P) + t ON @
and
Stable operation is guaranteed with the minimum value of
CEFF (CEFF(MIN)), as outlined in Table 5.
therefore:
Operating Conditions
ILOAD (mA)
CEFF(MIN) (mF)
3.15
0 to 2500
9
5.0
0 to 2500
6
ǒ
t ON + t SW @ D + t SW @ 1 *
Table 5. MINIMUM CEFF REQUIRED FOR STABILITY
VOUT (V)
I LOAD
C OUT
ǒ
V RIPPLE(P*P) + t SW @ 1 *
(eq. 3)
V IN
V OUT
V IN
V OUT
Ǔ
@
Ǔ
(eq. 4)
I LOAD
C OUT
(eq. 5)
and
t SW +
4. CEFF varies with manufacturer, material, and case size.
1
f SW
(eq. 6)
As can be seen from Equation 5, the maximum VRIPPLE
occurs when VIN is at minimum and ILOAD is at maximum.
Inductor Selection
Recommended nominal inductance value is 0.47 mH.
The FAN48623 employs valley−current limiting. Peak
inductor current can reach 6.5 A for a short duration during
overload conditions. Saturation effects cause the inductor
Voltage at VOUT
For applications where a foreign voltage source could be
applied at VOUT, care should be taken to ensure VOUT never
exceeds the Absolute Maximum Rating.
LAYOUT RECOMMENDATIONS
The layout recommendations below highlight various
layers using different colors.
To minimize spikes at VOUT, COUT must be placed as
close as possible to PGND and VOUT, as shown in
Figure 41.
For thermal reasons, it is suggested to maximize the pour
area for all planes other than SW. Especially the ground pour
should be set to fill all available PCB surface area and tied
to internal layers with a cluster of thermal vias.
Figure 41. Layout Recommendation
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14
FAN48623
Refer to the section below for detailed layout
recommendations for each layer.
VIN trace should go
through CIN before going
to VIN pins.
VOUT trace should be as wide
and as short as possible, for
low impedance.
Connect AGND directly to
GND layer through a via.
The ground area should be
made as large as possible
to help dissipate heat.
Put as many as possible vias
connected to ground plane (layer 2),
to help dissipate heat.
Figure 42. Top Layer
•
Layer 2 should be a solid ground layer, to shield VOUT
from capacitive coupling of the fast edges of SW node.
•
Logic signals can be routed on this layer.
Figure 43. Layer 2
SW trace should be as wide and as short
as possible, and be isolated with GND
area from any other sensitive traces.
Figure 44. Layer 3
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15
FAN48623
ORDERING INFORMATION
Part Number
Output Voltage
VSEL0/VSEL1
(Note 5)
Operating
Temperature
FAN48623UC315X
3.150 / 3.330
−40°C to 85°C
FAN48623UC32JX
3.20 / 3.413
FAN48623UC33X
3.300 / 3.489
JE
FAN48623UC35X
3.5 / 3.7
JF
FAN48623UC36FX
3.64 / 3.709
JG
FAN48623UC50X
5.000 / 5.286
JL
FAN48623UC50GX
5000 / 5.190
JM
Package
Shipping†
Device Marking
16−Ball, 4x4 Array, 0.4 mm Pitch,
250 mm Ball, Wafer−Level
Chip−Scale Package (WLCSP)
3000 /
Tape & Reel
JK
JD
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
5. Other output voltages are available on request. Please contact a onsemi representative.
PRODUCT−SPECIFIC DIMENSIONS
Product
D
E
X
Y
FAN48623UC315X
1.810 ±0.030
1.810 ±0.030
0.305
0.305
FAN48623UC32JX
1.810 ±0.030
1.810 ±0.030
0.305
0.305
FAN48623UC33X
1.810 ±0.030
1.810 ±0.030
0.305
0.305
FAN48623UC35X
1.810 ±0.030
1.810 ±0.030
0.305
0.305
FAN48623UC36FX
1.810 ±0.030
1.810 ±0.030
0.305
0.305
FAN48623UC50X
1.810 ±0.030
1.810 ±0.030
0.305
0.305
FAN48623UC50GX
1.810 ±0.030
1.810 ±0.030
0.305
0.305
TINYBOOST is a registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States
and/or other countries.
www.onsemi.com
16
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP16 1.81x1.81x0.586
CASE 567QZ
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13358G
WLCSP16 1.81x1.81x0.586
DATE 31 OCT 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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