Synchronous Regulator
with Bypass Mode,
TINYBOOST®,
2.5 MHz, 1500 mA
FAN48630
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Description
Features
• Few External Components: 0.47 mH Inductor and 0603 Case Size
•
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•
•
•
•
•
•
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Input and Output Capacitors
Input Voltage Range: 2.35 V to 5.5 V
Fixed Output Voltage Options: 3.0 V to 5.0 V
Maximum Continuous Load Current: 1500 mA at VIN of 2.6 V
Boosting VOUT to 3.5 V
Up to 96% Efficient
True Bypass Operation when VIN > VOUT_TARGET
Internal Synchronous Rectifier
Soft−Start with True Load Disconnect
Forced Bypass Mode
VSEL Control to Optimize Target VOUT
Short−Circuit Protection
Low Operating Quiescent Current
16−Bump, 0.4 mm Pitch WLCSP
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
WLCSP16 1.78x1.78x0.586
CASE 567SY
MARKING DIAGRAM
1
Pin−1
Mark
12
KK
X
Y
Z
2
K
K
X
Y
Z
= Alphanumeric Device Marking
= Lot Rune Code
= Alphabetical Year Code
= 2−weeks Date Code
= Assembly Plant Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Battery
VIN
+
VOUT
CIN
L1
The FAN48630 allows systems to take advantage of new battery
chemistries that can supply significant energy when the battery
voltage is lower than the required voltage for system power ICs. By
combining built−in power transistors, synchronous rectification, and
low supply current; this IC provides a compact solution for systems
using advanced Li−Ion battery chemistries.
The FAN48630 is a boost regulator designed to provide a minimum
output voltage from a single−cell Li−Ion battery, even when the
battery voltage is below system minimum. Output voltage regulation
is guaranteed to a maximum load current of 1500 mA. Quiescent
current in Shutdown Mode is less than 3 mA, which maximizes battery
life. The regulator transitions smoothly between Bypass and normal
Boost Mode. The device can be forced into Bypass Mode to reduce
quiescent current.
The FAN48630 is available in a 16−bump, 0.4 mm pitch,
Wafer−Level Chip−Scale Package (WLCSP).
0.47 mH
COUT
20 mF
PGND
4.7mF
SW
VSEL
SYSTEM
LO AD
FAN48630
AGND
EN
BYP
PG
Figure 1. Typical Application
Applications
• Boost for Low−Voltage Li−ion Batteries, Brownout Prevention,
Boosted Audio, USB OTG, and LTE / 3G RF Power
• Cell Phones, Smart Phones, Portable Instruments
© Semiconductor Components Industries, LLC, 2015
October, 2019 − Rev. 2
1
Publication Order Number:
FAN48630/D
FAN48630
Table 1. ORDERING INFORMATION
Part Number
Output Voltage
(Note 1)
VSELO/VSEL1
Soft −
Start
Forced
Bypass
Operating
Temperature
FAN48630UC315X
3.15 / 3.33
FAST
Low IQ
−40 to 85°C
FAN48630BUC315X
(Note 2)
3.15 / 3.33
FAST
Low IQ
FAN48630UC33X
3.30 / 3.49
FAST
Low IQ
FAN48630BUC33X
(Note 2)
3.30 / 3.49
FAST
Low IQ
JX
FAN48630BUC34X
(Note 2)
3.20 / 3.40
FAST
Low IQ
JR
FAN48630UC35X
3.50 / 3.70
FAST
Low IQ
J6
FAN48630UC37AX
3.70 / 3.77
FAST
Low IQ
JT
FAN48630UC45X
4.50 / 4.76
SLOW
OCP On
J7
FAN48630UC50X
5.00 / 5.29
SLOW
OCP On
J8
Package
Shipping†
16−Ball, 4x4 Array, Tape & Reel
0.4mm Pitch, 250um
Ball, Wafer−Level
Chip−Scale
Package (WLCSP)
Top
Marking
J5
J5
JX
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
1. Other output voltages are available on request. Please contact a ON Semiconductor representative.
2. The FAN48630BUC315X, FAN48630BUC33X and FAN48630BUC34X include backside lamination.
TYPICAL APPLICATION
Q3B Q3A
VIN
CIN
Q3
L1
Bypass
Control
Q1B
Q1A
SW
VOUT
Q2
GND
COUT
Q1
Synchronous
Rectifier Control
VSEL
EN
BYP
Modulator Logic
and Control
PG
Figure 2. Block Diagram
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2
FAN48630
Table 2. RECOMMENDED COMPONENTS
Component
Description
Vendor
Parameter
Typ.
Unit
L1
0.47 mH, 30%
Toko: DFE201612C
DFR201612C
Cyntec: PIFE20161B
L
0.47
mH
DCR (Series R)
40
mW
CIN
4.7 mF, 10%, 6.3 V, X5R, 0603
Murata: GRM188R60J475K
TDK: C1608X5R0J475K
C
4.7
mF
COUT
2 x 10 mF, 20%, 10 V, X5R, 0603
TDK: C1608X5R1A106M
C
20
mF
PIN CONFIGURATION
EN
PG
A1
A2
VSEL AGND
B1
VIN
B3
C2
C3
A2
A1
B4
B4
B3
B2
B1
C4
C4
C3
C2
C1
D4
D4
D3
D2
D1
SW
AGND
D1
A3
VOUT
B2
BYP
C1
A4
A4
A3
PGND
D2
D3
Figure 3. Top Through View (Bumps Down)
Figure 4. Bottom View
Table 3. PIN DEFINITIONS
Pin #
Name
A1
EN
Enable. When this pin is HIGH, the circuit is enabled (Note 3).
A2
PG
Power Good. This is an open−drain output. PG is actively pulled LOW if output falls out of
regulation due to overload or if thermal protection threshold is exceeded.
A3–A4
VIN
Input Voltage. Connect to Li−Ion battery input power source (Note 3).
B1
VSEL
Output Voltage Select. When boost is running, this pin can be used to select output voltage.
B2, C2, D1
AGND
Analog Ground. This is the signal ground reference for the IC. All voltage levels are
measured with respect to this pin.
B3–B4
VOUT
Output Voltage. Place COUT as close as possible to the device.
C1
BYP
Bypass. This pin can be used to activate Forced Bypass Mode. When this pin is LOW,
the bypass switches (Q3 and Q1) are turned on and the IC is otherwise inactive.
C3–C4
SW
Switching Node. Connect to inductor.
D2–D4
PGND
Description
Power Ground. This is the power return for the IC. The COUT bypass capacitor should be
returned with the shortest path possible to these pins.
3. Do not connect the EN pin to VIN. A logic voltage of 1.8 V should control the EN pin and enable/disable the device.
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FAN48630
Table 4. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VIN
VIN Input Voltage
VOUT
Min.
Max.
Unit
−0.3
6.5
V
VOUT Output Voltage
SW Node
6.0
V
DC
−0.3
8.0
V
Transient: 10 ns, 3 MHz
−1.0
8.0
V
6.5
V
Other Pins
−0.3
(Note 4)
ESD
Electrostatic Discharge Protection Level
Human Body Model per JESD22−A114
3.0
Charged Device Model per JESD22−C101
kV
1.5
kV
TJ
Junction Temperature
−40
+150
°C
TSTG
Storage Temperature
−65
+150
°C
+260
°C
TL
Lead Soldering Temperature, 10 Seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
4. Lesser of 6.5 V or VIN + 0.3 V.
Table 5. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min.
Max.
Unit
VIN
Supply Voltage
2.35
5.5
V
IOUT
Output Current
0
1500
mA
TA
Ambient Temperature
−40
+85
°C
TJ
Junction Temperature
−40
+125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 6. THERMAL CHARACTERISTICS
Symbol
Typ.
Unit
θJA
Junction−to−Ambient Thermal Resistance
Parameter
80
°C/W
θJB
Junction−to−Board Thermal Resistance
42
Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with four−layer Fairchild® evaluation
boards (1 oz copper on all layers). Special attention must be paid not to exceed junction temperature TJ(max) at a given ambient temperate TA.
Table 7. ELECTRICAL CHARACTERISTICS
Recommended operating conditions, unless otherwise noted, circuit per Figure 1, VIN = 2.35 V to VOUT, TA = −40°C to 85°C. Typical
values are given VIN = 3.0 V and TA = 25°C.
Parameter
Symbol
IQ
V
IN
Quiescent Current
Typ.
Max.
Unit
Bypass Mode VOUT = 3.5 V, VIN = 4.2 V
Condition
140
190
μA
Boost Mode VOUT = 3.5 V, VIN = 2.5 V
150
250
μA
Shutdown: EN = 0, VIN = 3.0 V
1.5
5.0
μA
Low IQ
4
10
μA
OCP On
45
90
μA
0.2
1.0
μA
Forced Bypass Mode
VOUT = 3.5 V
VIN = 3.5 V
ILK
Min.
VOUT to VIN Reverse Leakage
VOUT = 5 V, EN = 0
ILK_OUT
VOUT Leakage Current
VOUT = 0, EN = 0, VIN = 4.2 V
0.1
1.0
μA
VUVLO
Under−Voltage Lockout
VIN Rising
2.20
2.35
V
VUVLO_HYS
Under−Voltage Lockout Hysteresis
200
VPG(OL)
PG Low
IPG = 5 mA
IPG_LK
PG Leakage Current
VPG = 5 V
VIH
Logic Level High EN, VSEL, BYP
VIL
Logic Level Low EN, VSEL, BYP
mV
0.4
V
1
μA
1.2
V
0.4
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4
V
FAN48630
Table 7. ELECTRICAL CHARACTERISTICS (continued)
Recommended operating conditions, unless otherwise noted, circuit per Figure 1, VIN = 2.35 V to VOUT, TA = −40°C to 85°C. Typical
values are given VIN = 3.0 V and TA = 25°C.
Symbol
RLOW
IPD
Parameter
Condition
Logic Control Pin Pull Downs
(LOW Active)
BYP, VSEL, EN
Min.
Typ.
Max.
Unit
kΩ
300
Weak Current Source Pull−Down
BYP, VSEL, EN
VREG
Output Voltage Accuracy
Referred to GND, DC,
VOUT−VIN > 100 mV
VTRSP
Load Transient Response
500–1250 mA, VIN = 3.6 V,
VOUT = 5.0 V
±4
%
tON
On−Time
VIN = 3.0 V, VOUT = 3.5 V,
Load > 1000 mA
80
ns
fSW
Switching Frequency
VIN = 3.6 V, VOUT = 5.0 V,
Load = 1000 mA
2.0
2.5
3.0
MHz
2.6
2.9
3.1
A
IV_LIM
100
–2
nA
4
%
Boost Valley Current Limit
VIN = 2.6 V
IV_LIM_SS
Boost Valley Current Limit During SS
VIN = 2.6 V
1.6
A
VMIN_1.5A
Minimum VIN for 1500 mA Load
(Short Term)
VOUT = 5.0 V, TJ < 120°C
3.0
V
VOUT = 4.5 V, TJ < 120°C
2.8
V
VOUT = 3.5 V, TJ < 120°C
2.35
V
VOUT = 3.15 V, TJ < 120°C
2.35
V
LIN1
Slow
350
mA
Fast
800
mA
Slow
700
mA
Fast
1600
mA
Slow, 50 Ω Load
1300
μs
Fast, 50 Ω Load
600
μs
VIN = 5.0 V, VIN − VOUT
200
ISS_PK
Soft−Start Input Peak Current Limit
LIN2
tSS
Soft−Start EN HIGH to Regulation
VOCP
OCP Comparator Threshold
VOVP
Output Over−Voltage Protection Threshold
6.0
VOVP_HYS
Output Over−Voltage Protection Hysteresis
300
RDS(ON)N
N−Channel Boost Switch RDS(ON)
VIN = 3.5 V, VOUT = 3.5 V
85
120
mW
RDS(ON)P
P−Channel Sync Rectifier RDS(ON)
VIN = 3.5 V, VOUT = 3.5 V
65
85
mW
VIN = 3.5 V, VOUT = 3.5 V
65
85
mW
RDS(ON)P_BYP P−Channel Bypass Switch RDS(ON)
mV
6.3
V
mV
T120A
T120 Activation Threshold
120
°C
T120R
T120 Release Threshold
100
°C
T150T
T150 Threshold
150
°C
T150H
T150 Hysteresis
20
°C
FAULT Restart Timer
20
ms
tRST
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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FAN48630
TYPICAL CHARACTERISTICS
Unless otherwise specified; VIN = 3.6 V, VOUT = 5 V, and TA = 25°C; circuit and components according to Figure 1.
100%
96%
94%
92%
Efficiency
Efficiency
96%
92%
88%
2.5 VIN
3.0 VIN
84%
90%
88%
86%
84%
3.3 VIN
−40C
82%
4.2 VIN
+25C
+85C
80%
80%
0
250
500
750
1000
1250
0
1500
250
500
750
1000
1250
1500
Load Current (mA)
Load Current (mA)
Figure 5. Efficiency vs. Load Current
and Input Voltage, VOUT = 3.5 V
Figure 6. Efficiency vs. Load Current and
Temperature, VIN = 3.0 V, VOUT = 3.5 V
96%
96%
92%
92%
Efficiency
Efficiency
88%
84%
88%
84%
80%
2.5 VIN
3.0 VIN
76%
−40C
80%
3.6 VIN
+25C
4.2 VIN
72%
0
250
500
750
1000
1250
+85C
76%
1500
0
250
500
750
1000
1250
Load Current (mA)
Load Current (mA)
Figure 7. Efficiency vs. Load Current
and Input Voltage
Figure 8. Efficiency vs. Load Current
and Temperature
1500
100%
100%
96%
96%
Efficiency
Efficiency
92%
92%
88%
88%
84%
5.0 VOUT
4.5 VOUT
3.5 VOUT
5.0 VOUT
84%
4.5 VOUT
80%
3.5 VOUT
3.15 VOUT
3.15 VOUT
80%
2.0
2.5
3.0
3.5
4.0
76%
2.0
4.5
Input Voltage (V)
2.5
3.0
3.5
4.0
Input Voltage (V)
Figure 9. Efficiency vs. Input Voltage
and Output Voltage, 200 mA Load
Figure 10. Efficiency vs. Input Voltage
and Output Voltage, 1000 mA Load
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4.5
FAN48630
3
3
2
2
Output Regulation (%)
Output Regulation (%)
TYPICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified; VIN = 3.6 V, VOUT = 5 V, and TA = 25°C; circuit and components according to Figure 1.
1
0
2.5 VIN
3.0 VIN
−1
1
0
−40C
−1
3.6 VIN
+25C
4.2 VIN
−2
0
250
500
750
1000
1250
+85C
−2
1500
0
250
Load Current (mA)
1250
1500
−40C Auto
+25C Auto
+85C Auto
−40C Bypass
+25C Bypass
+85C Bypass
200
Input Current (
Input Current (
250
150
100
50
150
100
50
0
0
2.0
2.5
3.0
3.5
4.0
4.5
2.0
2.5
Input Voltage (V)
50
2,500
Switching Frequency (KHz)
3,000
40
30
20
2.5 VIN
3.0 VIN
10
3.6 VIN
4.2 VIN
0
250
500
750
3.5
4.0
4.5
Figure 14. Quiescent Current vs. Input Voltage,
Temperature and Mode, VOUT = 3.5 V,
Forced Bypass, Low IQ
60
0
3.0
Input Voltage (V)
Figure 13. Quiescent Current vs. Input Voltage,
Temperature and Mode,
VOUT = 5.0 V, Forced Bypass, OCP Active
Output Ripple (mVpp)
1000
Figure 12. Output Regulation vs. Load
Current and Temperature (Normalized to
3.6 VIN, 500 mA Load, TA = 255C)
−40C Auto
+25C Auto
+85C Auto
−40C Bypass
+25C Bypass
+85C Bypass
200
750
Load Current (mA)
Figure 11. Output Regulation vs.
Load Current and Input Voltage
(Normalized to 3.6 VIN, 500 mA Load)
250
500
1000
1250
2,000
1,500
1,000
2.5 VIN
3.0 VIN
500
3.6 VIN
4.2 VIN
0
1500
0
Load Current (mA)
250
500
750
1000
1250
Load Current (mA)
Figure 15. Output Ripple vs. Load Current
and Input Voltage
Figure 16. Frequency vs. Load Current
and Input Voltage
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1500
FAN48630
TYPICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified; VIN = 3.6 V, VOUT = 5 V, and TA = 25°C; circuit and components according to Figure 1.
Figure 17. Startup, 50 Load
Figure 18. Startup, 50 Load,
VIN = 2.5 V, VOUT = 3.5 V
Figure 20. Load Transient, 100−500 mA,
100 ns Edge
Figure 19. Overload Protection
Figure 21. Load Transient, 500−1250 mA,
100 ns Edge
Figure 22. Load Transient, 100−500 mA,
100 ns Edge, VIN = 3 V, VOUT = 3.5 V
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FAN48630
TYPICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified; VIN = 3.6 V, VOUT = 5 V, and TA = 25°C; circuit and components according to Figure 1.
Figure 23. Transient Overload, 500−1950 mA,
100 ns Edge, VIN = 3 V, VOUT = 3.5 V
Figure 24. Line Transient, 3.0−3.6 VIN,
10 s Edge, 500 mA Load, VOUT = 3.15 V
Figure 25. Line Transient, 3.0−3.6 VIN,
10 s Edge, 1,000 mA Load, VOUT = 3.5 V
Figure 26. Line Transient, 3.3−3.9 VIN,
10 s Edge, 500 mA load, VOUT = 3.5 V
Figure 27. Bypass Entry / Exit, Slow VIN Ramp
1 ms Edge, 500 mA Load, VOUT = 3.5 V, 3.2 − 3.8 VIN
Figure 28. VSEL Step, VIN = 3 V,
VOUT = 3.5 V, 500 mA Load
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FAN48630
CIRCUIT DESCRIPTION
internal fixed current source from VIN (Q3). The current is
limited to LIN1 set point.
If VOUT reaches VIN−300 mV during LIN1 Mode, the SS
state is initiated. Otherwise, LIN1 times out after 512 ms and
LIN2 Mode is entered.
In LIN2 Mode, the current source is incremented to 2 A.
If VOUT fails to reach VIN−300 mV after 1024 ms, a fault
condition is declared.
FAN48630 is a synchronous boost regulator, typically
operating at 2.5 MHz in Continuous Conduction Mode
(CCM), which occurs at moderate to heavy load current and
low VIN voltages. The regulator includes a Bypass Mode
that activates when VIN is above the boost regulator’s
setpoint.
In anticipation of a heavy load transition, the setpoint can
be adjusted upward by fixed amounts with the VSEL pin to
reduce the required system headroom during lighter−load
operation to save power.
SS State
Upon the successful completion of the LIN state
(VOUT ≥ VIN−300 mV), the regulator begins switching with
boost pulses current limited to 50% of nominal level.
During SS state, VOUT is ramped up by stepping
the internal reference. If VOUT fails to reach regulation
during the SS ramp sequence for more than 64 ms, a fault
condition is declared. If large COUT is used, the reference is
automatically stepped slower to avoid excessive input
current draw.
Table 8. OPERATING STATES
Mode
Description
Invoked When
LIN
Linear Startup
VIN > VOUT
SS
Boost Soft−Start
VOUT < VOUT_TARGET
BST
Boost Operating Mode
VOUT = VOUT_TARGET
BPS
Bypass Mode
VIN > VOUT_TARGET
BST State
This is a normal operating state of the regulator.
Boost Mode
The FAN48630 uses a current−mode modulator to
achieve excellent transient response and smooth transitions
between CCM and Discontinuous Conduction Mode
(DCM) operation. During CCM operation, the device
maintains a switching frequency of about 2.5 MHz.
In light−load operation (DCM), frequency is reduced to
maintain high efficiency.
BPS State
If VIN is above VREG when the SS Mode successfully
completes, the device transitions directly to BPS Mode.
FAST and SLOW Soft−Start Options
The fast startup versions feature EN to regulation time of
600 ms. LIN1 and LIN2 phase currents are doubled
compared to SLOW options, SS phase is also faster.
Slow startup achieves EN to regulation time of 1300 ms to
reduce inrush current.
Table 9. BOOST STARTUP SEQUENCE
Start
State
LIN1
Entry
Exit
End State
VIN >
UVLO,
EN = 1
VOUT >
VIN−300 mV
SS
LIN2
LIN2
SS
LIN1 Exit
LIN1 or
LIN2 Exit
VOUT >
VIN−300 mV
SS
TIMEOUT
FAULT
VOUT =
VOUT_TARGET
BST
OVERLOAD
TIMEOUT
FAULT
Timeout
(s)
Table 10. OPERATING STATES
512
EN
BYP
Mode
VOUT
0
0
Shutdown
0
1
Shutdown
0
0
Forced Bypass
VIN
Auto Bypass
VOUT_TARGET or VIN
(or VIN > VOUT_TARGET
1
1024
1
FAULT State
64
The regulator enters the FAULT state under any of the
following conditions:
• VOUT fails to achieve the voltage required to advance
from LIN state to SS state.
• VOUT fails to achieve the voltage required to advance
from SS state to BST state.
• Boost current limit triggers for 2 ms during the BST
state.
• VDS protection threshold is exceeded during BPS state.
Shutdown and Startup
If EN is LOW, all bias circuits are off and the regulator is
in Shutdown Mode. During shutdown, current flow is
prevented from VIN to VOUT, as well as reverse flow from
VOUT to VIN. During startup, it is recommended to keep DC
current draw below 500 mA.
LIN State
When EN is HIGH and VIN > UVLO, the regulator
attempts to bring VOUT within 300 mV of VIN using the
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10
FAN48630
• PG is released HIGH when the soft−start sequence is
Once a fault is triggered, the regulator stops switching and
presents a high−impedance path between VIN and VOUT.
After waiting 20 ms, a restart is attempted.
•
Power Good
Power good is 0 FAULT, 1 POWER GOOD, open−drain
output.
The Power good pin is provided for signaling the system
when the regulator has successfully completed soft−start
and no faults have occurred. Power good also functions as
an early warning flag for high die temperature and overload
conditions.
•
Forced Bypass
Entry to Forced Bypass Mode initiates with a current limit
on Q3 and then proceeds to a true bypass state. To prevent
reverse current to the battery, the device waits until output
discharges below VIN before entering Forced Bypass
Mode.
For Low−IQ Forced Bypass versions, after the transition
is complete, most of the internal circuitry is disabled to
minimize quiescent current draw. Short−circuit, UVLO,
output OVP and over−temperature protections are inactive
in Forced Bypass Mode.
For OCP−On Forced Bypass versions, during Forced
Bypass Mode, the device is short−circuit protected by
a voltage comparator tracking the voltage drop from VIN to
VOUT. If the drop exceeds 200 mV, a FAULT is declared.
The over−temperature protection is also active.
Over−Temperature
The regulator shuts down when the die temperature
exceeds 150°C. Restart occurs when the IC has cooled by
approximately 20°C.
Bypass Operation
In normal operation, the device automatically transitions
from Boost Mode to Bypass Mode, if VIN goes above target
VOUT. In Bypass Mode, the device fully enhances both Q1
and Q3 to provide a very low impedance path from VIN to
VOUT. Entry to the Bypass Mode is triggered by condition
where VIN > VOUT and no switching has occurred during
past 5 ms. To soften the entry to Bypass Mode, Q3 is driven
as a linear current source for the first 5 ms. Bypass Mode exit
is triggered when VOUT reaches the target VOUT voltage.
During Automatic Bypass Mode, the device is short−circuit
protected by voltage comparator tracking the voltage drop
from VIN to VOUT; if the drop exceeds 200 mV, FAULT is
declared.
With sufficient load to enforce CCM operation, the
Bypass Mode to Boost Mode transition occurs at the target
VOUT. The corresponding input voltage at the transition
point is:
V IN v V OUT ) I LOAD * (DCR L ) R DS(ON)P)ŦR DS(ON)BYP
successfully completed.
PG is pulled LOW when PMOS current limit has
triggered for 64 ms OR the die the temperature exceeds
120°C. PG is re−asserted when the device cools below
to 100°C.
Any FAULT condition causes PG to be de−asserted.
VSEL
VSEL can be asserted in anticipation of a positive load
transient. Raising VSEL increases VOUT_TARGET by a fixed
amount and VOUT is stepped to the corresponding target
output voltage in 20 ms. The functionality can also be utilized
to mitigate undershoot during severe line transients, while
minimizing VOUT during more benign operating conditions
to save power.
EN
Setting the EN pin voltage below 0.4 V disables the part.
Placing the voltage above 1.2 V enables the part. Do not
connect the EN pin to VIN. A logic voltage of 1.8 V should
control the EN pin and enable / disable the device.
The EN pin should be pulled HIGH after the VIN voltage has
reached a minimum voltage of 2.3 V.
(eq. 1)
The Bypass Mode entry threshold has 25 mV hysteresis
imposed at VOUT to prevent cycling between modes. The
transition from Boost Mode to Bypass Mode occurs at the
target VOUT+25 mV. The corresponding input voltage is:
V IN w V OUT ) 25mV ) I LOAD * (DCR L ) R DS(ON)P) (eq. 2)
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11
FAN48630
APPLICATION INFORMATION
Output Capacitance (COUT)
Output Voltage Ripple
Output voltage ripple is inversely proportional to COUT.
During tON, when the boost switch is on, all load current is
supplied by COUT. Output ripple is calculated as:
Stability
The effective capacitance (CEFF) of small, high−value,
ceramic capacitors decreases as bias voltage increases.
FAN48630 is guaranteed for stable operation with the
minimum value of CEFF (CEFF(MIN)) outlined in Table 11
below.
V RIPPLE(P*P) + t ON *
and
ǒ
t ON + t SW * D + t SW * 1 *
Table 11. MINIMUM CEFF REQUIRED FOR STABILITY
Operating Conditions
therefore:
VOUT (V)
ILOAD (mA)
CEFF(MIN) (F
3.15
0 to 1500
12
3.5
0 to 1500
9
4.5 and 5
0 to 1500
6
I LOAD
C OUT
ǒ
V RIPPLE(P*P) + t SW * 1 *
(eq. 3)
V IN
V OUT
Ǔ
Ǔ
I LOAD
V IN
*
V OUT
C OUT
(eq. 4)
(eq. 5)
and
t SW +
CEFF varies with manufacturer, material, and case size.
1
f SW
(eq. 6)
As can be seen from eq. 5, the maximum VRIPPLE occurs
when VIN is at minimum and ILOAD is at maximum.
Inductor Selection
Recommended nominal inductance value is 0.47 mH.
FAN48630 employs valley−current limiting; peak
inductor current can reach 3.8 A for a short duration during
overload conditions. Saturation effects cause the inductor
current ripple to become higher under high loading as only
valley of the inductor current ripple is controlled.
For
FAN48630UC315X,
FAN48630BUC315X,
FAN48630UC33X and FAN48630BUC33X, a 0.33 mH
inductor can be used for improved transient performance.
Layout Recommendations
The layout recommendations below highlight various
top−copper pours using different colors.
To minimize spikes at VOUT, COUT must be placed as
close as possible to PGND and VOUT, as shown in
Figure 29.
For thermal reasons, it is suggested to maximize the pour
area for all planes other than SW. Especially the ground pour
should be set to fill all available PCB surface area and tied
to internal layers with a cluster of thermal vias.
Startup
Input current limiting is in effect during soft−start, which
limits the current available to charge COUT and any
additional capacitance on the VOUT line. If the output fails
to achieve regulation within the limits described in the
Startup section, a FAULT occurs, causing the circuit to shut
down then restart after a significant time period. If the total
combined output capacitance is very high, the circuit may
not start on the first attempt, but eventually achieves
regulation if no load is present. If a high−current load and
high capacitance are both present during soft−start, the
circuit may fail to achieve regulation and continually
attempts soft−start, only to have the output capacitance
discharged by the load when in a FAULT state.
Figure 29. Layout Recommendation
Table 12. PRODUCT−SPECIFIC DIMENSIONS
D
E
X
Y
1.780 ±0.030
1.780 ±0.030
0.290
0.290
TINYBOOST is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
FAIRCHILD is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
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12
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
WLCSP16 1.78x1.78x0.586
CASE 567SY
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON16621G
WLCSP16 1.78x1.78x0.586
DATE 30 NOV 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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