FAN48632UC33X

Pulsed-Load Synchronous Regulator with Bypass Mode for GSM PA Supply, TINYBOOST), 2.5 MHz, 2.0 A FAN48632 www.onsemi.com Description Features • Few External Components: 0.47 mH Inductor and 0603 Case Size • • • • • • • • • • • • • • Input and Output Capacitors Input Voltage Range: 2.35 V to 5.5 V Fixed Output Voltage: 3.3 V to 3.5 V Maximum Continuous Load Current of: 1.5 A at VIN of 2.6 V Maximum Pulsed Load Current of: 2.0 A for GSM 217 Hz Repetition Rate, boosting VOUT to 3.3 V or 3.5 V Up to 96% Efficient True Bypass Operation when VIN > Target VOUT Internal Synchronous Rectifier Soft−Start with True Load Disconnect Forced Bypass Mode VSEL Control to Optimize Target VOUT Short−Circuit Protection Low Operating Quiescent Current 16−Bump, 0.4 mm Pitch WLCSP These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant WLCSP16 1.78x1.78x0.586 CASE 567SY MARKING DIAGRAM 1 Pin−1 Mark 12 KK X Y Z 2 K K X Y Z = Alphanumeric Device Marking = Lot Run Code = Alphabetical Year Code = 2−weeks Date Code = Assembly Plant Code ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. VIN Battery + VOUT CIN L1 The FAN48632 allows systems to take advantage of new battery chemistries that can supply significant energy when the battery voltage is lower than the required voltage for system power ICs. By combining built−in power transistors, synchronous rectification, and low supply current; this IC provides a compact solution for systems using advanced Li−Ion battery chemistries. The FAN48632 is a boost regulator designed to provide a minimum output voltage (VOUT(MIN)) from a single−cell Li−Ion battery, even when the battery voltage is below system minimum. In boost mode, output voltage regulation is guaranteed to a maximum load current of 1.5 A continuous and 2.0 A pulsed. Quiescent current in Shutdown Mode is less than 3 mA, which maximizes battery life. The regulator transitions smoothly between Bypass and normal Boost Mode. The device can be forced into Bypass Mode to reduce quiescent current. The FAN48632 is available in a 16−bump, 0.4 mm pitch, Wafer−Level Chip−Scale Package (WLCSP). 0.47 mH COUT 40 mF PGND 10mF SW SYSTEM LO AD FAN48632 VSEL AGND EN BYP PG Figure 1. Typical Application Applications • Boost for Low−Voltage Li−ion Batteries, Brownout Prevention, Supply GSM RF PA • Cell Phones, Smart Phones, Tablets © Semiconductor Components Industries, LLC, 2013 July, 2021 − Rev. 2 1 Publication Order Number: FAN48632/D FAN48632 Table 1. ORDERING INFORMATION Output Voltage VSELO/VSEL1 Soft − Start Forced Bypass Operating Temperature FAN48632UC33X 3.30 / 3.49 FAST Low IQ −40 to 85°C FAN48632BUC33X (Note 1) 3.30 / 3.49 FAST Low IQ FAN48632UC35X 3.50 / 3.70 FAST Low IQ Part Number Package Shipping† 16−Ball, 4x4 Array, 0.4 mm 3000 / Tape & Reel Pitch, 250 mm Ball, Wafer−Level Chip−Scale Package (WLCSP) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 1. The FAN48632BUC33X includes backside lamination. TYPICAL APPLICATION Q3B Q3A VIN CIN Q3 L1 Bypass Control Q1B Q1A SW VOUT Q2 COUT Q1 Synchronous Rectifier Control GND VSEL EN Modulator Logic and Control BYP PG Figure 2. Block Diagram Table 2. RECOMMENDED COMPONENTS Component Description Vendor Parameter Typ. Unit L1 0.47 mH, 30% Toko: DFE201612C DFR201612C Cyntec: PIFE20161B L 0.47 mH DCR (Series R) 40 mW CIN 10 mF, 10%, 10 V, X5R, 0603 TDK: C1608X5R1A106K C 10 mF COUT 2 x 22 mF, 20%, 6.3 V, X5R, 0603 TDK: C1608X5R0J226M C 44 mF www.onsemi.com 2 FAN48632 PIN CONFIGURATION EN PG A1 A2 VSEL AGND B1 VIN B3 C2 C3 A2 A1 B4 B4 B3 B2 B1 C4 C4 C3 C2 C1 D4 D4 D3 D2 D1 SW AGND D1 A3 VOUT B2 BYP C1 A4 A4 A3 PGND D2 D3 Figure 3. Top Through View (Bumps Down) Figure 4. Bottom View (Bumps Up) Table 3. PIN DEFINITIONS Pin # Name A1 EN Enable. When this pin is HIGH, the circuit is enabled (Note 2). Description A2 PG Power Good. This is an open−drain output. PG is actively pulled LOW if output falls out of regulation due to overload or if thermal protection threshold is exceeded. A3–A4 VIN Input Voltage. Connect to Li−Ion battery input power source (Note 2). B1 VSEL Output Voltage Select. When boost is running, this pin can be used to select output voltage. B2, C2, D1 AGND Analog Ground. This is the signal ground reference for the IC. All voltage levels are measured with respect to this pin. B3–B4 VOUT Output Voltage. Place COUT as close as possible to the device. C1 BYP Bypass. This pin can be used to activate Forced Bypass Mode. When this pin is LOW, the bypass switches (Q3 and Q1) are turned on and the IC is otherwise inactive. C3–C4 SW Switching Node. Connect to inductor. D2–D4 PGND Power Ground. This is the power return for the IC. The COUT bypass capacitor should be returned with the shortest path possible to these pins. 2. The EN pin can be tied to VIN, but it is recommended to tie EN to the 1.8 V logic voltage. www.onsemi.com 3 FAN48632 Table 4. ABSOLUTE MAXIMUM RATINGS Symbol Parameter VIN VIN Input Voltage VOUT Min. Max. Unit −0.3 6.5 V VOUT Output Voltage SW Node 6.0 V DC −0.3 8.0 V Transient: 10 ns, 3 MHz −1.0 8.0 V 6.5 V Other Pins −0.3 (Note 3) ESD Electrostatic Discharge Protection Level Human Body Model per JESD22−A114 3.0 Charged Device Model per JESD22−C101 kV 1.5 kV TJ Junction Temperature −40 +150 °C TSTG Storage Temperature −65 +150 °C +260 °C TL Lead Soldering Temperature, 10 Seconds Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3. Lesser of 6.5 V or VIN + 0.3 V. Table 5. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min. Max. Unit VIN Supply Voltage 2.35 5.5 V IOUT Output Current 0 1500 mA TA Ambient Temperature −40 +85 °C TJ Junction Temperature −40 +125 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. Table 6. THERMAL CHARACTERISTICS Symbol Typ. Unit θJA Junction−to−Ambient Thermal Resistance Parameter 80 °C/W θJB Junction−to−Board Thermal Resistance 42 Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with four−layer ON Semiconductor evaluation boards (1 oz copper on all layers). Special attention must be paid not to exceed junction temperature TJ(max) at a given ambient temperature TA. www.onsemi.com 4 FAN48632 Table 7. ELECTRICAL CHARACTERISTICS Recommended operating conditions, unless otherwise noted, circuit per Figure 1, VIN = 2.35 V to VOUT, TA = −40°C to 85°C. Typical values are given VIN = 3.0 V and TA = 25°C. Symbol IQ Parameter VIN Quiescent Current Condition Typ. Max. Unit Bypass Mode VOUT = 3.5 V, VIN = 4.2 V 140 190 μA Boost Mode VOUT = 3.5 V, VIN = 2.5 V 150 250 μA Shutdown: EN = 0, VIN = 3.0 V 1.5 5.0 μA 4 10 μA Forced Bypass Mode VIN = 3.5 V Min. Low IQ VOUT to VIN Reverse Leakage VOUT = 5 V, EN = 0 0.2 1.0 μA ILK_OUT VOUT Leakage Current VOUT = 0, EN = 0, VIN = 4.2 V 0.1 1.0 μA VUVLO Under−Voltage Lockout VIN Rising 2.20 2.35 ILK VUVLO_HYS Under−Voltage Lockout Hysteresis 200 VPG(OL) PG Low IPG = 5 mA IPG_LK PG Leakage Current VPG = 5 V VIH Logic Level High EN, VSEL, BYP VIL Logic Level Low EN, VSEL, BYP RLOW IPD 0.4 V 1 μA 1.2 V 0.4 Logic Control Pin Pull Downs (LOW Active) BYP, VSEL, EN Weak Current Source Pull−Down BYP, VSEL, EN Output Voltage Accuracy Target VOUT relative to GND, DC, VOUT−VIN > 100 mV 100 VTRSP –2 V kW 300 VREG V mV nA 4 % Load Transient Response 500–1250 mA, VIN = 3.0 V ±4 % tON On−Time VIN = 3.0 V, VOUT = 3.5 V, Load > 1 A 80 ns fSW Switching Frequency VIN = 3.0 V, VOUT = 3.5 V, Load = 1 A 2.0 2.5 3.0 MHz Boost Valley Current Limit VIN = 2.6 V 3.3 3.7 4.1 A Boost Valley Current Limit During SS VIN = 2.6 V Soft−Start Input Peak Current Limit LIN1 LIN2 IV_LIM IV_LIM_SS ISS_PK tSS VOVP Soft−Start EN HIGH to Regulation Fast, 50 W Load 1.8 A Fast 900 mA Fast 1800 mA μs 600 Output Over−Voltage Protection Threshold 6.0 VOVP_HYS Output Over−Voltage Protection Hysteresis 300 RDS(ON)N N−Channel Boost Switch RDS(ON) VIN = 3.5 V 85 120 mW RDS(ON)P P−Channel Sync Rectifier RDS(ON) VIN = 3.5 V 65 85 mW VIN = 3.5 V 65 85 mW RDS(ON)P_BYP P−Channel Bypass Switch RDS(ON) 6.3 V mV T120A T120 Activation Threshold 120 °C T120R T120 Release Threshold 100 °C T150T T150 Threshold 150 °C T150H T150 Hysteresis 20 °C FAULT Restart Timer 20 ms tRST Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. www.onsemi.com 5 FAN48632 TYPICAL CHARACTERISTICS 100% 100% 95% 95% 90% 90% Efficiency Efficiency Unless otherwise specified; VIN = 3.0 V, VOUT = 3.5 V, VSEL = 0 V, and TA = 25°C; circuit and components according to Figure 1. 85% 2.5 VIN 80% 85% 80% 2.7 VIN −40C 3.0 VIN 75% 75% +25C 3.3 VIN +85C 3.0 VIN, VSEL1 Pulse Load only Pulse Load only 70% 70% 0 500 1000 1500 0 2000 500 Figure 5. Efficiency vs. Load Current and Input Voltage 2000 Figure 6. Efficiency vs. Load Current and Temperature 100% 95% 95% 90% 90% Efficiency 100% 85% 85% 80% 80% 2.5 VIN −40C 2.7 VIN 75% +25C 75% 3.0 VIN +85C 3.0 VIN, VSEL1 Pulse Load only Pulse Load only 70% 70% 0 500 1000 1500 0 2000 500 Load Current (mA) 1000 1500 2000 Load Current (mA) Figure 7. Efficiency vs. Load Current and Input Voltage, VOUT = 3.3 V Figure 8. Efficiency vs. Load Current and Temperature, VOUT = 3.3 V 3 3 2.5 VIN −40C 2.7 VIN +25C Output Regulation (%) 3.0 VIN 2 3.3 VIN Output Regulation (%) 1500 Load Current (mA) Load Current (mA) Efficiency 1000 1 0 −1 +85C 2 1 0 −1 Pulse Load only Pulse Load only −2 −2 0 500 1000 1500 2000 0 Load Current (mA) 500 1000 1500 Load Current (mA) Figure 9. Output Regulation vs. Load Current and Input Voltage (Normalized to 3.0 VIN, 500 mA Load) Figure 10. Output Regulation vs. Load Current and Temperature (Normalized to 3.0 VIN, 500 mA Load, TA = 255C) www.onsemi.com 6 2000 FAN48632 TYPICAL CHARACTERISTICS (continued) Unless otherwise specified; VIN = 3.0 V, VOUT = 3.5 V, VSEL = 0 V, and TA = 25°C; circuit and components according to Figure 1. 200 10 −40C −40C +25C +25C 8 +85C Input Current (mA) Input Current (mA) 180 160 140 120 +85C 6 4 2 100 0 2.0 2.5 3.0 3.5 4.0 4.5 2.0 2.5 3.0 Input Voltage (V) 3.5 4.0 4.5 Input Voltage (V) Figure 11. Quiescent Current vs. Input Voltage and Temperature, Auto Bypass Figure 12. Quiescent Current vs. Input Voltage, Temperature, Forced Bypass (Low IQ) 3500 60 2.5 VIN 2.7 VIN 3000 Switching Frequency (KHz) 50 Output Ripple (mVpp) 3.0 VIN 3.3 VIN 40 30 20 10 2500 2000 1500 2.5 VIN 1000 2.7 VIN 500 3.0 VIN 3.3 VIN Pulse Load only 0 Pulse Load only 0 0 500 1000 1500 0 2000 Load Current (mA) 500 1000 1500 Load Current (mA) Figure 13. Output Ripple vs. Load Current and Input Voltage Figure 14. Switching Frequency vs. Load Current and Input Voltage Figure 15. Startup, 50 W Load Figure 16. Overload Protection www.onsemi.com 7 2000 FAN48632 TYPICAL CHARACTERISTICS (continued) Unless otherwise specified; VIN = 3.0 V, VOUT = 3.5 V, VSEL = 0 V, and TA = 25°C; circuit and components according to Figure 1. Figure 17. Load Transient, 100−500 mA, 100 ns Edge Figure 18. Transient Overload, 1.0−2.5 A, 100 ns Edge Figure 19. Line Transient, 3.0−3.6 VIN, 10 ms Edge, 1.0 A Load Figure 20. Line Transient, 3.3−3.9 VIN, 10 ms Edge, 1.0 A Load Figure 21. Bypass Entry / Exit, Slow VIN Ramp 1 ms Edge, 500 mA Load, 3.2−3.8 VIN Figure 22. VSEL Step, VIN = 3.0 V, 500 mA Load www.onsemi.com 8 FAN48632 CIRCUIT DESCRIPTION If VOUT reaches VIN−300 mV during LIN1 Mode, the SS state is initiated. Otherwise, LIN1 times out after 512 ms and LIN2 Mode is entered. In LIN2 Mode, the current source is incremented to 2 A. If VOUT fails to reach VIN−300 mV after 1024 ms, a fault condition is declared. FAN48632 is a synchronous boost regulator, typically operating at 2.5 MHz in Continuous Conduction Mode (CCM), which occurs at moderate to heavy load current and low VIN voltages. The regulator includes a Bypass Mode that activates when VIN is above the boost regulator’s set point. In anticipation of a heavy load transition, the set point can be adjusted upward by fixed amounts with the VSEL pin to reduce the required system headroom during lighter−load operation to save power. SS State Upon the successful completion of the LIN state (VOUT ≥ VIN−300 mV), the regulator begins switching with boost pulses current limited to 50% of nominal level. During SS state, VOUT is ramped up by stepping the internal reference. If VOUT fails to reach regulation during the SS ramp sequence for more than 64 ms, a fault condition is declared. If large COUT is used, the reference is automatically stepped slower to avoid excessive input current draw. Table 8. OPERATING STATES Mode Description Invoked When LIN Linear Startup VIN > VOUT SS Boost Soft−Start VOUT < VOUT(MIN) BST Boost Operating Mode VOUT = VOUT(MIN) BPS Bypass Mode VIN > VOUT(MIN) BST State This is a normal operating state of the regulator. Boost Mode BPS State If VIN is above VREG when the SS Mode successfully completes, the device transitions directly to BPS Mode. The FAN48632 uses a current−mode modulator to achieve excellent transient response and smooth transitions between CCM and Discontinuous Conduction Mode (DCM) operation. During CCM operation, the device maintains a switching frequency of about 2.5 MHz. In light−load operation (DCM), frequency is reduced to maintain high efficiency. Table 10. EN AND BYP LOGIC TABLE Table 9. BOOST STARTUP SEQUENCE Start State LIN1 Entry Exit End State VIN > UVLO, EN = 1 VOUT > VIN−300 mV SS LIN2 LIN2 SS LIN1 Exit VOUT > VIN−300 mV SS TIMEOUT FAULT VOUT = VOUT(MIN) BST OVERLOAD TIMEOUT FAULT LIN1 or LIN2 Exit EN BYP Mode VOUT 0 0 Shutdown 0 1 Shutdown 0 0 Forced Bypass VIN 1 Auto Bypass VREG or VIN (if VIN > VREG ) 1 Timeout (ms) FAULT State The regulator enters the FAULT state under any of the following conditions: • VOUT fails to achieve the voltage required to advance from LIN state to SS state. • VOUT fails to achieve the voltage required to advance from SS state to BST state. • Boost current limit triggers for 2 ms during the BST state. • VDS protection threshold is exceeded during BPS state. 512 1024 64 Once a fault is triggered, the regulator stops switching and presents a high−impedance path between VIN and VOUT. After waiting 20 ms, a restart is attempted. Shutdown and Startup If EN is LOW, all bias circuits are off and the regulator is in Shutdown Mode. During shutdown, current flow is prevented from VIN to VOUT, as well as reverse flow from VOUT to VIN. During startup, it is recommended to keep DC current draw below 500 mA. Power Good Power good is 0 FAULT, 1 POWER GOOD, open−drain input. The Power good pin is provided for signaling the system when the regulator has successfully completed soft−start and no faults have occurred. Power good also functions as an early warning flag for high die temperature and overload conditions. LIN State When EN is HIGH and VIN > UVLO, the regulator attempts to bring VOUT within 300 mV of VIN using the internal fixed current source from VIN (Q3). The current is limited to LIN1 set point. www.onsemi.com 9 FAN48632 • PG is released HIGH when the soft−start sequence is • • The Bypass Mode entry threshold has 25 mV hysteresis imposed at VOUT to prevent cycling between modes. The transition from Boost Mode to Bypass Mode occurs at the target VOUT + 25 mV. The corresponding input voltage is: successfully completed. PG is pulled LOW when PMOS current limit has triggered for 64 ms OR the die the temperature exceeds 120°C. PG is re−asserted when the device cools below to 100°C. Any FAULT condition causes PG to be de−asserted. V IN w V OUT ) 25mV ) I LOAD @ (DCR L ) R DS(ON)P) Forced Bypass Entry to Forced Bypass Mode initiates with a current limit on Q3 and then proceeds to a true bypass state. To prevent reverse current to the battery, the device waits until output discharges below VIN before entering Forced Bypass Mode. Low−IQ Forced Bypass Mode is available for the FAN48632. After the transition is complete, most of the internal circuitry is disabled to minimize quiescent current draw. OCP, UVLO, output OVP and over−temperature protections are inactive in Forced Bypass Mode. In Forced Bypass Mode, VOUT can follow VIN below VOUT(MIN). Over−Temperature The regulator shuts down when the die temperature exceeds 150°C. Restart occurs when the IC has cooled by approximately 20°C. Bypass Operation In normal operation, the device automatically transitions from Boost Mode to Bypass Mode, if VIN goes above target VOUT. In Bypass Mode, the device fully enhances both Q1 and Q3 to provide a very low impedance path from VIN to VOUT. Entry to the Bypass Mode is triggered by condition where VIN > VOUT and no switching has occurred during past 5 ms. To soften the entry to Bypass Mode, Q3 is driven as a linear current source for the first 5 ms. Bypass Mode exit is triggered when VOUT reaches the target VOUT voltage. During Automatic Bypass Mode, the device is short−circuit protected by voltage comparator tracking the voltage drop from VIN to VOUT; if the drop exceeds 200 mV, FAULT is declared. With sufficient load to enforce CCM operation, the Bypass Mode to Boost Mode transition occurs at the target VOUT. The corresponding input voltage at the transition point is: Ŧ V IN v V OUT ) I LOAD @ (DCR L ) R DS(ON)P) R DS(ON)BYP (eq. 2) VSEL VSEL can be asserted in anticipation of a positive load transient. Raising VSEL increases VOUT(MIN) by a fixed amount and VOUT is stepped to the corresponding target output voltage in 20 ms. The functionality can also be utilized to mitigate undershoot during severe line transients, while minimizing VOUT during more benign operating conditions to save power. (eq. 1) www.onsemi.com 10 FAN48632 APPLICATION INFORMATION Output Capacitance (COUT) 2.0 A Pulsed Loads for GSM Applications The FAN48632 can support 2 A load pulses for GSM and GSM Edge applications, according to the minimum VIN levels shown in Figure 23. Stability The effective capacitance (CEFF) of small, high−value, ceramic capacitors decreases as bias voltage increases. FAN48632 is guaranteed for stable operation with the minimum value of CEFF (CEFF(MIN)) of 14 mF. Inductor Selection The recommended nominal inductance value is 0.47 mH. FAN48632 employs valley−current limiting; peak inductor current can exceed 4.4 A for a short duration during overload conditions. Saturation effects cause the inductor current ripple to become higher under high loading as only valley of the inductor current ripple is controlled. Startup Input current limiting is in effect during soft−start, which limits the current available to charge COUT and any additional capacitance on the VOUT line. If the output fails to achieve regulation within the limits described in the Startup section, a FAULT occurs, causing the circuit to shut down then restart after a significant time period. If the total combined output capacitance is very high, the circuit may not start on the first attempt, but eventually achieves regulation if no load is present. If a high−current load and high capacitance are both present during soft−start, the circuit may fail to achieve regulation and continually attempts soft−start, only to have the output capacitance discharged by the load when in a FAULT state. Figure 23. Minimum VIN for 2 A GSM Pulse, 3.5 VOUT Results shown use circuit/components of Figure 1 with device mounted on standard evaluation platform (layout Figure 24). Layout Recommendation To minimize spikes at VOUT, COUT must be placed as close as possible to PGND and VOUT, as shown in Figure 24. The associated PGND and VOUT routes are best made directly on the top copper layer, rather than thru vias. For thermal reasons, it is suggested to maximize the pour area for all planes other than SW. Especially the ground pour should be set to fill all available PCB surface area and tied to internal layers with a cluster of thermal vias. Output Voltage Ripple Output voltage ripple is inversely proportional to COUT. During tON, when the boost switch is on, all load current is supplied by COUT. Output ripple is calculated as: V RIPPLE(P*P) + t ON @ and ǒ I LOAD C OUT t ON + t SW @ D + t SW @ 1 * therefore: ǒ V RIPPLE(P*P) + t SW @ 1 * V IN V OUT Ǔ (eq. 3) Ǔ I LOAD V IN @ V OUT C OUT (eq. 4) (eq. 5) and t SW + 1 f SW (eq. 6) As can be seen from eq. 5, the maximum VRIPPLE occurs when VIN is at minimum and ILOAD is at maximum. Figure 24. Layout Recommendation www.onsemi.com 11 FAN48632 Table 11. PRODUCT−SPECIFIC DIMENSIONS D E X Y 1.780 ±0.030 1.780 ±0.030 0.290 0.290 TINYBOOST is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 12 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WLCSP16 1.78x1.78x0.586 CASE 567SY ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON16621G WLCSP16 1.78x1.78x0.586 DATE 30 NOV 2016 Electronic versions are uncontrolled except when accessed directly from the Document Repository. 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