FAN54015BUCX

USB-Compliant Single-Cell Li-Ion Switching Charger with USB-OTG Boost Regulator FAN54015 www.onsemi.com Description The FAN54015 combines a highly integrated switch−mode charger, to minimize single−cell Lithium−ion (Li−ion) charging time from a USB power source, and a boost regulator to power a USB peripheral from the battery. The charging parameters and operating modes are programmable through an I2C Interface that operates up to 3.4 Mbps. The charger and boost regulator circuits switch at 3 MHz to minimize the size of external passive components. The FAN54015 provides battery charging in three phases: conditioning, constant current and constant voltage. To ensure USB compliance and minimize charging time, the input current limit can be changed through the I2C by the host processor. Charge termination is determined by a programmable minimum current level. A safety timer with reset control provides a safety backup for the I2C host. Charge status is reported to the host through the I2C port. The integrated circuit (IC) automatically restarts the charge cycle when the battery falls below an internal threshold. If the input source is removed, the IC enters a high−impedance mode, preventing leakage from the battery to the input. Charge current is reduced when the die temperature reaches 120°C, protecting the device and PCB from damage. The FAN54015 can operate as a boost regulator on command from the system. The boost regulator includes a soft−start that limits inrush current from the battery and uses the same external components used for charging the battery. Features • Fully Integrated, High−Efficiency Charger for Single−Cell Li−Ion • • • • • • • • and Li−Polymer Battery Packs Faster Charging than Linear Charge Voltage Accuracy: +0.5% at 25°C +1% from 0 to 125°C +5% Input Current Regulation Accuracy +5% Charge Current Regulation Accuracy 20 V Absolute Maximum Input Voltage 6 V Maximum Input Operating Voltage 1.45 A Maximum Charge Rate Programmable through High−Speed I2C Interface (3.4 Mb/s) with Fast Mode Plus Compatibility ♦ Input Current ♦ Fast−Charge / Termination Current ♦ Charger Voltage ♦ Termination Enable © Semiconductor Components Industries, LLC, 2012 November, 2019 − Rev. 2 1 WLCSP20 1.96x1.87x0.586 CASE 567SL MARKING DIAGRAM A9&K &.&2&Z A9 &K &. &2 &Z = Specific Device Code = 2−Digits Lot Run Traceability Code = Pin One Dot = 2−Digit Date Code Format = Assembly Plant Code ORDERING INFORMATION See detailed ordering and shipping information on page 31 of this data sheet. Features (continued) • 3 MHz Synchronous Buck PWM Controller • • • • • • • • with Wide Duty Cycle Range Small Footprint 1 mH External Inductor Safety Timer with Reset Control 1.8 V Regulated Output from VBUS for Auxiliary Circuits Dynamic Input Voltage Control Low Reverse Leakage to Prevent Battery Drain to VBUS 5 V, 500 mA Boost Mode for USB OTG for 3.0 V to 4.5 V Battery Input Available in a 1.96 x 1.87 mm, 20−bump, 0.4 mm Pitch WLCSP Package These are Pb−Free Devices Applications • Cell Phones, Smart Phones, PDAs • Tablet, Portable Media Players • Gaming Device, Digital Cameras Publication Order Number: FAN54015D FAN54015 L1 SW VBUS 1 μH CBUS 1 μF COUT 0.1 μF PGND PMID CMID 4.7 μF CSIN SDA RSENSE 68 mW FAN54015 SCL VBAT + Battery CBAT VREG 10 μF DISABLE OTG/USB# SYSTEM LOAD CREG 1 μF STAT Figure 1. Typical Application Table 1. FEATURE SUMMARY Part Number Slave Address Automatic Charge Special Charger (Note 1) Safety Limits Battery Absent Behavior E2 Pin VREG (E3 Pin) FAN54015UCX 1101010 Yes Yes Yes ON DISABLE 1.8 V 1. A “special charger” is a current−limited charger that is not a USB compliant source. VREG CREG 1 μF 1.8 V / PMID REG PMID PMID Q1 Q3 CMID 4.7 μF Q1A VBUS CHARGE PUMP CBUS 1 μF VBUS OVP Q1B Q2 PWM MODULATOR I_IN CONTROL 1 μH RSENSE COUT 0.1 μF PGND VCC DAC L1 SW + Battery CSIN VREF VBAT SDA SCL DISABLE OTG/USB# PMID I2C INTERFACE 30 mA SYSTEM LOAD STAT CBAT OSC LOGIC AND CONTROL Figure 2. IC and System Block Diagram www.onsemi.com 2 PMID Q1A Q1B Greater than V BAT ON OFF Less than VBAT OFF ON FAN54015 Table 2. RECOMMENDED EXTERNAL COMPONENTS Component Description Vendor Parameter Typ Unit L1 1 mH ±20%, 1.6 A, DCR = 55 mW, 2520 Murata: LQM2HPN1R0 L 1.0 mH 1 mH ±30%, 1.4 A, DCR = 85 mW, 2016 Murata: LQM2MPN1R0 CBAT 10 mF, 20%, 6.3 V, X5R, 0603 Murata: GRM188R60J106M TDK: C1608X5R0J106M C 10 mF CMID 4.7 mF, 10%, 6.3 V, X5R, 0603 Murata: GRM188R60J475K TDK: C1608X5R0J475K C (Note 2) 4.7 mF CBUS 1.0 mF, 10%, 25 V, X5R, 0603 Murata GRM188R61E105K TDK:C1608X5R1E105M C 1.0 mF 2. A 6.3 V rating is sufficient for CMID because PMID is protected from over−voltage surges on VBUS by Q3 (Figure 2). A1 A2 A3 A4 A4 A3 A2 A1 B1 B2 B3 B4 B4 B3 B2 B1 C1 C2 C3 C4 C4 C3 C2 C1 D1 D2 D3 D4 D4 D3 D2 D1 E1 E2 E3 E4 E4 E3 E2 E1 Top View Bottom View Figure 3. WLCSP−20 Pin Assignments PIN DEFINITIONS Pin # Name Description A1, A2 VBUS A3 NC No Connect. No external connection is made between this pin and the IC’s internal circuitry. A4 SCL I 2C Interface Serial Clock. This pin should not be left floating. B1−B3 PMID Power Input Voltage. Power input to the charger regulator, bypass point for the input current sense, and high−voltage input switch. Bypass with a minimum of 4.7 mF, 6.3 V capacitor to PGND. B4 SDA I 2C Interface Serial Data. This pin should not be left floating. C1 − C3 SW Switching Node. Connect to output inductor. C4 STAT Status. Open−drain output indicating charge status. The IC pulls this pin LOW when charging. D1 − D3 PGND Power Ground. Power return for gate drive and power transistors. The connection from this pin to the bottom of CMID should be as short as possible. D4 OTG On−The−Go. Enables boost regulator in conjunction with OTG_EN and OTG_PL bits (see Table 16). On VBUS Power−On Reset (POR), this pin sets the input current limit for t15MIN charging. E1 CSIN Current−Sense Input. Connect to the sense resistor in series with the battery. The IC uses this node to sense current into the battery. Bypass this pin with a 0.1 mF capacitor to PGND. E2 DISABLE Charge Disable. If this pin is HIGH, charging is disabled. When LOW, charging is controlled by the I2C registers. When this pin is HIGH, the 15−minute timer is reset. This pin does not affect the 32−second timer. E3 VREG Regulator Output. Connect to a 1 mF capacitor to PGND. This pin can supply up to 2mA of DC load current. The output voltage is PMID, which is limited to 1.8 V. E4 VBAT Battery Voltage. Connect to the positive (+) terminal of the battery pack. Bypass with a 0.1 mF capacitor to PGND if the battery is connected through long leads. Charger Input Voltage and USB−OTG output voltage. Bypass with a 1 mF capacitor to PGND. www.onsemi.com 3 FAN54015 ABSOLUTE MAXIMUM RATINGS Symbol VBUS Parameter VBUS Voltage Min Max Unit Continuous –1.4 20.0 V Pulsed, 100 ms Maximum Non−Repetitive –2.0 VSTAT STAT Voltage –0.3 16.0 V VI PMID Voltage − 7.0 V SW, CSIN, VBAT, DISABLE Voltage –0.3 7.0 Voltage on Other Pins –0.3 6.5 (Note 3) V − 4 V/ms VO dV BUS Maximum VBUS Slope above 5.5 V when Boost or Charger are Active dt ESD Electrostatic Discharge Protection Level Human Body Model per JESD22−A114 2000 Charged Device Model per JESD22−C101 500 V TJ Junction Temperature –40 +150 °C TSTG Storage Temperature –65 +150 °C − +260 °C TL Lead Soldering Temperature, 10 Seconds Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 3. Lesser of 6.5 V or VI + 0.3 V. RECOMMENDED OPERATING CONDITIONS Symbol VBUS VBAT(MAX) * dV BUS dt Parameter Min Max Unit Supply Voltage 4 6 V Maximum Battery Voltage when Boost enabled − 4.5 V TA ≤ 60°C − 4 V/ms TA ≥ 60°C − 2 Negative VBUS Slew Rate during VBUS Short Circuit, CMID ≤ 4.7 mF (see VBUS Short While Charging) TA Ambient Temperature –30 +85 °C TJ Junction Temperature (see Thermal Regulation and Protection section) –30 +120 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. THERMAL PROPERTIES Symbol Parameter Value Unit qJA Junction−to−Ambient Thermal Resistance 60 °C/W qJB Junction−to−PCB Thermal Resistance 20 °C/W Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with four−layer 2s2p boards in accordance to JEDEC standard JESD51. Special attention must be paid not to exceed junction temperature TJ(max) at a given ambient temperature TA. For measured data, see Table 11. www.onsemi.com 4 FAN54015 ELECTRICAL SPECIFICATIONS (Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; VBUS = 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA, OTG = 0 or 1.8 V; and typical values are for TJ = 25°C) Parameter Symbol Conditions Min Typ Max Unit VBUS > VBUS(min), PWM Switching − 10 − mA VBUS > VBUS(min); PWM Enabled, Not Switching (Battery OVP Condition); I_IN Setting = 100 mA − 2.5 − mA 0°C < TJ < 85°C, HZ_MODE = 1 VBAT < VLOWV, 32S Mode − 63 90 mA POWER SUPPLIES IVBUS VBUS Current ILKG VBAT to VBUS Leakage Current 0°C < TJ < 85°C, HZ_MODE = 1, VBAT = 4.2 V, VBUS = 0 V − 0.2 5.0 mA IBAT Battery Discharge Current in High−Impedance Mode 0°C < TJ < 85°C, HZ_MODE = 1, VBAT = 4.2 V − − 20 mA DISABLE = 1, 0°C < TJ < 85°C, VBAT = 4.2 V − − 10 3.5 − 4.4 –0.5% − +0.5% TJ = 0 to 125°C –1% − +1% Output Charge Current Range VLOWV < VBAT < VOREG, RSENSE = 68 mW 550 − 1450 mA Charge Current Accuracy Across RSENSE 20 mV ≤ VIREG ≤ 40 mV 92 97 102 % VIREG > 40 mV 94 97 100 % Weak Battery Threshold Range 3.4 − 3.7 V Weak Battery Threshold Accuracy –5 − +5 % − 30 − ms CHARGER VOLTAGE REGULATION VOREG Charge Voltage Range Charge Voltage Accuracy TA = 25°C V CHARGING CURRENT REGULATION IOCHRG WEAK BATTERY DETECTION VLOWV Weak Battery Deglitch Time Rising Voltage LOGIC LEVELS: DISABLE, SDA, SCL, OTG VIH High−Level Input Voltage 1.05 − − V VIL Low−Level Input Voltage − − 0.4 V IIN Input Bias Current Input Tied to GND or VIN − 0.01 1.00 mA Termination Current Range VBAT > VOREG – VRCH, RSENSE = 68 mW 50 − 400 mA Termination Current Accuracy [VCSIN – VBAT] from 3 mV to 20 mV –25 − +25 % [VCSIN – VBAT] from 20 mV to 40 mV –5 − +5 2 mV Overdrive − 30 − ms 1.7 1.8 1.9 V V CHARGE TERMINATION DETECTION I(TERM) Termination Current Deglitch Time 1.8 V LINEAR REGULATOR VREG 1.8 V Regulator Output IREG from 0 to 2 mA INPUT POWER SOURCE DETECTION VIN(MIN)1 VBUS Input Voltage Rising To Initiate and Pass VBUS Validation − 4.29 4.42 VIN(MIN)2 Minimum VBUS During Charge During Charging − 3.71 3.94 V − 30 − ms –3 − +3 % tVBUS_VALID VBUS Validation Time SPECIAL CHARGER (VBUS) VSP Special Charger Setpoint Accuracy www.onsemi.com 5 FAN54015 ELECTRICAL SPECIFICATIONS (Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; VBUS = 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA, OTG = 0 or 1.8 V; and typical values are for TJ = 25°C) (continued) Symbol Parameter Conditions Min Typ Max Unit IIN Set to 100 mA 88 93 98 mA IIN Set to 500 mA 450 475 500 − − 6.5 V − 20 − mA 100 120 150 mV INPUT CURRENT LIMIT IINLIM Input Current Limit Threshold VREF BIAS GENERATOR VREF Bias Regulator Voltage VBUS > VIN(MIN) or VBAT > VBAT(MIN) Short−Circuit Current Limit BATTERY RECHARGE THRESHOLD VRCH Recharge Threshold Below V(OREG) Deglitch Time VBAT Falling Below VRCH Threshold − 130 − ms STAT OUTPUT VSTAT(OL) STAT Output Low ISTAT = 10 mA − − 0.4 V ISTAT(OH) STAT High Leakage Current VSTAT = 5 V − − 1 mA Begins after Termination Detected and VBAT ≤ VOREG – VRCH − –0.80 − mA BATTERY DETECTION IDETECT Battery Detection Current before Charge Done (Sink Current) (Note 4) tDETECT Battery Detection Time 262 ms SLEEP COMPARATOR VSLP tSLP_EXIT Sleep−Mode Entry Threshold, VBUS – VBAT 2.3 V ≤ VBAT ≤ VOREG, VBUS Falling 0 0.04 0.10 V Deglitch Time for VBUS Rising Above VBAT by VSLP Rising Voltage − 30 − ms IIN(LIMIT) = 500 mA − 180 250 mW Q1 On Resistance (PMID to SW) − 130 225 Q2 On Resistance (SW to GND) − 150 225 POWER SWITCHES (see Figure 2) RDS(ON) Q3 On Resistance (VBUS to PMID) CHARGER PWM MODULATOR fSW Oscillator Frequency 2.7 3.0 3.3 MHz DMAX Maximum Duty Cycle − − 100 % DMIN Minimum Duty Cycle − 0 − % ISYNC Synchronous to Non−Synchronous Current Cut−Off Threshold (Note 5) − 140 − mA 2.5 V < VBAT < 4.5 V, ILOAD from 0 to 200 mA 4.80 5.07 5.17 V 3.0 V < VBAT < 4.5 V, ILOAD from 0 to 500 mA 4.77 5.07 5.17 − 140 300 mA Low−Side MOSFET (Q2) Cycle−by− Cycle Current Limit BOOST MODE OPERATION (OPA_MODE = 1, HZ_MODE = 0) VBOOST Boost Output Voltage at VBUS IBAT(BOOST) Boost Mode Quiescent Current ILIMPK(BST) Q2 Peak Current Limit UVLOBST Minimum Battery Voltage for Boost Operation PFM Mode, VBAT = 3.6 V, IOUT = 0 1272 1590 1908 mA While Boost Active − 2.42 − V To Start Boost Regulator − 2.58 2.70 Normal Operation − 1500 − kW Charger Validation − 100 − W VBUS LOAD RESISTANCE RVBUS VBUS to PGND Resistance www.onsemi.com 6 FAN54015 ELECTRICAL SPECIFICATIONS (Unless otherwise specified: according to the circuit of Figure 1; recommended operating temperature range for TJ and TA; VBUS = 5.0 V; HZ_MODE; OPA_MODE = 0; (Charge Mode); SCL, SDA, OTG = 0 or 1.8 V; and typical values are for TJ = 25°C) (continued) Symbol Parameter Conditions Min Typ Max Unit PROTECTION AND TIMERS VBUS Over−Voltage Shutdown VBUS Rising 6.09 6.29 6.49 V Hysteresis VBUS Falling − 100 − mV Q1 Cycle−by−Cycle Peak Current Limit Charge Mode − 2.3 − A VSHORT Battery Short−Circuit Threshold VBAT Rising 1.95 2.00 2.05 V Hysteresis VBAT Falling − 100 − mV ISHORT Linear Charging Current VBAT < VSHORT 20 30 40 mA Thermal Shutdown Threshold (Note 6) TJ Rising − 145 − °C Hysteresis (Note 6) TJ Falling − 10 − TCF Thermal Regulation Threshold (Note 6) Charge Current Reduction Begins − 120 − °C tINT Detection Interval − 2.1 − s t32S 32−Second Timer (Note 7) Charger Enabled 20.5 25.2 28.0 s Charger Disabled 18.0 25.2 34.0 15−Minute Timer 15−Minute Mode 12.0 13.5 15.0 min Low−Frequency Timer Accuracy Charger Inactive –25 − 25 % VBUSOVP ILIMPK(CHG) TSHUTDWN t15MIN DtLF Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Negative current is current flowing from the battery to VBUS (discharging the battery). 5. Q2 always turns on for 60 ns, then turns off if current is below ISYNC. 6. Guaranteed by design; not tested in production. 7. This tolerance (%) applies to all timers on the IC, including soft−start and deglitching timers. I2C TIMING SPECIFICATIONS (Guaranteed by design) Symbol fSCL tBUF tHD;STA tLOW tHIGH tSU;STA Parameter SCL Clock Frequency Conditions Min Typ Max Unit Standard Mode − − 100 kHz Fast Mode − − 400 High−Speed Mode, CB ≤ 100 pF − − 3400 High−Speed Mode, CB ≤ 400 pF − − 1700 Bus−Free Time between STOP and START Conditions Standard Mode − 4.7 − Fast Mode − 1.3 − START or Repeated START Hold Time Standard Mode − 4 − ms Fast Mode − 600 − ns High−Speed Mode − 160 − ns Standard Mode − 4.7 − ms Fast Mode − 1.3 − ms High−Speed Mode, CB ≤ 100 pF − 160 − ns High−Speed Mode, CB ≤ 400 pF − 320 − ns Standard Mode − 4 − ms Fast Mode − 600 − ns High−Speed Mode, CB ≤ 100 pF − 60 − ns High−Speed Mode, CB ≤ 400 pF − 120 − ns Standard Mode − 4.7 − ms Fast Mode − 600 − ns SCL LOW Period SCL HIGH Period Repeated START Setup Time www.onsemi.com 7 ms FAN54015 I2C TIMING SPECIFICATIONS (Guaranteed by design) (continued) Symbol tSU;DAT tHD;DAT tRCL Parameter Data Setup Time Data Hold Time SCL Rise Time Conditions Min Typ Max Unit High−Speed Mode − 160 − ns Standard Mode − 250 − ns Fast Mode − 100 − High−Speed Mode − 10 − Standard Mode 0 − 3.45 ms Fast Mode 0 − 900 ns High−Speed Mode, CB ≤ 100 pF 0 − 70 ns High−Speed Mode, CB ≤ 400 pF 0 − 150 ns ns Standard Mode 20 + 0.1 CB 1000 Fast Mode 20 + 0.1 CB 300 High−Speed Mode, CB ≤ 100 pF High−Speed Mode, CB ≤ 400 pF tFCL SCL Fall Time tRDA tRCL1 SDA Rise Time Rise Time of SCL after a Repeated START Condition and after ACK Bit tFDA tSU;STO CB SDA Fall Time Stop Condition Setup Time − 10 80 − 20 160 Standard Mode 20 + 0.1 CB 300 Fast Mode 20 + 0.1 CB 300 High−Speed Mode, CB ≤ 100 pF − 10 40 High−Speed Mode, CB ≤ 400 pF − 20 80 Standard Mode 20 + 0.1 CB 1000 Fast Mode 20 + 0.1 CB 300 High−Speed Mode, CB ≤ 100 pF − 10 80 High−Speed Mode, CB ≤ 400 pF − 20 160 Standard Mode 20 + 0.1 CB 300 Fast Mode 20 + 0.1 CB 300 ns ns ns High−Speed Mode, CB ≤ 100 pF − 10 80 High−Speed Mode, CB ≤ 400 pF − 20 160 Standard Mode − 4 − ms Fast Mode − 600 − ns High−Speed Mode − 160 − ns − − 400 pF Capacitive Load for SDA, SCL www.onsemi.com 8 FAN54015 TIMING DIAGRAMS tF tSU;STA tBUF SDA tR SCL TSU;DAT tHD;STO tHIGH tLOW tHD;STA tHD;DAT tHD;STA REPEATED START START STOP Figure 4. I2C Interface Timing for Fast and Slow Modes tFDA tRDA REPEATED START tSU;DAT SDAH tSU;STA tRCL1 SCLH tLOW tHD;STA tFCL tRCL tSU;STO tHIGH tHD;DAT REPEATED START note A = MCS Current Source Pull−up = RP Resistor Pull−up Note A: First rising edge of SCLH after Repeated Start and after each ACK bit. Figure 5. I2C Interface Timing for High−Speed Mode www.onsemi.com 9 STOP START FAN54015 CHARGE MODE TYPICAL CHARACTERISTICS 180 900 160 800 Battery Charge Current (mA) Battery Charge Current (mA) (Unless otherwise specified, circuit of Figure 1, VOREG = 4.2 V, VBUS = 5.0 V, and TA = 25°C) 140 120 100 80 60 5.5 VBUS 5.0 VBUS 4.5 VBUS 40 20 − 2.5 3 3.5 4 700 600 500 400 300 100 − 4.5 5.5 VBUS 5.0 VBUS 4.5 VBUS 200 2.5 3 Figure 6. Battery Charge Current vs. VBUS with IINLIM = 100 mA 97% Efficiency Efficiency 92% 88% 85% 90% 88% 5.5 VBUS 5.0 VBUS 4.5 VBUS 86% 300 500 700 900 1100 Battery Charge Current (mA) 4.5 94% 91% 82% 100 4 Figure 7. Battery Charge Current vs. VBUS with IINLIM = 500 mA 4.20 VBAT, 4.5 VBUS 4.20 VBAT, 5.0 VBUS 3.54 VBAT, 5.0 VBUS 3.54 VBAT, 4.5 VBUS 94% 3.5 Battery Voltage, VBAT (V) Battery Voltage, VBAT (V) 1300 84% 2.5 1500 2.7 2.9 3.1 3.3 3.5 3.7 3.9 Battery Voltage, VBAT (V) 4.1 4.3 Figure 8. Charger Efficiency, No IINLIM, IOCHARGE = 1450 mA Figure 9. Charger Efficiency vs. VBUS, IINLIM = 500 mA Figure 10. Auto−Charge Startup at VBUS Plug−in, IINLIM = 100 mA, OTG = 1, VBAT = 3.4 V Figure 11. Auto−Charge Startup at VBUS Plug−in, IINLIM = 500 mA, OTG=1, VBAT = 3.4 V www.onsemi.com 10 FAN54015 CHARGE MODE TYPICAL CHARACTERISTICS (Unless otherwise specified, circuit of Figure 1, VOREG = 4.2 V, VBUS = 5.0 V, and TA = 25°C) (continued) Figure 12. AutoCharge Startup with 300mA Limited Charger / Adaptor, IINLIM = 500 mA, OTG = 1, VBAT = 3.4 V Figure 13. Charger Startup with HZ_MODE Bit Reset, IINLIM = 500 mA, IOCHARGE = 1050 mA, OREG = 4.2 V, VBAT = 3.6 V Figure 14. Battery Removal / Insertion During Charging, VBAT = 3.9 V, IOCHARGE = 1050 Ma, No IINLIM, TE = 0 Figure 15. Battery Removal / Insertion During Charging, VBAT = 3.9 V, IOCHARGE = 1050 mA, No IINLIM, TE = 1 www.onsemi.com 11 FAN54015 CHARGE MODE TYPICAL CHARACTERISTICS (Unless otherwise specified, circuit of Figure 1, VOREG = 4.2 V, VBUS = 5.0 V, and TA = 25°C) (continued) 1.82 150 1.81 −30°C +25°C +85°C 100 VREG (V) High−Z Mode Current (mA) 200 50 1.80 1.79 −30°C, 5.0 VBUS +25°C, 5.0 VBUS +85°C, 5.0 VBUS 1.78 0 4.0 4.5 5.0 Input Voltage, VBUS (V) 5.5 1.77 6.0 Figure 16. VBUS Current in High−Impedance Mode with Battery Open 0 1 2 3 4 1.8 V Regulator Load Current (mA) Figure 17. VREG 1.8 V Output Regulation Figure 18. No Battery, VBUS at Power Up www.onsemi.com 12 5 FAN54015 BOOST MODE TYPICAL CHARACTERISTICS 100 100 95 95 Efficiency (%) Efficiency (%) (Unless otherwise specified, using circuit of Figure 1, VBAT = 3.6 V, TA = 25°C) 90 85 3.0 VBAT 3.6 VBAT 4.2 VBAT 80 75 0 100 200 300 400 90 85 −10°C, 3.6 VBAT +25°C, 3.6 VBAT +85°C, 3.6 VBAT 80 75 500 0 100 VBUS Load Current (mA) −10°C, 3.6 VBAT +25°C, 3.6 VBAT +85°C, 3.6 VBAT 5.05 5.00 VBUS (V) 5.00 VBUS (V) 500 5.10 3.0 VBAT 3.6 VBAT 4.2 VBAT 5.05 4.95 4.90 4.85 4.95 4.90 4.85 0 100 200 300 400 4.80 500 0 100 VBUS Load Current (mA) 200 300 400 VBUS Load Current (mA) 500 Figure 22. Output Regulation Over Temperature Figure 21. Output Regulation vs. VBAT 250 20 −30°C +25°C +85°C 200 High−Z Mode Current (mA) Quiescent Current (mA) 400 Figure 20. Efficiency Over Temperature 5.10 150 100 50 300 VBUS Load Current (mA) Figure 19. Efficiency vs. VBAT 4.80 200 2 2.5 3 3.5 4 4.5 15 10 5 0 5 Battery Voltage, VBUS (V) −30°C +25°C +85°C 2 2.5 3 3.5 4 4.5 5 Battery Voltage, VBUS (V) Figure 23. Quiescent Current Figure 24. High−Impedance Mode Battery Current www.onsemi.com 13 FAN54015 BOOST MODE TYPICAL CHARACTERISTICS (Unless otherwise specified, using circuit of Figure 1, VBAT = 3.6 V, TA = 25°C) Figure 27. Boost PWM Waveform Figure 28. Boost PFM Waveform 30 30 2.7 VBAT 3.6 VBAT 4.2 VBAT 4.5 VBAT 20 15 10 5 0 −30°C, 3.6 VBAT +25°C, 3.6 VBAT +85°C, 3.6 VBAT 25 VBUS Ripple (mVpp) VBUS Ripple (mVpp) 25 20 15 10 5 0 100 200 300 400 0 500 VBUS Load Current (mA) 0 100 200 300 400 VBUS Load Current (mA) Figure 25. Output Ripple vs. VBAT Figure 26. Output Ripple vs. Temperature www.onsemi.com 14 500 FAN54015 BOOST MODE TYPICAL CHARACTERISTICS (Unless otherwise specified, using circuit of Figure 1, VBAT = 3.6 V, TA = 25°C) VBUS IL IBAT Figure 29. Startup, 3.6 VBAT, 44 W Load, Additional 10 mF, X5R Across VBUS Figure 30. VBUS Fault Response, 3.6 VBAT Figure 31. Load Transient, 5 − 155 − 5 mA, tR = tF = 100 ns Figure 32. Load Transient, 5 − 255 − 5 mA, tR = tF = 100 ns www.onsemi.com 15 FAN54015 CIRCUIT DESCRIPTION / OVERVIEW When charging batteries with a current−limited input source, such as USB, a switching charger’s high efficiency over a wide range of output voltages minimizes charging time. FAN54015 combines a highly integrated synchronous buck regulator for charging with a synchronous boost regulator, which can supply 5 V to USB On−The−Go (OTG) peripherals. The regulator employs synchronous rectification for both the charger and boost regulators to maintain high efficiency over a wide range of battery voltages and charge states. The FAN54015 has three operating modes: 1. Charge Mode: Charges a single−cell Li−ion or Li−polymer battery. 2. Boost Mode: Provides 5 V power to USB−OTG with an integrated synchronous rectification boost regulator using the battery as input. 3. High−Impedance Mode: Both the boost and charging circuits are OFF in this mode. Current flow from VBUS to the battery or from the battery to VBUS is blocked in this mode. This mode consumes very little current from VBUS or the battery. NOTE: Default settings are denoted by bold typeface. Battery Charging Curve If the battery voltage is below VSHORT, a linear current source pre−charges the battery until VBAT reaches VSHORT. The PWM charging circuit is then started and the battery is charged with a constant current if sufficient input power is available. The current slew rate is limited to prevent overshoot. The FAN54015 is designed to work with a current−limited input source at VBUS. During the current regulation phase of charging, IINLIM or the programmed charging current limits the amount of current available to charge the battery and power the system. The effect of IINLIM on ICHARGE can be seen in Figure 34. VOREG ICHARGE VBAT ITERM VSHORT ISHORT CONSTANT CURRENT CONSTANT PRE− CHARGE (CC) VOLTAGE (CV) Figure 33. Charge Curve, ICHARGE Not Limited by IINLIM Charge Mode VOREG In Charge Mode, FAN54015 employs four regulation loops: 1. Input Current: Limits the amount of current drawn from VBUS. This current is sensed internally and can be programmed through the I2C interface. 2. Charging Current: Limits the maximum charging current. This current is sensed using an external RSENSE resistor. 3. Charge Voltage: The regulator is restricted from exceeding this voltage. As the internal battery voltage rises, the battery’s internal impedance and RSENSE work in conjunction with the charge voltage regulation to decrease the amount of current flowing to the battery. Battery charging is completed when the voltage across RSENSE drops below the ITERM threshold. 4. Temperature: If the IC’s junction temperature reaches 120°C, charge current is reduced until the IC’s temperature stabilizes at 120°C. 5. An additional loop limits the amount of drop on VBUS to a programmable voltage (VSP) to accommodate “special chargers” that limit current to a lower current than might be available from a “normal” USB wall charger. VBAT ICHARGE ITERM VSHORT ISHORT PRE− CHARGE CURRENT REGULATION VOLTAGE REGULATION Figure 34. Charge Curve, IINLIM Limits ICHARGE Assuming that VOREG is programmed to the cell’s fully charged “float” voltage, the current that the battery accepts with the PWM regulator limiting its output (sensed at VBAT) to VOREG declines, and the charger enters the voltage regulation phase of charging. When the current declines to the programmed ITERM value, the charge cycle is complete. Charge current termination can be disabled by resetting the TE bit (REG1[3]). The charger output or “float” voltage can be programmed by the OREG bits from 3.5 V to 4.44 V in 20 mV increments, as shown in Table 3. www.onsemi.com 16 FAN54015 Table 3. OREG BITS (OREG[7:2]) VS. CHARGER VOUT (VOREG) FLOAT VOLTAGE Decimal Hex VOREG Decimal Hex VOREG 0 00 3.50 32 20 4.14 1 01 3.52 33 21 4.16 2 02 3.54 34 22 4.18 3 03 3.56 35 23 4.20 A new charge cycle begins when one of the following occurs: • The battery voltage falls below VOREG − VRCH • VBUS Power on Reset (POR) clears and the battery voltage is below the weak battery threshold (VLOWV). • CE or HZ_MODE is reset through I2C write to CONTROL1 (R1) register. 4 04 3.58 36 24 4.22 Charge Current Limit (IOCHARGE) 5 05 3.60 37 25 4.24 6 06 3.62 38 26 4.26 7 07 3.64 39 27 4.28 8 08 3.66 40 28 4.30 9 09 3.68 41 29 4.32 DEC BIN 10 0A 3.70 42 2A 4.34 0 11 0B 3.72 43 2B 4.36 12 0C 3.74 44 2C 4.38 13 0D 3.76 45 2D 4.40 14 0E 3.78 46 2E 15 0F 3.80 47 2F 16 10 3.82 48 17 11 3.84 18 12 19 Table 5. IOCHARGE (REG4 [6:4]) CURRENT AS FUNCTION OF IOCHARGE BITS AND RSENSE RESISTOR VALUES IOCHARGE (mA) HEX VRSENSE (mV) 68 mW 100 mW 000 00 37.4 550 374 1 001 01 44.2 650 442 2 010 02 51.0 750 510 3 011 03 57.8 850 578 4.42 4 100 04 71.4 1050 714 4.44 5 101 05 78.2 1150 782 30 4.44 6 110 06 91.8 1350 918 49 31 4.44 7 111 07 98.6 1450 986 3.86 50 32 4.44 13 3.88 51 33 4.44 20 14 3.90 52 34 4.44 21 15 3.92 53 35 4.44 22 16 3.94 54 36 4.44 23 17 3.96 55 37 4.44 24 18 3.98 56 38 4.44 25 19 4.00 57 39 4.44 26 1A 4.02 58 3A 4.44 27 1B 4.04 59 3B 4.44 28 1C 4.06 60 3C 4.44 29 1D 4.08 61 3D 4.44 30 1E 4.10 62 3E 4.44 Termination Current Limit Current charge termination is enabled when TE (REG1[3]) = 1. Typical termination current values are given in Table 6. Table 6. ITERM CURRENT AS FUNCTION OF ITERM BITS (REG4[2:0]) AND RSENSE RESISTOR VALUES ITERM 68 mW 100 mW 0 3.3 49 33 1 6.6 97 66 2 9.9 146 99 3 13.2 194 132 4 16.5 243 165 5 19.8 291 198 6 23.1 340 231 7 26.4 388 264 The following charging parameters can be programmed by the host through I2C: Table 4. PROGRAMMABLE CHARGING PARAMETERS Parameter Name Register Output Voltage Regulation VOREG REG2[7:2] Battery Charging Current Limit IOCHRG REG4[6:4] Input Current Limit IINLIM REG1[7:6] Charge Termination Limit ITERM REG4[2:0] Weak Battery Voltage VLOWV REG1[5:4] ITERM (mA) VRSENSE (mV) When the charge current falls below ITERM, PWM charging stops and the STAT bits change to READY (00) for about 500 ms while the IC determines whether the battery and charging source are still connected. STAT then changes to CHARGE DONE (10), provided the battery and charger are still connected. www.onsemi.com 17 FAN54015 PWM Controller in Charge Mode USB−Friendly Boot Sequence The IC uses a current−mode PWM controller to regulate the output voltage and battery charge currents. The synchronous rectifier (Q2) has a current limit that which off the FET when the current is negative by more than 140 mA peak. This prevents current flow from the battery. At VBUS POR, when the battery voltage is above the weak battery threshold (VLOWV), the IC operates in accordance with its I2C register settings. If VBAT < VLOWV, the IC sets all registers to their default values and enables the charger using an input current limit controlled by the OTG pin (100 mA if OTG is LOW and 500 mA if OTG is HIGH). This feature can revive a battery whose voltage is too low to ensure reliable host operation. Charging continues in the absence of host communication even after the battery has reached VOREG, whose default value is 3.54 V, and the charger remains active until t15MIN times out. Once the host processor begins writing to the IC, charging parameters are set by the host, which must continually reset the t32S timer to continue charging using the programmed charging parameters. If t32S.times out, the register defaults are loaded, the FAULT bits are set to 110, STAT is pulsed HIGH, and charging continues with default charge parameters. Safety Timer Section references Figure 39. At the beginning of charging, the IC starts a 15−minute timer (t15MIN ). When this times out, charging is terminated. Writing to any register through I2C stops and resets the t15MIN timer, which in turn starts a 32−second timer (t32S). Setting the TMR_RST bit (REG0[7]) resets the t32S timer. If the t32S timer times out; charging is terminated, the registers are set to their default values, and charging resumes using the default values with the t15MIN timer running. Normal charging is controlled by the host with the t32S timer running to ensure that the host is alive. Charging with the t15MIN timer running is used for charging that is unattended by the host. If the t15MIN timer expires; the IC turns off the charger, sets the CE bit, and indicates a timer fault (110) on the FAULT bits (REG0[2:0]). This sequence prevents overcharge if the host fails to reset the t32S timer. Input Current Limiting To minimize charging time without overloading VBUS current limitations, the IC’s input current limit can be programmed by the IINLIM bits (REG1[7:6]). Table 7. INPUT CURRENT LIMIT VBUS POR / Non−Compliant Charger Rejection When the IC detects that VBUS has risen above VIN(MIN)1 (4.4 V), the IC applies a 100 W load from VBUS to GND. To clear the VBUS POR (Power−On−Reset) and begin charging, VBUS must remain above VIN(MIN)1 and below VBUSOVP for tVBUS_VALID (30 ms) before the IC initiates charging. The VBUS validation sequence always occurs before charging is initiated or re−initiated (for example, after a VBUS OVP fault or a VRCH recharge initiation). tVBUS_VALID ensures that unfiltered 50 / 60 Hz chargers and other non−compliant chargers are rejected. IINLIM REG1[7:6] Input Current Limit 00 100 mA 01 500 mA 10 800 mA 11 No limit The OTG pin establishes the input current limit when t15MIN is running. www.onsemi.com 18 FAN54015 FLOW CHARTS VBUS POR YES CE or HZ, CE# DISABLE Pin set? YES VBAT > VLOWV HZ State Charge Configuration State NO NO NO NO T15Min Timer? CE or HZ, CE# DISABLE Pin set? YES NO T32Sec Armed? YES YES CE or HZ, CE# DISABLE Pin set? YES NO HZ State T32Sec Armed? YES NO Reset all registers Start T15MIN Figure 35. Charger VBUS PO www.onsemi.com 19 Charge State FAN54015 FLOW CHARTS (continued) CHARGE STATE Disable Charging NO Indicate VBUS Fault VBAT < VSHORT YES Enable ISHORT , Reset Safety reg VBUS OK? NO Indicate Charging NO VBUS OK? YES YES PWM Charging T15MIN Timeout? Indicate Charging NO Disable Charging Indicate VBUS Fault YES T15MIN Timeout? Indicate timer fault YES Set CE Charge Configuration State NO NO HIGHZ mode NO IOUT < ITERM Termination enabled VBAT > VOREG – V RCH Indicate Charge Complete VBAT < VOREG – VRCH Reset Safety reg Delay tINT NO YES Stop Charging Battery Removed VBAT < VOREG – VRCH Enable IDET for TDETECT Figure 36. Charge Mode www.onsemi.com 20 YES YES Reset charge parameters FAN54015 FLOW CHARTS (continued) HZ State Charge Configuration State DISABLE PIN HIGH Reset T15min if running LOW T32Sec ARMED AND CE = 0? CE# YES Stop T32Sec Charge State RUN T32Sec NO NO NO Has T15Min and CE# CE = 0 START T15Min HZ or CE set? YES VBAT > VLOWV? YES HIGH NO VBAT < VOREG for 262 ms? NO YES DISABLE PIN Figure 37. Charge Configuration LOW Charge State Figure 38. HZ−State Charge Start Start T15MIN Reset Registers YES T32SEC NO Start T32SEC Stop T15MIN T15MIN Active? YES Expired? YES NO I2C Write received? NO Timer Fault : Set CE Figure 39. Timer Flow Chart www.onsemi.com 21 T15MIN Expired? YES NO Continue Charging YES FAN54015 Special Charger Table 9. ISAFE (IOCHARGE LIMIT) AS FUNCTION OF ISAFE BITS (REG6[6:4]) The FAN54015 has additional functionality to limit input current in case a current−limited “special charger” is supplying VBUS. These slowly increase the charging current until either: • IINLIM or IOCHARGE is reached ISAFE (REG6[6:4]) ISAFE (mA) or • VBUS = VSP. If VBUS collapses to VSP when the current is ramping up, the FAN54015 charge with an input current that keeps VBUS = VSP. When the VSP control loop is limiting the charge current, the SP bit (REG5[4]) is set. Table 8. VSP AS FUNCTION OF SP BITS (REG5[2:0]) SP (REG5[2:0]) DEC BIN HEX VSP 0 000 00 4.213 1 001 01 4.293 2 010 02 4.373 3 011 03 4.453 4 100 04 4.533 5 101 05 4.613 6 110 06 4.693 7 111 07 4.773 DEC BIN HEX VRSENSE (mV) 68 mW 100 mW 0 000 00 37.4 550 374 1 001 01 44.2 650 442 2 010 02 51.0 750 510 3 011 03 57.8 850 578 4 100 04 71.4 1050 714 5 101 05 78.2 1150 782 6 110 06 91.8 1350 918 7 111 07 98.6 1450 986 Table 10. VSAFE (VOREG LIMIT) AS FUNCTION OF VSAFE BITS (REG6[3:0]) VSAFE (REG6[3:0]) Safety Settings FAN54015 contain a SAFETY register (REG6) that prevents the values in OREG (REG2[7:2]) and IOCHARGE (REG4[6:4]) from exceeding the values of the VSAFE and ISAFE values. After VBAT exceeds VSHORT, the SAFETY register is loaded with its default value and may be written only before any other register is written. The entire desired Safety register value should be written twice to ensure the register bits are set. After writing to any other register, the SAFETY register is locked until VBAT falls below VSHORT. The ISAFE (REG6[6:4]) and VSAFE (REG6[3:0]) registers establish values that limit the maximum values of IOCHARGE and VOREG used by the control logic. If the host attempts to write a value higher than VSAFE or ISAFE to OREG or IOCHARGE, respectively; the VSAFE, ISAFE value appears as the OREG, IOCHARGE register value, respectively. DEC BIN HEX Max. OREG (REG2[7:2]) VOREG Max. 0 0000 00 100011 4.20 1 0001 01 100100 4.22 2 0010 02 100101 4.24 3 0011 03 100110 4.26 4 0100 04 100111 4.28 5 0101 05 101000 4.30 6 0110 06 101001 4.32 7 0111 07 101010 4.34 8 1000 08 101011 4.36 9 1001 09 101100 4.38 10 1010 0A 101101 4.40 11 1011 0B 101110 4.42 12 1100 0C 101111 4.44 13 1101 0D 110000 4.44 14 1110 0E 110001 4.44 15 1111 0F 110010 4.44 www.onsemi.com 22 FAN54015 Thermal Regulation and Protection this condition, VBUS must be driven from 5 V to GND with a high slew rate. Achieving this slew rate requires a 0 W short to the USB cable less than 10 cm from the connector. When the IC’s junction temperature reaches TCF (about 120°C), the charger reduces its output current to 550 mA to prevent overheating. If the temperature increases beyond TSHUTDOWN; charging is suspended, the FAULT bits are set to 101, and STAT is pulsed HIGH. In Suspend Mode, all timers stop and the state of the IC’s logic is preserved. Charging resumes at programmed current after the die cools to about 120°C. Additional qJA data points, measured using the FAN54015 evaluation board, are given in Table 11 (measured with TA = 25°C). Note that as power dissipation increases, the effective qJA decreases due to the larger difference between the die temperature and ambient. Charge Mode Battery Detection & Protection VBAT Over−Voltage Protection The OREG voltage regulation loop prevents VBAT from overshooting the OREG voltage by more than 50 mV when the battery is removed. When the PWM charger runs with no battery, the TE bit is not set and a battery is inserted that is charged to a voltage higher than VOREG; PWM pulses stop. If no further pulses occur for 30 ms, the IC sets the FAULT bits to 100, sets the STAT bits to 11, and pulses the STAT pin. Battery Detection During Charging The IC can detect the presence, absence, or removal of a battery if the termination bit (TE) is set. During normal charging, once VBAT is close to VOREG and the termination charge current is detected, the IC terminates charging and sets the STAT bits to 10. It then turns on a discharge current, IDETECT, for tDETECT. If VBAT is still above VOREG – VRCH, the battery is present and the IC sets the FAULT bits to 000. If VBAT is below VOREG – VRCH, the battery is absent and the IC: 1. Sets the registers to their default values. 2. Sets the FAULT bits to 111. 3. Resumes charging with default values after tINT. Table 11. EVALUATION BOARD MEASURED qJA Power (W) qJA 0.504 54°C/W 0.844 50°C/W 1.506 46°C/W Charge Mode Input Supply Protection Sleep Mode When VBUS falls below VBAT + VSLP, and VBUS is above VIN(MIN), the IC enters Sleep Mode to prevent the battery from draining into VBUS. During Sleep Mode, reverse current is disabled by body switching Q1. Battery Short−Circuit Protection If the battery voltage is below the short−circuit threshold (VSHORT); a linear current source, ISHORT, supplies VBAT until VBAT > VSHORT. Input Supply Low−Voltage Detection The IC continuously monitors VBUS during charging. If VBUS falls below VIN(MIN), the IC: 1. Terminates charging 2. Pulses the STAT pin, sets the STAT bits to 11, and sets the FAULT bits to 011. If VBUS recovers above the VIN(MIN) rising threshold after time tINT (about two seconds), the charging process is repeated. This function prevents the USB power bus from collapsing or oscillating when the IC is connected to a suspended USB port or a low−current−capable OTG device. System Operation with No Battery The FAN54015 continues charging after VBUS POR with the default parameters, regulating the VBAT line to 3.54 V until the host processor issues commands or the 15−minute timer expires. In this way, the FAN54015 can start the system without a battery. The FAN54015 soft−start function can interfere with the system supply with battery absent. The soft−start activates whenever VOREG, IINLIM, or IOCHARGE are set from a lower to higher value. During soft−start, the IIN limit drops to 100 mA for about 1 ms unless IINLIM is set to 11 (no limit). This could cause the system processor to fail to start. To avoid this behavior, use the following sequence. 1. Set the OTG pin HIGH. When VBUS is plugged in, IINLIM is set to 500 mA until the system processor powers up and can set parameters through I2C. 2. Program the Safety Register. 3. Set IINLIM to 11 (no limit). 4. Set OREG to the desired value (typically 4.18). 5. Reset the IO_LEVEL bit, then set IOCHARGE. 6. Set IINLIM to 500 mA if a USB source is connected. Input Over−Voltage Detection When the VBUS exceeds VBUSOVP, the IC: 1. Turns off Q3 2. Suspends charging 3. Sets the FAULT bits to 001, sets the STAT bits to 11, and pulses the STAT pin. When VBUS falls about 150 mV below VBUSOVP, the fault is cleared and charging resumes after VBUS is revalidated (see VBUS POR / Non−Compliant Charger Rejection). VBUS Short While Charging If VBUS is shorted with a very low impedance while the IC is charging with IINLIMIT = 100 mA, the IC may not meet datasheet specifications until power is removed. To trigger www.onsemi.com 23 FAN54015 During the initial system startup, while the charger IC is being programmed, the system current is limited to 500 mA for 1 ms during steps 4 and 5. This is the value of the soft−start ICHARGE current used when IINLIM is set to No Limit. If the system is powered up without a battery present, the CV bit should be set. When a battery is inserted, the CV bit is cleared. Table 14. DISABLE PIN AND CE BIT FUNCTIONALITY Charger Status / Fault Status The STAT pin indicates the operating condition of the IC and provides a fault indicator for interrupt driven systems. Raising the DISABLE pin stops t32S from advancing, but does not reset it. If the DISABLE pin is raised during t15MIN charging, the t15MIN timer is reset. Charge State STAT Pin 0 X OPEN X Normal Conditions OPEN 1 Charging LOW X DISABLE Pin CE HZ_MODE ENABLE 0 0 0 DISABLE X 1 X DISABLE X X 1 DISABLE 1 X X Operational Mode Control OPA_MODE (REG1[0]) and the HZ_MODE (REG1[1]) bits in conjunction with the FAULT state define the operational mode of the charger. Table 12. STAT PIN FUNCTION EN_STAT Charging Table 15. OPERATION MODE CONTROL Fault (Charging or Boost) 128 ms Pulse, then OPEN HZ_MODE OPA_MODE FAULT Operation Mode 0 0 0 Charge 0 X 1 Charge Configure The FAULT bits (R0[2:0]) indicate the type of fault in Charge Mode (see Table 13). Table 13. FAULT STATUS BITS DURING CHARGE MODE B1 B0 0 0 0 Normal (No Fault) 0 0 1 VBUS OVP 0 1 0 Sleep Mode 0 1 1 Poor Input Source 1 0 0 Battery OVP 1 0 1 Thermal Shutdown 1 1 0 Timer Fault 1 1 1 No Battery 1 0 Boost 1 X X High Impedance The IC resets the OPA_MODE bit whenever the boost is deactivated, whether due to a fault or being disabled by setting the HZ_MODE bit. Fault Bit B2 0 Fault Description BOOST MODE Boost Mode can be enabled if the IC is in 32−Second Mode with the OTG pin and OPA_MODE bits as indicated in Table 16. The OTG pin ACTIVE state is 1 if OTG_PL = 1 and 0 when OTG_PL = 0. If boost is active using the OTG pin, Boost Mode is initiated even if the HZ_MODE = 1. The HZ_MODE bit overrides the OPA_MODE bit. Table 16. ENABLING BOOST Charge Mode Control Bits Setting either HZ_MODE or CE through I2C disables the charger and puts the IC into High−Impedance Mode and resets t32S. If VBAT < VLOWV while in High−Impedance Mode, t32S begins running and, when it overflows, all registers (except SAFETY) reset, which enables t15MIN charging on versions with the 15−minute timer. When t15MIN overflows, the IC sets the CE bit and the IC enters High−Impedance Mode. If CE was set by t15MIN overflow, a new charge cycle can only be initiated through I2C or VBUS POR. Setting the RESET bit clears all registers. If HZ_MODE or CE bits were set when the RESET bit is set, these bits are also cleared, but the t32S timer is not started, and the IC remains in High−Impedance Mode. OTG_EN OTG Pin HZ_ MODE OPA_MODE BOOST 1 ACTIVE X X Enabled X X 0 1 Enabled X ACTIVE X 0 Disabled 0 X 1 X Disabled 1 ACTIVE 1 1 Disabled 0 ACTIVE 0 0 Disabled To remain in Boost Mode, the TMR_RST must be set by the host before the t32S timer times out. If t32S times out in Boost Mode; the IC resets all registers, pulses the STAT pin, sets the FAULT bits to 110, and resets the BOOST bit. VBUS POR or reading R0 clears the fault condition. www.onsemi.com 24 FAN54015 Boost PWM Control Table 17. Boost PWM Operating States The IC uses a minimum on−time and computed minimum off− time to regulate VBUS. The regulator achieves excellent transient response by employing current−mode modulation. This technique causes the regulator to exhibit a load line. During PWM Mode, the output voltage drops slightly as the input current rises. With a constant VBAT, this appears as a constant output resistance. The “droop” caused by the output resistance when a load is applied allows the regulator to respond smoothly to load transients with no undershoot from the load line. This can be seen in Figure 31 and Figure 40. Description Invoked When LIN Linear Startup VBAT > VBUS SS Boost Soft−Start VBUS < VBST BST Boost Operating Mode VBAT > UVLOBST and SS Completed Startup When the boost regulator is shut down, current flow is prevented from VBAT to VBUS, as well as reverse flow from VBUS to VBAT. LIN State When EN rises, if VBAT > UVLOBST, the regulator first attempts to bring PMID within 400 mV of VBAT using an internal 450 mA current source from VBAT (LIN State). If PMID has not achieved VBAT – 400 mV after 560 ms, a FAULT state is initiated. 350 Output Resistance (mW) Mode 325 300 275 SS State 250 When PMID > VBAT – 400 mV, the boost regulator begins switching with a reduced peak current limit of about 50% of its normal current limit. The output slews up until VBUS is within 5% of its setpoint; at which time, the regulation loop is closed and the current limit is set to 100%. If the output fails to achieve 95% of its setpoint (VBST) within 128 ms, the current limit is increased to 100%. If the output fails to achieve 95% of its setpoint after this second 384 ms period, a fault state is initiated. 225 200 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Battery Voltage, VBAT (V) Figure 40. Output Resistance (ROUT) VBUS as a function of ILOAD can be computed when the regulator is in PWM Mode (continuous conduction) as: V OUT + 5.07 * R OUT @ I LOAD BST State This is the normal operating mode of the regulator. The regulator uses a minimum tOFF − minimum tON modulation scheme. The minimum tOFF is propotional to VIN / VOUT, which keeps the regulator’s switching frequency reasonably constant in CCM. tON(MIN) is proportional to VBAT and is a higher value if the inductor current reached 0 before tOFF(MIN) in the prior cycle. To ensure the VBUS does not pump significantly above the regulation point, the boost switch remains off as long as FB > VREF. (eq. 1) At VBAT = 3.3 V, and ILOAD = 200 mA, VBUS would drop to: V OUT + 5.07 * 0.26 @ 0.2 + 5.018 V (eq. 2) At VBAT = 2.7 V, and ILOAD = 200 mA, VBUS would drop to: V OUT + 5.07 * 0.327 @ 0.2 + 5.005 V (eq. 3) PFM Mode If VBUS > VREFBOOST (nominally 5.07 V) when the minimum off−time has ended, the regulator enters PFM Mode. Boost pulses are inhibited until VBUS < VREFBOOST. The minimum on−time is increased to enable the output to pump up sufficiently with each PFM boost pulse. Therefore the regulator behaves like a constant on−time regulator, with the bottom of its output voltage ripple at 5.07 V in PFM Mode. Boost Faults If a BOOST fault occurs: 1. The STAT pin pulses. 2. OPA_MODE bit is reset. 3. The power stage is in High−Impedance Mode. 4. The FAULT bits (REG0[2:0]) are set per Table 18. www.onsemi.com 25 FAN54015 Restart After Boost Faults If boost was enabled with the OPA_MODE bit and OTG_EN = 0, Boost Mode can only be enabled through subsequent I2C commands since OPA_MODE is reset on boost faults. If OTG_EN = 1 and the OTG pin is still ACTIVE (see Table 16), the boost restarts after a 5.2 ms delay, as shown in Figure 41. If the fault condition persists, restart is attempted every 5 ms until the fault clears or an I2C command disables the boost. VBUS 0 560 BATTERY CURRENT VREG Pin B2 B1 B0 The 1.8 V regulated output on this pin can be disabled through I2C by setting the DIS_VREG bit (REG5[6]). VREG can supply up to 2 mA. This circuit, which is powered from PMID, is enabled only when PMID > VBAT and does not drain current from the battery. During boost, VREG is off. It is also off when the HZ_MODE bit (REG1[1]) = 1. 0 0 0 Normal (no fault) 0 0 1 VBUS > VBUSOVP 0 1 0 VBUS fails to achieve the voltage required to advance to the next state during soft−start or sustained (>50 μs) current limit during the BST state. Fault Description 1 VBAT < UVLOBST 1 0 0 N/A: This code does not appear. 1 0 1 Thermal shutdown 1 1 0 Timer fault; all registers reset. 1 1 1 N/A: This code does not appear. 64 Figure 41. Boost Response Attempting to Start into VBUS Short Circuit (Times in ms) Fault Bit 1 0 BOOST ENABLED Table 18. FAULT BITS DURING BOOST MODE 0 5200 450 mA Monitor Register (Reg10H) Additional status monitoring bits enable the host processor to have more visibility into the status of the IC. The monitor bits are real−time status indicators and are not internally debounced or otherwise time qualified. The state of the MONITOR register bits listed in High−Impedance Mode is only valid when VBUS is valid. Table 19. MONITOR REGISTER BIT DEFINITIONS STATE BIT# NAME 0 1 Active When 7 ITERM_CMP VCSIN – VBAT < VITERM VCSIN – VBAT > VITERM Charging with TE = 1 VCSIN – VBAT < 1 mV VCSIN – VBAT > 1mV Charging with TE = 0 VBAT < VSHORT VBAT > VSHORT Charging VBAT < VLOWV VBAT > VLOWV High−Impedance Mode VBAT < UVLOBST VBAT > UVLOBST Boosting Linear Charging Not Enabled Linear Charging Enabled Charging MONITOR 6 VBAT_CMP Address 10H 5 LINCHG 4 T_120 TJ < 120°C TJ > 120°C 3 ICHG Charging Current Controlled by ICHARGE Control Loop Charging Current Not Controlled by ICHARGE Control Loop 2 IBUS IBUS Limiting Charging Current Charge Current Not Limited by IBUS Charging 1 VBUS_VALID VBUS Not Valid VBUS is Valid VBUS > VBAT 0 CV Constant Current Charging Constant Voltage Charging Charging www.onsemi.com 26 Charging FAN54015 I2C INTERFACE The FAN54015’s serial interface is compatible with Standard, Fast, Fast Plus, and High−Speed Mode I2C−Bus specifications. The SCL line is an input and the SDA line is a bi−directional open−drain output; it can only pull down the bus when active. The SDA line only pulls LOW during data reads and signaling ACK. All data is shifted in MSB (bit 7) first. During a read from the FAN54015 (Figure 46, Figure 47), the master issues a Repeated Start after sending the register address and before resending the slave address. The Repeated Start is a 1−to−0 transition on SDA while SCL is HIGH, as shown in Figure 45. High−Speed (HS) Mode The protocols for High−Speed (HS), Low−Speed (LS), and Fast−Speed (FS) Modes are identical except the bus speed for HS Mode is 3.4 MHz. HS Mode is entered when the bus master sends the HS master code 00001XXX after a start condition. The master code is sent in Fast or Fast Plus Mode (less than 1 MHz clock); slaves do not ACK this transmission. The master then generates a repeated start condition (Figure 45) that causes all slaves on the bus to switch to HS Mode. The master then sends I2C packets, as described above, using the HS Mode clock rate and timing. The bus remains in HS Mode until a stop bit (Figure 44) is sent by the master. While in HS Mode, packets are separated by repeated start conditions (Figure 45). Slave Address Table 20. I2C SLAVE ADDRESS BYTE Part Type 7 6 5 4 3 2 1 0 FAN54015 1 1 0 1 0 1 0 R/W In hex notation, the slave address assumes a 0 LSB. The hex slave address for the FAN54015 is D4H and is D6H for all other parts in the family. Bus Timing As shown in Figure 42, data is normally transferred when SCL is LOW. Data is clocked in on the rising edge of SCL. Typically, data transitions shortly at or after the falling edge of SCL to allow ample time for the data to set up before the SDA Data change allowed SDA ACK(0) or NACK(1) SLADDR MS Bit Figure 45. Repeated Start Timing TSU SCL Read and Write Transactions Figure 42. Data Transfer Timing The figures below outline the sequences for data read and write. Bus control is signified by the shading of the packet, defined as Master Drives Bus and Slave Drives Bus . All addresses and data are MSB first. Each bus transaction begins and ends with SDA and SCL HIGH. A transaction begins with a START condition, which is defined as SDA transitioning from 1 to 0 with SCL HIGH, as shown in Figure 43. THD;STA Table 21. BIT DEFINITIONS FOR FIGURE 46, FIGURE 47, AND FIGURE 48 Slave Address MS Bit Symbol SCL A transaction ends with a STOP condition, which is defined as SDA transitioning from 0 to 1 with SCL HIGH, as shown in Figure 44. Slave Releases Master Drives START, see Figure 43 A ACK. The slave drives SDA to 0 to acknowledge the preceding packet. A NACK. The slave sends a 1 to NACK the preceding packet. R Repeated START, see Figure 45 P STOP, see Figure 44. Figure 44 t HD;STO ACK(0) or NACK(1) SCL Figure 44. Stop Bit www.onsemi.com 27 Definition S Figure 43. Start Bit SDA t HD;STA SCL TH SDA t SU;STA Slave Releases FAN54015 7 bits S 8 bits 0 Slave Address 0 A 8 bits 0 Reg Addr A 0 A Data P Figure 46. Write Transaction 7 bits S 8 bits 0 Slave Address 0 A 7 bits 0 Reg Addr A R 8 bits 0 Slave Address 1 A Data 1 A P Figure 47. Read Transaction REGISTER DESCRIPTIONS The nine FAN54015 user−accessible registers are defined in Table 22. Table 22. I2C REGISTER ADDRESS Register Address Bits Name REG# 7 6 5 4 3 2 1 0 CONTROL0 0 0 0 0 0 0 0 0 0 CONTROL1 1 0 0 0 0 0 0 0 1 OREG 2 0 0 0 0 0 0 1 0 IC_INFO 03 or 3BH 0 0 0 0 0 0 1 1 IBAT 4 0 0 0 0 0 1 0 0 SP_CHARGER 5 0 0 0 0 0 1 0 1 SAFETY 6 0 0 0 0 0 1 1 0 MONITOR 10h 0 0 0 1 0 0 0 0 Table 23. REGISTER BIT DEFINITIONS (This table defines the operation of each register bit for all IC versions. Default values are in bold text.) Bit Name Value Type TMR_RST OTG 1 W Writing a 1 resets the t32S timer; writing a 0 has no effect R Returns the OTG pin level (1 = HIGH) EN_STAT 0 CONTROL0 7 6 Register Address: 00 R/W 1 5:4 3 STAT BOOST 00 Prevents STAT pin from going LOW during charging; STAT pin still pulses to enunciate faults R Ready 01 Charge in progress 10 Charge done 11 Fault 0 FAULT Default Value = X1XX 0XXX Enables STAT pin LOW when IC is charging R 1 2:0 Description IC is not in Boost Mode IC is in Boost Mode R CONTROL1 Fault status bits: for Charge Mode, see Table 13; for Boost Mode, see Table 18 Register Address: 01 7:6 IINLIM 5:4 VLOWV 00 Default Value = 0011 0000 (30h) R/W Input current limit, see Table 7 R/W 3.4 V 01 3.5 V 10 3.6 V 11 3.7 V Weak battery voltage threshold www.onsemi.com 28 FAN54015 Table 23. REGISTER BIT DEFINITIONS (This table defines the operation of each register bit for all IC versions. Default values are in bold text.) (continued) Bit Name Value Type CONTROL1 3 Register Address: 01 TE 0 R/W 1 2 CE 0 HZ_MODE 0 R/W OPA_MODE 0 R/W R/W OREG 1 OTG_PL 0 0 Default Value = 0000 1010 (0Ah) R/W Charger output “float” voltage; programmable from 3.5 to 4.44V in 20mV increments; defaults to 000010 (3.54 V), see Table 3 R/W OTG pin active LOW 1 OTG_EN OTG pin active HIGH R/W 1 Disables OTG pin Enables OTG pin IC_INFO Register Address: 03 7:5 Vendor Code 4:2 PN 1:0 REV 100 00 Default Value = 10010100 (94h) R Identifies ON Semiconductor as the IC supplier R Part number bits, see the Ordering Info on page 31 R IC Revision, revision 1.X, where X is the decimal of these three bits IBAT Register Address: 04 7 RESET 1 W 6:4 IOCHARGE Table 5 R/W 3 Reserved 1 R 2:0 ITERM Table 6 R/W SP_CHARGER Reserved 0 R 6 DIS_VREG 0 R/W 1 Writing a 1 resets charge parameters, except the Safety register (Reg6), to their defaults: writing a 0 has no effect; read returns 1 Programs the maximum charge current, see Table 5 Unused Sets the current used for charging termination, see Table 6 0 0 R/W EN_LEVEL 0 2:0 VSP Table 8 1.8 V regulator is ON Output current is controlled by IOCHARGE bits Voltage across RSENSE for output current control is set to 34 mV (500 mA for RSENSE = 68 mW and 340 mA for 100 mW) R 1 3 Default Value = 001X X100 Unused 1.8 V regulator is OFF 1 SP Default Value = 1000 1001 (89h) Register Address: 05 7 IO_LEVEL See Table 16 Charge Mode Register Address: 02 7:2 4 Not High−Impedance Mode Boost Mode OREG 5 Charger enabled High−Impedance Mode 1 0 Disable charge current termination Charger disabled 1 0 Default Value = 0011 0000 (30h) Enable charge current termination 1 1 Description Special charger is not active (VBUS is able to stay above VSP) Special charger has been detected and VBUS is being regulated to VSP R 1 DISABLE pin is LOW DISABLE pin is HIGH R/W SAFETY Special charger input regulation voltage, see Table 8 Register Address: 06 Default Value = 0100 0000 (40h) 7 Reserved 0 R Bit disabled and always returns 0 when read back 6:4 ISAFE Table 9 R/W Sets the maximum IOCHARGE value used by the control circuit, see Table 9 3:0 VSAFE Table 10 R/W Sets the maximum VOREG used by the control circuit, see Table 10 www.onsemi.com 29 FAN54015 Table 23. REGISTER BIT DEFINITIONS (This table defines the operation of each register bit for all IC versions. Default values are in bold text.) (continued) Bit Name Value Type MONITOR Description Register Address: 10h (16) 7 ITERM_CMP 6 VBAT_CMP 5 See Table 19 See Table 19 R ITERM comparator output, 1 when VRSENSE > ITERM reference R Output of VBAT comparator LINCHG R 30 mA linear charger ON 4 T_120 R Thermal regulation comparator; when = 1 and T_145 = 0, the charge current is limited to 22.1 mV across RSENSE 3 ICHG R 0 indicates the ICHARGE loop is controlling the battery charge current 2 IBUS R 0 indicates the IBUS (input current) loop is controlling the battery charge current 1 VBUS_VALID R 1 indicates VBUS has passed validation and is capable of charging 0 CV R 1 indicates the constant−voltage loop (OREG) is controlling the charger and all current limiting loops have released PCB LAYOUT RECOMMENDATIONS Bypass capacitors should be placed as close to the IC as possible. In particular, the total loop length for CMID should be minimized to reduce overshoot and ringing on the SW, PMID, and VBUS pins. All power and ground pins must be routed to their bypass capacitors, using top copper whenever possible. Copper area connecting to the IC should be maximized to improve thermal performance if possible. Figure 48. PCB Layout Recommendations www.onsemi.com 30 FAN54015 ORDERING INFORMATION Part Number FAN54015UCX FAN54015BUCX (Note 8) Temperature Range −40 to 85°C Package 20−Bump, Wafer−Level Chip−Scale Package (WLCSP), 0.4 mm Pitch, Estimated Size: 1.96 x 1.87 mm (Pb−Free) PN Bits: IC_INFO[4:2] Shipping† 101 3000 / Tape & Reel 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 8. FAN54015BUCX includes backside lamination. ON Semiconductor is licensed by the Philips Corporation to carry the I2C bus protocol. www.onsemi.com 31 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WLCSP20 1.96x1.87x0.586 CASE 567SL ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON16608G WLCSP20 1.96x1.87x0.586 DATE 30 NOV 2016 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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