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FAN6208
Secondary-Side Synchronous Rectifier Controller for
LLC Topology
Features
Description
Specialized SR Controller for LLC or LC Resonant
Converters
Secondary-Side Timing Detection with Timing
Estimator
Gate-Shrink Function to Prevent Shoot-Through
During Load and Line Transient
Green-Mode Function for Higher Efficiency at LightLoad Condition
Programmable Dead Time between Primary-Side
Gate Drive Signal and SR Drive Signal
Advanced Output-Short / Overload Protection
Based on the Feedback Information
Internal Over-Temperature Protection (OTP)
Optimal timing circuits and protection functions are
integrated in an 8-pin SOP package, which allows highefficiency power supply design with fewer components.
VDD Pin Over-Voltage Protection (OVP)
Related Resources
Applications
FAN6208 is a synchronous rectification (SR) controller
for isolated LLC or LC resonant converters that can
drive two individual SR MOSFETs emulating the
behavior of rectifier diodes. FAN6208 measures the SR
conduction time of each switching cycle by monitoring
the drain-to-source voltage of each SR and determines
the optimal timing of the SR gate drive. FAN6208 uses
the change of opto-coupler diode current to adaptively
shrink the duration of SR gate drive signals during load
transients to prevent shoot-through. To improve lightload efficiency, Green-Mode operation is employed,
which disables the SR drive signals, minimizing gate
drive power consumption at light-load condition.
LCD TV
FAN6208 Product Folder
PC Power
Open-Frame SMPS
Ordering Information
Part Number
FAN6208MY
Operating Temperature Range
Package
Packing Method
-40°C to +105°C
8-Pin Small Outline Package (SOP)
Tape & Reel
© 2010 Fairchild Semiconductor Corporation
FAN6208 • Rev. 1.0.5
www.fairchildsemi.com
FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology
October 2014
Secondary-Side
Primary-Side
VIN
VO
Lr IP
Lm
Im
DETL1 GATE1
DETL2 GND
Cr
RP
GATE2
FD
VDD
FAN6208
Figure 1. Typical Application
Block Diagram
DETL1
Internal Bias
Maximum
On-Time
Function
VDD
R
Timing
Estimator
UVLO
7.5/8.5
Q
S
GATE1
DET
Detector
Minimum
Re-Trigger
Function
Green Mode
FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology
Application Diagram
Lock
Functiom
GND
DETL2
Maximum
On-Time
Function
RP
Program
Dead Time
& Green Mode
R
Timing
Estimator
Q
S
GATE2
DET
Detector
Minimum
Re-Trigger
Function
FD
Feedback
Detection
Function
Figure 2. Block Diagram
© 2010 Fairchild Semiconductor Corporation
FAN6208 • Rev. 1.0.5
www.fairchildsemi.com
2
FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology
Marking Information
F- Fairchild Logo
Z- Plant Code
X- Year Code
Y- Week Code
TT: Die Run Code
T - Package Type (M = SOP)
P - Y: Green Package
M - Manufacture Flow Code
6208
6208
TPM
Figure 3. Top Mark
Pin Configuration
GATE1
GND
GATE2
VDD
8
7
6
5
1
2
3
4
DETL1
DETL2
RP
FD
Figure 4. Pin Assignments
Pin Definitions
Pin #
Name
Description
1
DETL1
Low Detect provides low-voltage detection of VDS of SR MOSFET1.
2
DETL2
Low Detect provides low-voltage detection of VDS of SR MOSFET2.
3
RP
Dead Time Programming Resistor programs H/L frequency version and dead time.
4
FD
Feedback Detection is used for short-circuit protection and gate shrink.
5
VDD
6
GATE2
7
GND
8
GATE1
Power Supply
Driver Output. The totem-pole output driver for driving the SR MOSFET2.
Ground
Driver Output. The totem-pole output driver for driving the SR MOSFET1.
© 2010 Fairchild Semiconductor Corporation
FAN6208 • Rev. 1.0.5
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VDD
Supply Voltage
30
V
VFD
Voltage on FD Pin
30
V
VLV
Voltage on DETL1, DETL2, RP Pins
-0.3
7.0
V
PD
Power Dissipation
350 mW
at TA=90°C
1000 mW
at TA=25°C
ΘJA
Junction–to-Ambient Thermal Resistance
130
°C/W
ΨJT
Junction-to-Top Thermal Characteristics
45
°C/W
TJ
TSTG
TL
ESD
Operating Junction Temperature
Internally Limited
°C
Storage Temperature Range
-55
+150
°C
+260
°C
Lead Temperature (Wave Soldering or IR, 10 Seconds)
Human Body Model, JESD22-A114
6
Charged Device Model, JESD22-C101
2
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
Parameter
Operating Ambient Temperature
© 2010 Fairchild Semiconductor Corporation
FAN6208 • Rev. 1.0.5
Min.
Max.
Unit
-40
+105
°C
FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology
Absolute Maximum Ratings
www.fairchildsemi.com
4
VDD=20 V, TA=25C, unless otherwise specified. All voltages are with respect to GND unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
28
V
VDD Section
VDD
DC Supply Voltage
VTH-OFF
IDD-OP1
Operating Current
VDD=12 V,
DETL=50 KHz, CL=6 nF,
RRP=24 K
7.0
8.5
10.0
mA
IDD-OP2
Operating Current
VDD=12 V,
DETL=100 KHz
2.4
3.2
4.0
mA
IDD-ST
Startup Current
VDD=8 V
180
300
500
μA
9.3
9.7
10.1
V
VTH-ON1 VTH-ON2 On Threshold Voltage
VTH-OFF1
VTH-OFF2
Off Threshold Voltage
8.3
8.8
9.3
V
VDD-OVP1
VDD-OVP2
VCC Over-Voltage
Protection
26
27
28
V
VDD-OVP-HYS1
VDD-OVP-HYS2
VCC Over-Voltage
Protection Hysteresis
1.3
1.8
2.3
V
tOVP1,tOVP2
VCC Over-VoltageProtection Debounce
30
60
100
μs
VDD=12 V,
Threshold Voltage for LOW
DETL=50 KHz, CL=6 nF,
Detection of DETL
RRP=24 KΩ
1.7
2.0
2.3
V
Delay from DETL LOW to
SR Gate Turn-On
tDB+ tPD+ tR
300
350
400
ns
VDD=12 V, DETL Pin
Floating
4.5
DETL Section
VDETL1
VDETL2
tSR-ON-DETL1
tSR-ON-DETL2
VDETL-FLOATING1
DETL Floating Voltage
VDETL-FLOATING2
V
IDETL-SOURCE1
IDETL-SOURCE2
DETL Source Current
VDETL1=0 V
40
50
60
μA
tDETL_Green_LF1
tDETL_Green_LF2
DETL LOW Time
Threshold for Green Mode
at Low-Frequency
Operation
VRP < 1.5 V
3.50
3.75
4.00
μs
DETL LOW Time
tDET(L)_Green_HF1 Threshold for Green Mode
tDET(L)_Green_HF2 at High-Frequency
Operation
VRP > 1.5 V
1.75
1.90
2.05
μs
FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology
Electrical Characteristics
Thermal Shutdown
Shutdown Temperature
TSHUTDOWN
Temperature Rising,
VDD=15 V
Hysteresis
TSTARTUP
Startup Temperature
140
20
Before Startup
°C
120
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN6208 • Rev. 1.0.5
www.fairchildsemi.com
5
VDD=20 V, TA=25°C, unless otherwise specified. All voltages are with respect to GND unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
10
12
14
V
0.5
V
Gate Section
Gate Output Voltage
Maximum (Clamping)
VDD=20 V
VOL1 VOL2
Gate Output Voltage LOW
VDD=12 V; IO=100 mA
VOH1VOH2
Gate Output Voltage HIGH
VDD=12 V; IO=100 mA
9
tR1 tR2
Rising Time
VDD=12 V; CL=6 nF;
VGATE=2 V to 9 V
30
70
120
ns
tF1 tF2
Falling Time
VDD=12 V; CL=6 nF;
VGATE=9 V to 2 V
30
50
70
ns
tPD_HIGH_DETL1
tPD_HIGH_DETL2
Propagation Delay to Gate
Output HIGH (DETL
Trigger)
tR: 0 V~2 V, VDD=12 V
(DET Floating)
120
ns
tPD_LOW_ DETL1
tPD_LOW_ DETL2
Propagation Delay to Gate
Output LOW (DETL
Trigger)
tF: 100%~90%, VDD=12 V
(DET Floating)
120
ns
Maximum On-Time
Trim Maximum On-Time
9.0
10.5
12.0
μs
tINHIBIT_LF1
tINHIBIT_LF2
Gate Inhibit Time (from
Turn-Off to Next Turn-On)
VRP < 1.5 V
1.8
2.1
2.5
μs
tINHIBIT_HF1
tINHIBIT_HF2
Gate Inhibit Time (from
Turn-Off to Next Turn-On)
VRP > 1.5 V
1.25
1.45
1.70
μs
tBLANKING1
tBLANKING2
Blanking Time for SR TurnOff Triggered by DETL
High (Minimum On-Time)
VZ1 VZ2
tON_MAX1
tON_MAX2
KR
Gate ON-Time Increase
Rate Between Two
Consecutive Cycles
tON(n) / tON(n-1) %
V
300
ns
140
%
Timing Estimator Section
tDW
Detection Window for
Insufficient Dead Time
(from Gate Turn-Off to
DETL HIGH)
tSHRINK-DT
Gate Shrink Time by
Insufficienct Dead Time
tDEAD
tDB
tSHRINK-RNG
tGreen_DH
80
125
150
ns
RRP=20 KΩ, tDETL=5 μs
1.00
1.25
1.50
μs
Dead Time by Timing
Estimator (70 kHz ~
140 kHz, VRP < 1.5 V)
tDETL=4 μs, RRP=20 KΩ
210
300
390
tDETL=6 μs, RRP=20 KΩ
570
720
870
Dead Time by Timing
Estimator (160kHz ~
240 kHz, VRP > 1.5V)
tDETL=2.5 μs, RRP=43 KΩ
220
320
420
tDETL=3.8 μs, RRP=43 KΩ
560
670
780
ns
DETL HIGH-to-LOW
Debounce Time for Gate
Turn-on Trigger
150
ns
Gate Shrink by DETL
Ringing around Zero
1.2
μs
DETL Pull-HIGH Time
Threshold for Green Mode
18
24
30
FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology
Electrical Characteristics
μs
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN6208 • Rev. 1.0.5
www.fairchildsemi.com
6
VDD=20 V, TA=25°C, unless otherwise specified. All voltages are with respect to GND unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Feedback Detection (FD) Section
∆V1% ∆V2%
Feedback Increase
Threshold for Gate Shrink
tSHRINK-FD
Gate Shrink by Feedback
Detection
tD-SHRINK-FD
Gate-Shrink Duration by
Feedback Detection
60
90
120
μs
VDD-VFD.SCP
Short-Circuit Protection
(SCP) Threshold by
Feedback Detection
200
270
340
mV
Debounce Time for ShortCircuit Protection (SCP)
12
16
20
μs
RP Source Current
38.5
41.5
44.5
μA
VRPO
RP Open Protect
3.40
3.65
3.90
V
VRPS
RP Short Protect
0.25
0.30
0.35
V
tRPOS
RP Open/Short Debounce
1.6
2.0
2.4
μs
VRPHL
H/L Frequency Threshold
1.40
1.46
1.52
V
tDB-SCP
[(VDD-VFD)n+1/(VDD-VFD)n]
120
%
1.4
μs
RP Section
IRP
Figure 5. tDEAD vs. tDETL RP Curve for LF Mode
© 2010 Fairchild Semiconductor Corporation
FAN6208 • Rev. 1.0.5
FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology
Electrical Characteristics
Figure 6. tDEAD vs. tDETL RP Curve for HF Mode
www.fairchildsemi.com
7
VDS.SR1
Operation Principle
FAN6208 is a secondary-side synchronous rectifier
controller for LLC or LC resonant converters that drive
two synchronous rectifier MOSFETs. Figure 7 is the
simplified circuit diagram of an LLC converter. The
FAN6208 determines SR MOSFET turn-on/off timing by
detecting the drain-to-source voltage of each SR
MOSFET. The key waveforms for LLC resonant
converter for below resonance and above resonance
are shown in Figure 8 and Figure 9, respectively.
(a) Heavy-Load Condition
40
20
0
Ip
1
0
-1
ISR1
Secondary-Side Synchronous Rectifiers
VIN
8
6
4
SR1
IP
2
0
VO
Lr
Lm
VDS.SR1
(b) Light-Load Condition
DETL1 GATE1
DETL2 GND
Cr
RP
GATE2
FD
VDD
40
20
FAN6208
LLC Resonant Converter
0
Ip
SR2
1
Figure 7. Simplified Schematic of LLC Converter
0
VDS.SR1
(a) Heavy-Load Condition
-1
ISR1
40
8
20
6
4
0
2
Ip
0
1
Figure 9. Key Waveforms of LLC Resonant Converter for
Above Resonance Operation
0
-1
Timing Estimator
ISR1
Figure 10 shows the timing diagram for FAN6208. Once
the body diode of SR begins conducting, the drain-tosource voltage drops to zero, which causes DETL pin
voltage to drop to zero. FAN6208 turns on the MOSFET
after tON-ON-DETL (about 350 ns), when voltage on DETL
drops below 2 V. As depicted in Figure 11, the turn-on
delay (after tSR-ON-DETL) is the sum of debounce time
(150 ns) and propagation delay (200 ns).
10
8
6
4
2
0
VDS.SR1
(b) Light-Load Condition
40
FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology
Function Description
FAN6208 measures the SR conduction duration (tDETL),
during which DETL stays lower than 2 V, and uses this
information to determine the turn-off instant of SR gates
of the next switching cycle. The turn-off timing is
obtained by subtracting a dead time (tDEAD) from the
measured SR conduction duration of the previous
switching cycle. The dead time can be programmed
using a resistor on the RP pin and the relationship
between the dead time and SR conduction duration
(tDETL) for different resistor values on RP pin is given in
Figure 5.
20
0
Ip
1
0
-1
ISR1
8
6
4
2
0
Figure 8. Key Waveforms of LLC Resonant Converter for
Below Resonance Operation
© 2010 Fairchild Semiconductor Corporation
FAN6208 • Rev. 1.0.5
www.fairchildsemi.com
8
2V
tSR-ON-DETL
tSR-ON-DETL
VGATE
VGATE
(a) When insufficient dead time is detected in the
previous switching cycle. When the DETL goes
HIGH within 125 ns of detection window after SR
gate is turned off, the SR gate drive signal in the
next switching cycle is reduced by tSHRINK-DT (about
1.25 µs) to increase the dead time, as shown in
Figure 12.
tDETL (n) - tDEAD
tDETL (n-1) - tDEAD
tDETL (n)
tDETL (n+1)
VDET
Figure 10. SR Gate Timing Diagram
2V
tSR-ON-DETL
DETL1
2V
350ns
VDETL1
tDB
125ns
Detection window
tPD
VGATE
GATE1 150ns 200ns
tDETL_LOW (n) – tDEAD– tSHRINK
tDETL_LOW (n-1) - tDEAD
tSR-ON-DETL
Shrink
VGATE
tDETL_LOW (n)
tDETL_LOW (n+1)
350ns
DETL1
Figure 12. Gate Shrink by Minimum Dead Time
Detection Window
2V
VDETL1
tDB
tPD
GATE1
(b) When the feedback information changes fast.
FAN6208 monitors the current through the optocoupler diode by measuring the voltage across the
resistor in series with the opto-coupler diode, as
depicted in Figure 13. If the feedback current
through the opto-coupler diode increases by more
than 20% of the feedback current of the previous
switching cycle, the SR gate signal is shrunk by
tSHRINK-FD (about 1.4 µs) for tD-SHRINK-FD (about 90 µs),
as shown in Figure 14.
150ns 200ns
tSR-ON-DETL
350ns
DETL1
VDETL1
2V
tDB
GATE1
tPD
150ns 200ns
VDETL1
DETL1
LLC
Resonant
Converter
2V
tDB
GATE1 150ns
tPD
200ns
VO
R2
FAN6208 —Secondary-Side Synchronous Rectifier Controller for LLC Topology
increases fast and switching transition of the primaryside MOSFETs takes place before the turn-off
command of SR is given. To prevent the shoot-through,
FAN6208 has gate-shrink functions. Gate shrink occurs
under three conditions:
VDET
R1
Opto-Couple
Diode
DETL1 GATE1
DETL2
Figure 11. DETL Debounce (Blanking) Time
GND
RP
GATE2
FD
VDD
FAN6208
TL431
Gate-Shrink Functions
In normal operation, the turn-off instant is determined by
subtracting a dead time (tDEAD) from the measured SR
conduction duration of the previous switching cycle, as
shown in Figure 10. This allows proper driving timing for
SR MOSFETS when the converter is in steady state and
the switching frequency does not change much.
However, this control method may cause shoot-through
of SR MOSFETs when the switching frequency
© 2010 Fairchild Semiconductor Corporation
FAN6208 • Rev. 1.0.5
Figure 13. Typical Application Circuit
www.fairchildsemi.com
9
tD-SHRINK-FD
RP Pin Open Protection Region
(VDD - FD)n
VRPO (3.65V)
(VDD - FD)n-2
FD
(VDD - FD)n/(VDD - FD)n-1 > 120%
RRP = 68K
VRP = 2.822V
tSHRINK-FD
GATE1
tDEAD
High- Frequency Mode
RRP = 56K
VRP = 2.324V
DETL1
VRPHL (1.46V)
tSHRINK-FD
GATE2
tDEAD
RRP = 30K
VRP = 1.245V
Low-Frequency Mode
RRP = 24K
VRP = 0.996V
DETL2
VRPS (0.3V)
RP Pin Short Protection Region
Figure 16.
Figure 14. Gate Shrink by Feedback Detection
RP Pin Operation
To handle abnormal conditions for IC pins, the RP pin
also provides open/short protection. When VRP is less
than VRPS (0.3 V) or VRP is higher than VRPO (3.65 V),
the protection is triggered. Figure 17 shows the RP pin
short protection timing sequence. If VRP < VRPS (0.3 V)
for longer than tRPOS (2 µs), FAN6208 is disabled. Figure
18 shows the RP pin open protection timing sequence.
If VRP > VRPO (3.65 V) for longer than tRPOS (2 µs),
FAN6208 is disabled.
(c) When the DETL voltage has ringing around zero. As
depicted in Figure 8, the drain voltage of SR has
ringing around zero at light-load condition after the
switching transition of the primary-side switches.
When DETL voltage rises above 2 V within 350 ns
after DETL voltage drops to zero and stays above
2 V longer than 150 ns, the gate is shrunk by 1.2 µs
(tSHRINK-RNG), as shown in Figure 15.
tRPOS
RP
tRPOS
tRPOS
VRP = IRP×RRP
VDETL
VRPS
>150ns
200ns (tPD)
RP Short Protection Area
GATE1
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