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FAN6224
Synchronous Rectification Controller for Flyback and
Forward Freewheeling Rectification
Features
mWSaver™ Technology:
Internal Green Mode to Stop SR Switching for
Lower No-Load Power Consumption
-
Description
300 A Ultra-Low Green Mode Operating
Current
Synchronous Rectification Controller
Suited for High-Side and Low-Side of Flyback
Converters in QR, DCM, and CCM Operation
Suited for Forward Freewheeling Rectification
PWM Frequency Tracking with Secondary-Side
Winding Voltage Detection
140 kHz Maximum Operation Frequency
VDD Pin Over-Voltage Protection (OVP)
LPC Pin Open/Short Protection
RES Pin Open/Short Protection
RP Pin Open/Short Protection
FAN6224 is a secondary-side Synchronous Rectification
(SR) controller to drive SR MOSFET for improved
efficiency. The IC is suitable for flyback converters and
forward freewheeling rectification.
FAN6224 can be applied in Continuous or
Discontinuous Conduction Mode (CCM and DCM) and
Quasi-Resonant (QR) flyback converters based on a
proprietary linear-predict timing-control technique. The
benefits of this technique include a simple control
method without current-sense circuitry to accomplish
noise immunity.
With PWM frequency tracking and secondary-side
winding voltage detection, FAN6224 can operate in both
fixed- and variable-frequency systems up to 140kHz.
FAN6224 detects output load condition and determines
adjustable loading levels for Green Mode. In Green
Mode, the SR controller stops all SR switching operation
to reduce the operating current. Power consumption is
maintained at a minimum level in light-load condition.
Internal Over-Temperature Protection (OTP)
SOP-8 Package Available
Applications
AC-DC NB Adapters
Open-Frame SMPS
Ordering Information
Part Number
Operating
Temperature Range
Package
Packing
Method
FAN6224M
-40°C to +105°C
8-Lead, Small Outline Package (SOP-8)
Tape & Reel
© 2013 Fairchild Semiconductor Corporation
FAN6224 • Rev. 1.4
www.fairchildsemi.com
FAN6224 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
September 2015
VIN
N1
N2
VOUT
ISR
N3
VIN
N1
Q2
Q2
ISR
VDET VOUT
VDET
Q1
GATE
3
R1
VLPC
LPC
RP
RES
FAN6224
8
7
5
RES
N2
Q1
VRES
4
1
8
VLPC
6
RRP
Figure 2. Flyback High-Side SR
VDET
VIN
Q1
VOUT
Q3
ISR
GATE
3
R1
VLPC
LPC
VDD
5
8
FAN6224
RP 1
4
R2
7
RES
6
GND AGND
R3
VRES
R4
RRP
CRP
Figure 3. Forward Freewheeling Rectification
R1
LPC
GND AGND
CRP
RRP
Q2
4
1
R4
R4
GATE
3
FAN6224
7
VRES
6
GND AGND
Figure 1. Flyback Low-Side SR
© 2013 Fairchild Semiconductor Corporation
FAN6224 • Rev. 1.4
VDD
R3
R3
RP
R2
CRP
VDD
5
R2
FAN6224 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
Typical Application Diagrams
www.fairchildsemi.com
2
VDD
5
GATE
3
Internal Bias
RP 1
-
Timing
Calculation
0.35V +
Setting High/Low
Frequency Mode
Calculate
VLPC-EN
Protection
VCT
Adjustable
Green Mode
S&H
+
tGREEN-ON/OFF
10.5V/10.1V
tGREEN-ON/OFF
LPC 8
-
S
Q
R
Q
Drive
PWM Block
GATE
-
1.45V
+
Maximum
Period
Internal OTP
2 AGND
tLPC-EN
blanking
+
Causal
Function
Gate Expand Limit
RESET
OVP
-
27.5V/26V
2.5V
Green Mode
+
VLPC-EN
6 AGND
VCT
Enable
RESET
iCHR
iDISCHR
S&H
1µA/V
CT
0.256µA/V
RESET
Fault Timing
Protection
Protection
S&H
7
RES
Figure 4.
© 2013 Fairchild Semiconductor Corporation
FAN6224 • Rev. 1.4
Block Diagram
4
GND
FAN6224 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
Internal Block Diagram
www.fairchildsemi.com
3
: Fairchild Logo
Z: Plant Code
X: Year Code
Y: Week Code
TT: Die Run Code
T: Package Type (M = SOP)
M: Manufacturing Flow Code
ZXYTT
6224
TM
Figure 5.
Top Mark
Pin Configuration
LPC
8
RES AGND VDD
7
6
5
FAN6224
1
RP
2
3
4
AGND GATE GND
Figure 6.
Pin Configuration
Pin Definitions
Pin #
Name
Description
1
RP
2, 6
AGND
Signal Ground.
3
GATE
Driver Output. The totem-pole output driver for driving the power MOSFET.
4
GND
Ground. MOSFET source connection.
5
VDD
Power Supply. The threshold voltages for startup and turn-off are 10.5 V and 10.1 V,
respectively.
7
RES
Reset Control of Linear Predict. RES pin is used to detect output voltage level through a
voltage divider. An internal current source, IDISCHR, is modulated by this voltage level on the
RES pin.
8
LPC
Winding Detection. This pin is used to detect the voltage on the winding during the on-time
period of the primary GATE.
Programmable. A resistor paralleled with a capacitor is connected to RP pin and reference
ground externally. The timing to enter / exit Green Mode is programmable by the resistor, while
the range of operating frequency is programmable by the capacitor.
© 2013 Fairchild Semiconductor Corporation
FAN6224 • Rev. 1.4
FAN6224 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
Marking Information
www.fairchildsemi.com
4
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
30
V
VDD
DC Supply Voltage
VLPC
Voltage on LPC Pin (TA=25°C)
-0.3
7.0
V
VRES
Voltage on RES Pin (Continuously in -0.5 V) (TA=25°C)
-1.5
7.0
V
VRP
Voltage on RP Pin (TA=25°C)
-0.3
7.0
V
PD
Power Dissipation (TA=25°C)
0.8
W
ΘJA
Thermal Resistance (Junction-to-Air)
151
°C/W
ΘJC
Thermal Resistance (Junction-to-Case)
TSTG
Storage Temperature Range
TL
ESD
-55
Lead Temperature (Soldering) 10s
Electrostatic Discharge
Capability
58
°C/W
150
°C
260
°C
Human Body Model, JESD22-A114
5500
Charged Device Model, JESD22-C101
2000
V
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
VLPC
Voltage on LPC Pin
VRES
Voltage on RES Pin
VRP
Voltage on RP Pin
© 2013 Fairchild Semiconductor Corporation
FAN6224 • Rev. 1.4
Condition
Min.
Continuous Operation
0.5
Max.
Unit
4.8
V
4.8
V
2.5
V
FAN6224 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
Absolute Maximum Ratings
www.fairchildsemi.com
5
VDD=15 V and TA=25°C, unless otherwise noted.
Symbol
VOP
Parameter
Condition
Continuously Operating Voltage
Min.
Typ.
VDD-OFF
Max.
Unit
VDD-OVP
V
VDD-ON
Turn-On Threshold Voltage
9.5
10.5
11.5
V
VDD-OFF
Turn-Off Threshold Voltage
9.1
10.1
11.1
V
VDD-HYST
Hysteresis Voltage for Turn-On /
Turn-Off Threshold
0.1
0.7
V
8
mA
IDD-OP
VDD=15 V, LPC=65 kHz,
CL=6000 pF
Operating Current
7
IDD-GREEN
Operating Current in Green Mode VDD=15 V
300
400
µA
VDD-OVP
VDD Over-Voltage Protection
26.0
27.5
29.0
V
Hysteresis Voltage for VDD OVP
1.1
1.5
1.9
V
VDD-OVP-HYST
tVDD-OVP
(3)
VDD OVP Debounce Time
100
µs
Output Driver for internal SR Mosfet Section
VZ
Output Voltage Maximum
(Clamp)
VOL
Output Voltage LOW
VDD=12 V, IO=50 mA
VOH
Output Voltage HIGH
VDD=12 V, IO=50 mA
9
tR
Rising Time
VDD=12 V, CL=6 nF,
GATE=2 V~9 V
30
70
120
ns
tF
Falling Time
VDD=12 V, CL=6 nF,
GATE=9 V~2 V
20
50
100
ns
tPD_HIGH_LPC
Propagation Delay to GATE
HIGH (LPC Trigger)
tR:0%~10%, VDD=12 V
150
250
ns
tPD_LOW_LPC
Propagation Delay to GATE LOW
tF:100%~90%,VDD=12 V
(3)
(LPC Trigger
tMAX-PERIOD
10
Limitation between LPC Rising
Edge to Gate Falling Edge
12
14
V
0.5
V
V
150
ns
fs=65 kHz
24.0
29.5
35.0
fs=140 kHz
12.5
15.5
18.5
µs
LPC Section
tBNK
tLPC-SMP
(3)
150
Blanking Time for Charging CT
LPC Sampling Timing of Previous
Cycle
ns
fs=65 kHz,
RRP=75 k~200 k,
CRP=100 nF
0.9
1.1
1.3
µs
fs=140 kHz,
RRP=75 k~200 k,
CRP=1 nF
0.5
0.6
0.7
µs
0
0.1
0.2
V
1.38
1.45
1.54
V
VLPC-SOURCE
Lower Clamp Voltage
Source ILPC=10 µA
VLPC-HIGH-EN
Threshold Voltage for LPC to
Enable SR
VLPC-HIGH>VLPC-HIGH-EN, SR
Enable
VEN-CLAMP
SR Enable Threshold Clamp
(3)
Voltage
VLPC-EN=2.5 V at VLPC-HIGH
>3 V
VLPC-TH-HIGH
Threshold Voltage on LPC Rising
(3)
Edge
VLPC-CLAMP-H
VLPC High Clamping Voltage
VLPC>VLPC-CLAMP-H
5.7
VLPC-DIS
Threshold Voltage of VLPC to
Disable SR Gate Switching
VLPC>VLPC-DIS
4.8
tLPC-EN-RES
No LPC Signal, Reset VLPC-EN
(3)
2.5
V
1.22
V
6.2
95
6.7
V
5.5
V
FAN6224 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
Electrical Characteristics
s
Continued on the following page…
© 2013 Fairchild Semiconductor Corporation
FAN6224 • Rev. 1.4
www.fairchildsemi.com
6
VDD=15 V and TA=25°C, unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
RES Section
(3)
2.5
VRES Sampling Time
VRES-EN
Threshold Voltage of VRES to
Enable SR Gate Switching
VRES>VRES-EN
1.3
1.6
2.0
V
VRES-CLAMP-H
VRES High Clamping Voltage
VRES>VRES-CLAMP-H
5.7
6.2
6.7
V
0
0.2
KRES-DROP
VRES-SOURCE
tSR_gate=5 µs
µs
tRES-SMP
(3)
VRES Drop Protection Ratio
VRES Low Clamping Voltage
85
VRES[n+1]VLPCEN=0.875 x VLPC-HIGH
1
µA/V
0.256
µA/V
VRES=3 V,VLPC=3 V CRP=100 nF
3.65
3.90
4.15
fs=65 kHz, RRP=75 k~200 k,
CRP=100 nF
0.9
1.1
1.3
fs=140 kHz, RRP=75 k~200 k,
CRP=1 nF
0.5
0.6
0.7
µs
RatioSR-LMT
Maximum Ratio of SR Gate On
(3)
Time
RatioSR-LMT < tON-SR[n+1]/ tON-SR[n]
tLPC-EXP-LMT
LPC Pulse Width Expansion Limit
tLPC-EXP-LMT < tLPC[n+1]- tLPC[n]
0.5
0.7
0.9
µs
tLPC-SRK-LMT
LPC Pulse Width Shrink Limit
tLPC-SRK-LMT < tLPC[n]- tLPC[n+1]
0.6
0.8
1.0
µs
120
%
Green Mode Section
tGREEN-OFF
SR Gate On Time to Exit Green
Mode
RRP=200 k, CRP=100 nF
5.5
5.9
6.3
RRP=75 k,CRP=1 nF
3.0
3.3
3.6
tGREEN-ON
SR Gate On time to Enter Green
Mode
RRP=200 k, CRP=100 nF
4.0
4.4
4.8
RRP=75 k,CRP=1 nF
1.6
1.9
2.2
tGREEN-
µs
µs
Hysteresis Voltage for tGREEN(3)
On/tGREEN-Off Threshold
RRP=200 k, CRP=100 nF
1.5
µs
Hysteresis Voltage for tGREEN(3)
On/tGREEN-Off Threshold
RRP=75 k,CRP=1 nF
1.4
µs
nGREEN-OFF
Number of Switching Cycles to
(3)
Exit Green Mode
SR Gate On Time > tGREEN-OFF
15
times
nGREEN-ON
Number of Switching Cycles to
(3)
Enter Green Mode
SR Gate On Time < tGREEN-ON
3
times
VRP-OPEN
Threshold Voltage for RP Pin Pull
High Protection
3.0
3.5
4.0
V
VRP-SHORT
Threshold Voltage for RP Pin Pull
Low Protection
0.30
0.35
0.40
V
tGREEN-ENTER
No Gate Signal to Enter Green
(3)
Mode
HYST(65kHz)
tGREENHYST(140kHz)
75
FAN6224 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
Electrical Characteristics (Continued)
s
Continued on the following page…
© 2013 Fairchild Semiconductor Corporation
FAN6224 • Rev. 1.4
www.fairchildsemi.com
7
VDD=15 V and TA=25℃, unless otherwise noted.
Symbol
Parameter
Condition
Min.
Typ.
Max. Unit
Operation Frequency Setting Section
VCRP-TH
Threshold Voltage for High / Low
(3)
Frequency Determination
tCRP-TH
Debounce Time for High / Low
(3)
Frequency Determination
IRP-SOURCE
RP Pin Source Current
Set VRP> VCRP-th for Higher
Operating Frequency
0.35
V
170
µs
8.5
9.5
10.5
µA
480
680
880
ns
350
500
650
ns
130
150
170
%
Casual Function Section
tDEAD-CAUSAL
fS=65 kHz,
(RRP=75 k~200 k,
SR Turn-Off Dead Time by Causal CRP=100 nF)
Function
fS=140 kHz,
(RRP=75 k~200 k,
CRP=1 nF)
tCAUSAL-FAULT
If tS-PWM(n+1) > tCAUSALx tS-PWM(n),
SR Stops Switching & Enters
Green Mode
tCAUSAL_LEAVE
(Assume SR Triggers Fault
Causal Protection) If LPC Rises
Twice during tCAUSAL_LEAVE and
Previous On-Time of VLPC-HIGH is
Longer than tLPC-EN, then SR
(3)
Leaves Fault Causal Protection
tDEAD-CFR
Once CFR is Triggered, SR
Terminates & Forces SR to Enter
Green Mode (The Last Time from
(3)
SR Gate Falling to LPC Rising)
fS=65 kHz to 140 kHz
Causal Function Regulator
(CFR)
5.3
µs
70
ns
Internal Over-Temperature Protection for OTP
TOTP
Internal Threshold Temperature
(3)
for OTP
140
°C
TOTP-HYST
Hysteresis Temperature for
(3)
Internal OTP
20
°C
Note:
3. Guaranteed by Design
© 2013 Fairchild Semiconductor Corporation
FAN6224 • Rev. 1.4
FAN6224 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
Electrical Characteristics
www.fairchildsemi.com
8
Figure 7. VDD-ON vs. Temperature
Figure 8. VDD-OFF vs. Temperature
Figure 9. tGREEN-OFF vs. Temperature
Figure 10. tGREEN-OFF vs. Temperature
Figure 11. IRP-SOURCE vs. Temperature
Figure 12. IDD-GREEN vs. Temperature
© 2013 Fairchild Semiconductor Corporation
FAN6224 • Rev. 1.4
FAN6224 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
Typical Performance Characteristics
www.fairchildsemi.com
9
Figure 13. tDEAD-CAUSAL vs. Temperature
Figure 14. tDEAD-CAUSAL vs. Temperature
Figure 15. VRES-EN vs. Temperature
Figure 16. RatioLPC-RES vs. Temperature
Figure 17. tLPC-EN vs. Temperature
Figure 18. tLPC-EN vs. Temperature
© 2013 Fairchild Semiconductor Corporation
FAN6224 • Rev. 1.4
FAN6224 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
Typical Performance Characteristics (Continued)
www.fairchildsemi.com
10
Figure 19. tMAX-PERIOD vs. Temperature
Figure 20. tMAX-PERIOD vs. Temperature
Figure 21. VLPC-SOURCE vs. Temperature
Figure 22. VRES-SOURCE vs. Temperature
Figure 23. tGREEN-ON vs. RRP
Figure 24. tGREEN-OFF vs. RRP
© 2013 Fairchild Semiconductor Corporation
FAN6224 • Rev. 1.4
FAN6224 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
Typical Performance Characteristics (Continued)
www.fairchildsemi.com
11
Body diode of
SR MOSFET
Body diode of
SR MOSFET
Body diode of
SR MOSFET
VGS
Body diode of
SR MOSFET
VGS
Primary
MOSFET
Synchr onous Rectifier
MOSFET
Primary
MOSFET
VDET
Synchr onous Rectifier
MOSFET
Primary
MOSFET
VDET
VIN/n
VIN/n
VIN/n+VOUT
VIN/n+VOUT
VOUT
VLPC
VLPC-HIGH
0.875VLPC-HIGH
VOUT
Blanking Time
(tLPC-EN)
VLPC
VLPC-HIGH
0.875VLPC-HIGH
VLPC-TH-HIGH
VLPC-TH-HIGH
VRES
VRES
VRES-EN
VRES-EN
IM,max
IM,max
IM
IM
IM,av
IDS
ISR /n
IDS
IM,min
IDS
ISR /n
IM,min
VCT
VCT
t PM.ON
t CT.DIS
t PM.ON
t L.DIS
t CT.DIS
t L.DIS
Figure 25. Waveforms of Linear-Predict Timing Control in CCM and DCM / QR Flyback
for Low-Side Application
© 2013 Fairchild Semiconductor Corporation
FAN6224 • Rev. 1.4
FAN6224 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
Functional Description
www.fairchildsemi.com
12
Body diode of
SR MOSFET
Body diode of
SR MOSFET
VGS
Body diode of
SR MOSFET
VGS
Primary
MOSFET
Synchr onous Rectifier
MOSFET
Primary
MOSFET
VDET
Synchr onous Rectifier
MOSFET
Primary
MOSFET
VDET
VIN/n
VIN/n
VIN/n+VOUT
VIN/n+VOUT
VOUT
VLPC-HIGH
VLPC-EN=
0.875VLPC-HIGH
VLPC-TH-HIGH
VLPC
VOUT
Blanking Time
(tLPC-EN)
VLPC-HIGH
VLPC-EN=
0.875VLPC-HIGH
VLPC-TH-HIGH
VLPC
VRES
VRES
tRES-SMP
tRES-SMP
VRES-EN
VRES-EN
IM,max
IM,max
IM
IM
IM,av
IDS
ISR /n
IDS
IM,min
IDS
ISR /n
IM,min
VCT
VCT
t PM.ON
t CT.DIS
t PM.ON
t L.DIS
t CT.DIS
t L.DIS
Figure 26. Waveforms of Linear-Predict Timing Control in CCM and DCM / QR Flyback for
High-Side Application
FAN6224 uses the LPC and RES pins with two sets of
voltage dividers to sense DET voltage (VDET) and output
voltage (VOUT), respectively; so VIN/n, tPM.ON, and VOUT
can be obtained. As a result, tL,DIS, which is the on-time
of SR MOSFET, can be predicted by Equation 1. As
shown in Figure 25, the SR MOSFET is turned on when
the SR MOSFET body diode starts conducting and DET
voltage drops to zero. The SR MOSFET is turned off by
linear-predict timing control.
Linear Predict Timing Control
The SR MOSFET turn-off timing is determined by
linear-predict timing control and the operation principle
is based on the volt-second balance theorem, which
states: the inductor average voltage is zero during a
switching period in steady state, so the charge voltage
and charge time product is equal to the discharge
voltage and discharge time product. In flyback
converters, the charge voltage on the magnetizing
inductor is input voltage (VIN), while the discharge
voltage is reflected output voltage (nVOUT), as the
typical waveforms show in Figure 25. The following
equation can be drawn:
VIN tPM.ON n VOUT tL.DIS
Circuit Realization
The linear-predict timing-control circuit generates a
replica (VCT) of the magnetizing current of the flyback
transformer using an internal timing capacitor (CT), as
shown in Figure 27. Using the internal capacitor voltage,
the inductor discharge time (tL.DIS) can be detected
indirectly, as shown in Figure 25. When CT is discharged
to zero, the SR controller turns off the SR MOSFET.
(1)
where tPM,ON is inductor charge time; tL,DIS is inductor
discharge time; and n is turn ratio of primary windings
(N1) to secondary windings (N2).
© 2013 Fairchild Semiconductor Corporation
FAN6224 • Rev. 1.4
FAN6224 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
Body diode of
SR MOSFET
www.fairchildsemi.com
13
VDET
Turn on SR Gate at
the falling edge
+
-
S
Turn off
VCT SR Gate
Q
In addition, considering the linear operating range, LPC
and RES voltage should be under 4.8 V, and therefore:
VOUT
SR Gate
R Q
R1
R3
LPC
iCHR
8
1µA/V
VCT
RES
iDISCHR
CT
7
R4
Figure 27. Simplified Linear-Predict Block
VIN tPM .ON
n VOUT
(2)
The voltage scale-down ratio between RES and LPC is
defined as K below:
R4 / R3 R4
R2 / R1 R2
3.9 VIN
(
VOUT ) VOUT ) tPM .ON VOUT tCT .DIS
K
n
(3)
3.9 VIN
(
VOUT ) VOUT ) tPM .ON
n
K
VOUT
(
(10)
3.9 VIN
(
VOUT ) VOUT ) tPM .ON
K
n' n
VOUT
(
tCT .DIS
(4)
(11)
Therefore, when the voltage scale-down ratio (K) and
turn ratio (n’) product is 3.9; the discharge time, tCT.DIS,
is the same as inductor current discharge time, t L.DIS. To
guarantee tCT.DIS is shorter than tL.DIS, the K and n’
product should be larger than 3.9. It is typical to set the
product around 4.0~4.5. When designing the voltage
divider of LPC, the consideration is the same as that of
low-side application, which means that the linear
operating range, Equations (6) and (8) must be
satisfied. However, when determining the voltage
divider of RES, note that turn ratio n’ must be taken into
consideration and so that Equation (7) and (9) are
modified as:
(5)
When the voltage scale-down ratio between LPC and
RES (K) is 3.9, the discharge time of CT (tCT.DIS) is the
same as inductor current discharge time (tL.DIS).
However, considering the tolerance of voltage divider
resistors and internal circuit, the scale-down ratio (K)
should be larger than 3.9 to guarantee that tCT.DIS is
shorter than tL.DIS. It is typical to set K around 4.0~4.5.
Referring to Figure 25, when LPC voltage is higher
than VLPC-EN over a period of blanking time (tLPC-EN)
and lower than VLPC-TH-HIGH (1.22 V), then SR
MOSFET can be triggered. Therefore, V LPC-EN must be
lager than VLPC-TH-HIGH or the SR MOSFET cannot be
turned on. As a result, when designing the voltage
divider of the LPC, considering the tolerance, R 1 and
R2 should satisfy the equation:
R2
V
( IN.MIN VOUT ) 1.54
R1 R 2
n
3.9 VIN
(
VOUT ) VOUT ) tPM .ON VOUT tCT .DIS
K n' n
where n’ is the turn ratio of auxiliary windings (N3) to
secondary windings (N2).
The discharge time of CT can be obtained as:
Therefore, the discharge time of CT is given as:
tCT .DIS
(9)
(
During tPM.ON, the charge current of CT is iCHR-iDICHR,
while during tL.DIS, the discharge current is iDICHR. As a
result, the current-second balance equation for internal
timing capacitor (CT) can be derived from:
(
R4
VOUT 4.8
R3 R4
For high-side applications, as shown in Figure 2, an
extra auxiliary winding (N3) is used to supply voltage for
controller. To detect output voltage, the RES pin is
connected to the auxiliary winding through a set of
voltage dividers. As Figure 26 shows, VRES is
proportional to VOUT when SR MOSFET or its body
diode conducts. Therefore, information of V OUT is
sampled at tRES-SMP after the primary-side MOSFET
turns off. As a result, Equation (4) can be rewritten as:
The voltage-second balance equation for the primaryside inductance of the flyback converter is given in
Equation (1). Inductor current discharge time is given as:
K
(8)
0.256µA/V
R2
tL.DIS
R2
V
( IN.MAX VOUT ) 4.8
R1 R2
n
(6)
R4
n 'VOUT 2
R3 R4
(12)
R4
n ' VOUT 4.8
R3 R4
(13)
FAN6224 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
VLPC
VLPC-TH
On the other hand, there is also a threshold voltage,
VRES-EN, for RES pin to enable SR switching, hence R3
and R4 must satisfy:
R3
VOUT 2
R3 R4
© 2013 Fairchild Semiconductor Corporation
FAN6224 • Rev. 1.4
(7)
www.fairchildsemi.com
14
The typical waveforms of CCM operation in steady state
are shown as right side of Figure 25 and Figure 26.
When the primary-side MOSFET is turned on, the
energy is stored in Lm. During the on-time of the
primary-side MOSFET (tPM.ON), the magnetizing current
(IM) increases linearly from IM,min to IM,max. Meanwhile,
internal timing capacitor (CT) is charged by current
source (iCHR-iDICHR) proportional to VIN, so VCT also
increases linearly.
When the primary-side MOSFET is turned off, the
energy stored in Lm is released to the output. During the
inductor discharge time (tL.DIS), the magnetizing current
(IM) decreases linearly from IM,max to IM,min. At the same
time, the internal timing capacitor (CT) is discharged by
current source (iDISCHR) proportional to VOUT, so VCT also
decreases linearly. To guarantee the proper operation
of SR, it is important to turn off the SR MOSFET just
before SR current reaches IM,min so that the body diode
of the SR MOSFET is naturally turned off.
SR Gate
Green Mode
Normal Mode
3 Times
1.9µs~4.4µs
1.9µs~4.4µs
t
1.9µs~4.4µs
IM
t
Figure 28. Entering Green Mode
DCM / QR Operation
In DCM / QR operation, when primary-side MOSFET is
turned off, the energy stored in Lm is fully released to
the output at the turn-off timing of primary-side
MOSFET. Therefore, the DET voltage continues
resonating until the primary-side MOSFET is turned on,
as depicted in Figure 25. While DET voltage is
resonating, DET voltage and LPC voltage drop to zero
by resonance, which can trigger the turn-on of the SR
MOSFET. To prevent fault triggering of the SR
MOSFET in DCM operation, a blanking time is
introduced to LPC voltage. The SR MOSFET is not
turned on even when LPC voltage drops below VLPC-THHIGH unless LPC voltage stays above 0.875 VLPC-HIGH
longer than the blanking time (tLPC-EN). The turn-on
timing of the SR MOFET is inhibited by gate inhibit time
(tINHIBIT), once the SR MOSFET turns off, to prevent
fault triggering.
SR Gate
Green Mode
Normal Mode
15 Times
3.3µs~5.9µs
3.3µs~5.9µs
3.3µs~5.9µs
t
IM
……
t
Figure 29. Resuming Normal Operation
tCT.DIS (s)
mWSaver™ Technology
Green-Mode Operation
To minimize the power consumption at light-load
condition, the SR circuit is disabled when the load
decreases. As illustrated in Figure 28, the discharge
times of the inductor and internal timing capacitor
decrease as load decreases. If the discharge time of
the internal timing capacitor (tCT.DIS) is shorter than
tGREEN-ON for more than three cycles, then the SR circuit
enters Green Mode. Once FAN6224 enters Green
Mode, the SR MOSFET stops switching and the major
internal block is shut down to further reduce the
operating current of the SR controller. In Green Mode,
the operating current reduces to 300 µA. This allows
power supplies to meet stringent power conservation
requirements. When the discharge time of the internal
capacitor is longer than tGREEN-OFF for more than fifteen
cycles, the SR circuit is enabled and resumes the
normal operation, as shown in Figure 29.
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
tGREEN-OFF
tGREEN-ON
50
70
90
110 130 150 170 190 210 230
RRP (kΩ)
Figure 30. Adjustable tGREEN-ON and tGREEN-OFF
FAN6224 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
RRP resistance corresponds to longer tGREEN-ON and
tGREEN-OFF, and vice versa. Therefore, by setting
different resistance of RRP, the loading of entering and
exiting Green Mode is adjustable.
CCM Operation
To enhance flexibility of design, tGREEN-ON and tGREEN-OFF
are adjustable by the external resistor of the RP pin
within a certain range. As shown in Figure 30, larger
© 2013 Fairchild Semiconductor Corporation
FAN6224 • Rev. 1.4
www.fairchildsemi.com
15
For different operating frequency range, internal
parameters of the SR controller should be different to
optimize signal processing. The capacitor of the RP pin
(CRP) is used to determine the operating frequency
range of the SR controller. For low switching frequency
systems ( 1.5xtS-PWM [n-1]
VLPC
LPC Width Expansion / Shrink Protection
LPC width expansion and shrink protection is utilized to
disable the SR MOSFET switching under some
abnormal conditions. As Figure 35 shows, once the
LPC pulse width (tLPC[n]) is longer than that of previous
cycle (tLPC[n-1]) for tLPC-EXP-LMT, the LPC width
expansion protection is triggered and SR MOSFET
switching is terminated immediately. Figure 36 shows
the timing diagram of LPC width shrink protection. Once
tLPC[n] is shorter than tLPC[n-1], the SR MOSFET
switching also shuts down immediately.
t
SR Gate
Disable
SR Gate &
enter Green
Mode
t
Figure 32. Fault Causal Timing Protection
Gate Expansion Limit Protection
FAN6224 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
time of the internal timing capacitor (tDIS.CT) is longer
than 120% of the previous on-time of the SR MOSFET
(ton-SR[n-1]); ton-SR[n] is limited to 120% of ton-SR[n-1], as
shown in Figure 33. When output load changes rapidly
from light load to heavy load, voltage-second balance
theorem may not be applied. In this transient state, gate
expand limit protection is activated to prevent overlap
between the SR Gate and the PWM gate.
Selection of Operating Frequency
Gate expansion limit protection controls the on-time
expansion of the SR MOSFET. Once the discharge
© 2013 Fairchild Semiconductor Corporation
FAN6224 • Rev. 1.4
www.fairchildsemi.com
16
tLPC[n]
LPC-Short Protection: If VLPC is pulled to ground and
the charging current of timing capacitor (CT) is near
zero, SR Gate is not output.
t
SR Gate off
RES Pin Open / Short Protection
SR Gate
t
RES-Open Protection: If VRES is pulled to HIGH level,
the gate signal is extremely small and FAN6224 enters
Green Mode. In addition, VRES is clamped at 6.2 V to
avoid RES pin damage.
Figure 35. VLPC Width Expand Protection
tLPC[n-1]
tLPC[n]
VLPC
RES-Short Protection: If VRES is lower than VRES-EN
(1.6 V), FAN6224 stops switching immediately and
enters Green Mode.
t
SR Gate off
SR Gate
Under-Voltage Lockout (UVLO)
The power ON and OFF VDD threshold voltages are
fixed at 10.5 V and 10.1 V, respectively. The FAN6224
can be used in various output voltage applications.
t
Figure 36. VLPC Width Shrink Protection
VDD Pin Over-Voltage Protection (OVP)
Over-voltage conditions are usually caused by an open
feedback loop. VDD over-voltage protection prevents
damage to the SR MOSFET. When the voltage on the
VDD pin exceeds 27.5 V; the SR controller stops
switching the SR MOSFET.
Over-Time Protection
Generally, the minimum operating frequency of PWM
controller in normal status is above 65 kHz
(65~140 kHz). In FAN6224, there are two over-time
protections that force the SR controller to go into green
mode. As shown in upper part of Figure 37, the first one
is when the time between LPC pulses (from LPC falling
edge to rising edge) is longer than 95 us. This is
typically triggered when the primary side controller
operates in burst mode operation. To minimize the
power consumption, FAN6224 enters into green mode
in this condition. This green mode is also triggered
when the LCP voltage divider is malfunctioning.
Over-Temperature Protection (OTP)
To prevent the SR Gate from fault triggering in high
temperatures, internal over-temperature protection is
integrated in FAN6224. If the temperature is over
140°C, the SR Gate is disabled until the temperature
drops below 120°C.
Another condition is when the time duration from SR
turn-off to SR turn-on is longer than 75us as shown in
lower part of Figure 37. This happens when the
PWM controller in the primary side goes into burst
mode operation at light load condition.
tLPC < 95uS
tLPC > 95uS
VLPC
VSR-GATE
t
VLPC
VSR-GATE
VCT
tSR-Gate < 75uS
tSR-Gate > 75uS
Disable SR Gate &
enter Green Mode
t
Figure 37. Over-Time Protection
FAN6224 — Synchronous Rectification Controller for Flyback and Forward Freewheeling Rectification
tLPC[n-1]
VLPC
LPC Pin Open / Short Protection
LPC-Open Protection: If VLPC is higher than VLPC-DIS
for longer than debounce time tLPC-HIGH, FAN6224 stops
switching immediately and enters Green Mode. VLPC is
clamped at 6.2 V to avoid LPC pin damage.
© 2013 Fairchild Semiconductor Corporation
FAN6224 • Rev. 1.4
www.fairchildsemi.com
17
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