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FAN6240
Secondary-Side Synchronous Rectifier Controller for
Flyback Converters
Features
Works in Discontinuous Conduction Mode (DCM).
Adaptive Turn-off Trigger Blanking Time for easier
use
Turn-on Trigger Blanking Time (Minimum-OFF
Time) for Improved Noise Immunity
Supports High-Frequency Applications up to
200 kHz
Minimum Turn-on Delay (20 ns)
Adaptive Turn-off Threshold Control for Minimized
SR MOSFET Body Diode Conduction (Dead-Time
is independent of SR MOSFET)
Wide Voltage Range for LDO Input up to 30 V
Small Footprint: SOT-23 6 Pin Package
Description
The FAN6240M6X is a secondary-side synchronous
rectifier (SR) controller for an isolated flyback converter
operating in Discontinuous Conduction Mode (DCM).
The adaptive dead-time control algorithm minimizes the
body diode conduction of SR MOSFET while
guaranteeing stable and robust SR operation against
noise and disturbance caused by the circuit parasitic.
30 V rated input voltage LDO and Low VDD UnderVoltage Lockout (UVLO) voltage allow FAN6240M6X to
be used for wide ranges of switched mode power supply
output voltage without additional circuit.
Applications
Battery Chargers for Smart Phones, Feature
Phones, and Tablet PCs
AC-DC Adapters for Portable Devices that Require
CV/CC Control
Ordering Information
Part Number
Operating
Temperature Range
Package
Packing
Method
FAN6240M6X
-40C to +125C
6-Lead, SOT23, JEDEC MO-178 Variation AB,
1.6 mm Wide
Tape & Reel
© 2016 Fairchild Semiconductor Corporation
FAN6240 • Rev. 1.0
www.fairchildsemi.com
FAN6240 — Secondary-Side Synchronous Rectifier Controller for Flyback Converters
July 2016
Vo (+)
TX1
L1
R3
C3
BR1
NP
C1
C2
C7
NS
LCM
R12
C6
R4
AC IN
R1
Q2
D1
R2
F1
Fuse
Q1
R5
R15
R16
R13
R17
R6
R14
1
U3
Photo
9
FB
8
IMIN
Gate
HV
4
R7
CS 3
U1
10 GNDFAN602VDD 5
C5
R11
FMAX
NC
7
2
VS
R18
R8
D2
R9
6
NA
11
GATE
22
GND
33
VDD
DRAIN
6
U2 SOURCE 5
FAN6240M6X
VIN
C8
R19
4
C9
C4
R10
CY
GATE
Figure 1.
Typical Application
Internal Block Diagram
VDD
VIN
SR_COND
Turn-on
Trigger
Blanking
+
LDO
-
VIN_ON / VIN_OFF
Adaptive Dead
Time Control
+
VTH_ARM
-
VTH_ON
DRAIN
TARM
Slope
Detection
D
SET
GATE
Q
210mV
Turn-on
+
CLR
Q
Turn-off
VTH_OFF
+
10mV
SOURCE
-
SR_COND
Turn-off
Trigger
Blanking
SR_COND
Minimum Turn
On Time
SKIP
GND
Figure 2.
© 2016 Fairchild Semiconductor Corporation
FAN6240 • Rev. 1.0
Function Block Diagram
www.fairchildsemi.com
2
FAN6240 — Secondary-Side Synchronous Rectifier Controller for Flyback Converters
Application Diagram
Axx:
TT:
ACD: FAN6240M6X
Wafer Lot Code
: Year Code
_ _ _:
Week Code
••••
---
_AXXTT
Figure 3.
Top Mark
Pin Configuration
GATE
DRAIN
GND
SOURCE
VDD
VIN
Figure 4.
Pin Configuration
Pin Definitions
Pin #
Name
Description
1
GATE
Gate drive output
2
GND
Ground
3
VDD
Internal regulator 5 V output and gate drive power supply rail. Bypass with 1uF capacitor to
GND.
4
VIN
LDO input, supports up to 30 V operation. An integrated 5 V LDO generates the internal VDD
power supply rail for the low-voltage control circuitry.
5
SOURCE
6
DRAIN
Synchronous rectifier source sense input.
Synchronous rectifier drain sense input.
© 2016 Fairchild Semiconductor Corporation
FAN6240 • Rev. 1.0
www.fairchildsemi.com
3
FAN6240 — Secondary-Side Synchronous Rectifier Controller for Flyback Converters
Marking Information
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
30
V
VIN
Power Supply Input Pin Voltage
-0.3
VDD
Internal Regulator Output Pin Voltage
-0.3
6.5
V
VDRAIN
Drain Sense Input Pin Voltage
-1
100
V
VGATE
Gate Drive Output Pin Voltage
-0.3
6.5
V
VSOURCE
1
V
PD
Power Dissipation (TA=25°C)
23
mW
ΘJA
Thermal Resistance (Junction-to-Ambient Thermal)
235
°C/W
TJ
TSTG
TL
ESD
Source Sense Input Pin Voltage
-1
Operating Junction Temperature
-40
150
°C
Storage Temperature Range
-60
150
°C
260
°C
Lead Temperature (Soldering) 10 Seconds
Electrostatic Discharge Capability
Human Body Model, ANSI / ESDA /
JEDEC JS-001-2012
2.5
Charged Device Model, JESD22-C101
1.5
kV
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values are with respect to the GND pin.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance. Fairchild does not recommend exceeding them or
designing to Absolute Maximum Ratings.
Symbol
Parameter
Min.
Typ.
Max.
Unit
VIN
Power Supply Input Pin Voltage
2.8
20
V
VDD
Internal Regulator Output Pin Voltage
2.8
6
V
VDRAIN
Drain Sense Input Pin Voltage
-0.3
100
V
VGATE
Gate Drive Output Pin Voltage
-0.3
6
V
Source Sense Input Pin Voltage
-0.3
1
V
VSOURCE
© 2016 Fairchild Semiconductor Corporation
FAN6240 • Rev. 1.0
www.fairchildsemi.com
4
FAN6240 — Secondary-Side Synchronous Rectifier Controller for Flyback Converters
Absolute Maximum Ratings
VIN = 12 V and TJ = -40°C to 125°C unless otherwise specified.
Symbol
Parameter
Conditions
Min. Typ. Max. Unit
Input Voltage
VIN_ON
Turn-On Threshold
VIN Rising
3.1
3.4
3.7
V
VIN_OFF
Turn-Off Threshold
VIN Falling
2.8
2.9
3.0
V
Operating Current
fSW = 100 kHz, CGATE = 3.3 nF,
VIN = 5 V
2
3.5
mA
5.00
5.25
5.50
V
Maximum of adaptive offset current
(15 steps, 6 µA resolution)
75
90
105
µA
RDRAIN = 0 Ω (includes comparator
input offset voltage)
-235
-210
-185
mV
IIN_OP
Power Supply Section
VDD
Internal LDO Output Voltage
VIN = 20 V
Drain Voltage Sensing Section
IOFFSET
VTH_ON
Turn-On Threshold
(3)
Turn-On Delay
20
ns
(3)
Turn-Off Threshold
10
mV
Turn-Off Delay
20
ns
TON.DLY
VTH_OFF
(3)
TOFF.DLY
VTH_ARM
(3)
TARM
(3)
VTH_HGH
Gate Re-arming Threshold
VIN = 5 V, (Typically 0.7*VDD)
3.3
3.5
3.7
V
Gate Re-arming Time for Slope
Detection
85
ns
SR OFF Detection Threshold
0.5
V
50
%
Minimum On-Time and Minimum Off-Time
KTON
Ratio between minimum on time
Adaptive Minimum On-Time Ratio and SR conduction of previous
switching cycle
(3)
tON_MIN.LL
tON_MIN.UL
(3)
tOFF_MIN
Minimum On-Time Lower Limit
300
Minimum On-Time Upper Limit
Minimum Off-Time
400
500
2
Default Option for Medium
Frequency
1.0
1.2
ns
µs
1.4
µs
0.25
V
Output Driver Section
VOL
Output Voltage Low
VIN = 6 V
VOH
Output Voltage High
VIN = 6 V
tR
Rise Time
VIN = 6 V, CL=3300 pF,
GATE = 1 V~4 V
10
ns
tF
Fall Time
VIN=6 V, CL = 3300 pF,
GATE = 4 V~1 V
10
ns
5.0
V
Adaptive Dead-Time Control
(3)
tDEAD
Dead-Time Self-Tuning Target
From GATE OFF to VDRAIN rising
above VTH_HGH
290
ns
Note:
3. Not tested and guaranteed by design.
© 2016 Fairchild Semiconductor Corporation
FAN6240 • Rev. 1.0
www.fairchildsemi.com
5
FAN6240 — Secondary-Side Synchronous Rectifier Controller for Flyback Converters
Electrical Characteristics
Theory of SR Control Operation
For an ideal circuit operation, the SR control algorithm
of FAN6240 is very straightforward. FAN6240 controls
the SR MOSFET based on the instantaneous drain-tosource voltage as illustrated in Figure 5. When the body
diode starts conducting, the drain-to-source voltage
drops below the turn-on threshold (VTH_ON) which
triggers the turn-on of the gate. Then the drain-to-source
voltage is determined by the product of RDSON and
instantaneous SR current. When the drain-to-source
voltage reaches the turn-off threshold (VTH_OFF) as SR
MOSFET current decreases to near zero, FAN6240
turns off the gate. If the turn off threshold (VTH_OFF) is
very close to zero, the turn off dead time can be
minimized.
GND
VDS.SR
VTH_OFF
VTH_ON
TON.DLY
VGS.SR
TDEAD
ISD.SR
Figure 5.
SR MOSFET Operation Waveforms
(Ideal Case)
SR Turn-On Algorithm
As the diagram shown in Figure 6, the turn-on of SR GATE is triggered by the three input signals of AND gate. The
first input signal is TURN_ON_ALLOW signal, which is given after tOFF_MIN from the falling edge of VGS.SR signal. The
second input is the TURN_ON_TRG signal, which is enabled after DRAIN pin voltage drops below VTH_ON. The third
signal is TARM which allows turn-on trigger only when SR drain voltage drops fast with a large slope, preventing SR
from triggering by the drain resonance voltage in DCM operation.
VTH_ARM
GND
VTH_OFF
VDS.SR
VTH_ON
ARM
TARM
TARM
tOFF_MNI
TURN_ON_ALLOW
ARMTARM
TURN_ON_ALLOW
TURN_ON_TRG
TURN_ON_TRG
VGS.SR
VGS.SR
IDS.SR
IDS.SR
Figure 6.
© 2016 Fairchild Semiconductor Corporation
FAN6240 • Rev. 1.0
TARM
SR Turn-On Algorithm
www.fairchildsemi.com
6
FAN6240 — Secondary-Side Synchronous Rectifier Controller for Flyback Converters
Functional Description
As diagram shown in Figure 7, the turn-off of SR GATE is triggered by the two input signals of AND gate. The first
input signal is turn off signal, which is enabled when VDS.SR>VTH_OFF .The second input is TURN_OFF_ALLOW signal
given from the adaptive turn-off blanking. The blanking time is adaptively determined as half of SR conduction time
(SR_COND) of the previous switching cycle for better noise immunity.
GND
VTH_OFF
VDS.SR
VTH_ON
VDS.SR
Turn off
Turn off
Turn off
Turn off
Turn off
KTON*SR_COND
TURN_OFF_ALLOW
TURN_OFF_ALLOW
SR_COND
VGS.SR
VGS.SR
ISD.SR
ISD.SR
Figure 7.
SR Turn-Off Algorithm
SR Skipping Mode Algorithm
As diagram shown in Figure 8, FAN6240 disables SR gate signal (SR skipping) at next cycle when previous cycle SR
conduction time VGS.SR signal is smaller than the minimum ON time tON_MIN.LL in order reduce power consumption. This
operation occurs only when the burst mode entry level of the primary side PWM controller is extremely low.
GND
VTH_OFF
VDS.SR
SR condition
time
VGS.SR
VGS.SR
ISD.SR
ISD.SR
Figure 8.
© 2016 Fairchild Semiconductor Corporation
FAN6240 • Rev. 1.0
VGS.SR
ISD.SR
SR Skipping Diagram
www.fairchildsemi.com
7
FAN6240 — Secondary-Side Synchronous Rectifier Controller for Flyback Converters
SR Turn-Off Algorithm
REVISIONS
LTR
A
C
2
D
0.15 C A-B
DESCRIPTION
E.C.N.
RELEASE TO DOCUMENT CONTROL
2X
DATE
11/4/2006
5 JULY 07
DWG UPDATED TO CONFORM TO MO178
BY/APP'D
H.ALLEN
L.HUEBENER
SYMM
C
L
2.9
(0.95)
1.9
(0.95)
D
A
(1.00MIN)
1.4
C
D
1.6
2.8
(2.60)
(0.70MIN)
0.15 C D
2X
0.15 C
PIN 1 INDEX AREA
2X 3 TIPS
0.95
B
(1.90)
2X 0.3-0.5
0.20
C A-B D
LAND PATTERN RECOMMENDATION
SEE DETAIL A
1.45 MAX
1.30
0.90
0.08
0.22
C
0.15
0.05
6X
0.10
C
R0.10MIN
GAGE PLANE
R0.10MIN
0.25
8°
0°
0.60
0.30
SEATING PLANE
0.60 REF
DETAIL A
NOTES:
A. THIS PACKAGE CONFORMS TO JEDEC MO-178,
VARIATION AB.
B. ALL DIMENSIONS ARE IN MILLIMETERS.
C. DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS
OR GATE BURRS.
D. DOES NOT INCLUDE INTERLEAD FLASH OR
PROTRUSIONS.
E. DIMENSIONS AND TOLERANCING AS PER ASME
Y14.5M-1994
F. DRAWING FILE NAME: MA06EREV2
SCALE: 2:1
APPROVALS
DATE
L.HUEBENER
5 JULY 07
H.ALLEN
17 JULY 07
6LD,SOT23,JEDEC
MO-178 VARIATION AB,
1.6MM WIDE
1:1
FORMERLY:
/
NA
N/A
MKT-MA06E
SHEET :
2
1
OF 1
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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