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to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON
Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON
Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA
Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended
or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out
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is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
FAN6248
Advanced Synchronous Rectifier
Controller for LLC Resonant Converter
The FAN6248 is an advanced synchronous rectifier (SR) controller that is
optimized for LLC resonant converter topology with minimum external
components. It has two driver stages for driving the SR MOSFETs which
are rectifying the outputs of the secondary transformer windings. The two
gate driver stages have their own sensing inputs and operate
independently of each other. The adaptive parasitic inductance
compensation function minimizes the body diode conduction maximizing
the efficiency. The advanced control algorithm allows stable SR
operation over entire load range. FAN6248 has two different versions FAN6248HAMX having higher turn-off threshold voltage and
FAN6248HBMX having lower turn-off threshold voltage.
www.onsemi.com
PACKAGE PICTURE
SOIC-8 NB
CASE 751
.
Features
Highly integrated self-contained control of synchronous rectifier with
a minimum external component count
Optimized for LLC resonant converter
Adaptive parasitic inductance compensation to minimize the body
diode conduction
SR current inversion detection under light load condition
Low operating current in green mode (typ. 350uA)
Anti shoot-through control for reliable SR operation
Separate 100V rated sense inputs for sensing the drain and source
voltage of each SR MOSFET
U
V
Z
X
Y
TT
= Frequency, H:High
= Vth_off level, A or B
= Assembly Plant Code
= Year Code
= Two Week Code
= Die Run Code
Light load detection
PIN CONNECTIONS
Adaptive minimum on time for noise immunity
Operating voltage range up to 30 V
GATE1 1
Low start-up and stand-by current consumption
Operating frequency range from 25kHz up to 700 kHz
GND
2
SOIC−8 Package
VD1
3
High driver output voltage of 10.5 V to drive all MOSFET brands to
the lowest RDS_ON
VS1
4
8 GATE2
TBD
Top Mark
7 VDD
6
VD2
5
VS2
(Top View)
Applications
High power density laptop adapter
MARKING DIAGRAM
ORDERING INFORMATION
See detailed ordering and shipping information on page 3 of
this data sheet.
High Power Density Adapter
Large Screen LCD-TV, PDP-TV, RP-TV Power
High-Efficiency Desktop and Server Power Supplies
Networking and Telecom Power Supplies
High Power LED Lighting
© Semiconductor Components Industries, LLC, 2017
April 2017- Rev.1.0
1
Publication Order Number:
FAN6248
FAN6248
M2
Optional
Roffset2
Q1
Lr
Lp
Roffset1
VS1
Q2
VS2
VO
VD1 VD2
Cr
G2
Cin
GND VDD
PFC
Stage
G1
Bridge
Diode
FAN6248
VAC
EMI
Filter
RO
CO
Optional
M1
LLC
Controller
Shunt
Regulator
Figure 1. Typical Application Schematic of FAN6248
VDD
4.5/4.2V
VDS1.HGH
GREEN
VDS2.HGH
IOFFSET1
VTH_HGH
VD1
VTH_ON
VS1
DLY.ENA
Adaptive
turn-on
debounce
DLY.ENA
D
SET
Turn-on
CLR
Q
Q
Q
Q
Turn-off
VTH_OFF
SET
D
Turn-on
CLR
Adaptive
turn-on
debounce
Turn-off
Turn-off
Trigger
Blanking
IOFFSET2
VTH_HGH
VD2
VTH_ON
VTH_OFF
VS2
Turn-off
Trigger
Blanking
GATE2
GATE1
GATE1
GATE2
VDS1.HGH
VDS1.HGH
Green Mode
GREEN
SR Current
Inversion detect
VDS2.HGH
IOFFSET1
Light Load
Detection
GND
Figure 2. Internal Block Diagram of FAN6248
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2
DLY.ENA
FAN6248
Pin Decription
Pin Number
Name
Description
1
GATE1
Gate drive output for SR1
2
GND
Ground
3
VD1
Synchronous rectifier drain sense input. A IOFFSET1 current source flows out of the
DRAIN pin such that an external series resistor can be used to adjust the
synchronous rectifier turn-off threshold. The IOFFSET1 current source is turned off
when VDD is under-voltage or when switching is disabled in green mode
4
VS1
Synchronous rectifier source sense input for SR1
5
VS2
Synchronous rectifier source sense input for SR2
6
VD2
Synchronous rectifier drain sense input. A IOFFSET2 current source flows out of the
DRAIN pin such that an external series resistor can be used to adjust the
synchronous rectifier turn-off threshold. The IOFFSET2 current source is turned off
when VDD is under-voltage or when switching is disabled in green mode
7
VDD
Supply Voltage
8
GATE2
Gate drive output for SR2
Ordering and Shipping Information
Ordering Code
Device Marking
VTH_OFF1 / VTH_OFF2
Package
Shipping
FAN6248HAMX
FAN6248HA
130mV / 228mV
SOIC-8
2500 / Tape & Reel
FAN6248HBMX
FAN6248HB
100mV / 175mV
SOIC-8
2500 / Tape & Reel
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3
FAN6248
MAXIMUM RATINGS
Stresses exceeding the absolute maximum ratings may damage the device. If any of these limits are exceeded, device
functionality should not be assumed. In addition, extended exposure to stresses above the recommended operating
conditions may affect device reliability.
Symbol
VDD
Parameter
Min.
Power Supply Input Pin Voltage
Max.
Unit
-0.3
30
V
VD1, VD2
Drain Sense Input Pin Voltage
-1
100
V
VGATE1,
VGATE2
Gate Drive Output Pin Voltage
-0.3
30
V
VS1, VS2
Source Sense Input Pin Voltage
-0.4
0.4
V
0.625
W
165
°C/W
PD
Power Dissipation (TA=25°C)
ΘJA
Thermal Resistance (Junction-to-Ambient Thermal)
TJ
TSTG
TL
Operating Junction Temperature
-40
150
°C
Storage Temperature Range
-60
150
°C
260
°C
Lead Temperature (Soldering) 10 Seconds
ESD
Human Body Model, ANSI / ESDA /
JEDEC JS-001-2012
Electrostatic Discharge Capability
4
Charged Device Model, JESD22-C101
kV
1.75
Notes:
1. All voltage values are with respect to the GND pin.
THERMAL CHARACTERISTICS
Rating
Symbol
Value
Unit
Thermal Characteristics
RψJT
22
°C/W
Thermal Characteristics
RθJA
165
°C/W
Recommended Operating Conditions
The Recommended Operating Conditions table defines the continuous conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the data sheet specifications. ON Semiconductor does
not recommend exceeding them or designing to Absolute Maximum Ratings
Symbol
VDD2
Parameter
VDD Pin Supply Voltage to GND
Min.
Max.
Unit
0
27
V
VD1 ,VD2
Drain Sense Input Pin Voltage
-0.7
100
V
VS1 VS2
Source Sense Input Pin Voltage
-0.4
0.4
V
TA3
Operating Ambient Temperature
-40
+125
ºC
Notes:
2. Allowable operating supply voltage VDD can be limited by the power dissipation of FAN6248 related to switching
frequency, load capacitance and ambient temperature.
3. Allowable operating ambient temperature can be limited by the power dissipation of FAN6248 related to switching
frequency, load capacitance on GATE pin and VDD.
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4
FAN6248
Electrical Characteristics
VDD = 12V and TJ = -40°C to 125°C unless otherwise specified
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input Voltage
VDD_ON
Turn-On Threshold
VDD rising
4.3
4.5
4.7
V
VDD_OFF
Turn-Off Threshold
VDD falling
4.0
4.2
4.4
V
IDD_OP
Operating Current
fSW = 100kHz, CGATE = 3.3nF
7
8.5
10
mA
200
A
350
500
A
-1
0
1
mV
IDD_SRARTUP
IDD_GREEN
VDD = VDD_ON - 0.1V
Operating Current in Green Mode
VDD = 12V (no switching)
Drain Voltage Sensing Section
VOSI(1)
Comparator Input Offset Voltage
IOFFSET
IOFFSET1 and IOFFSET2
Maximum of adaptive offset current
(15 steps, 9uA resolution)
IOFFSET=IOFFSET_STEP15
112.5
135
157.5
A
VTH_ON
Turn-On Threshold
RDRAIN = 0Ω (includes comparator
input offset voltage)
-290
-240
-190
mV
tON_DLY(1)
Turn on delay for de-bounce time
when turn-on delay mode is disabled
by detecting normal SR current
From VDS falling below VTH_ON to
VGATE rising above VG_HG (With 50mV
overdrive), CGATE=0nF
80
ns
tON_DLY2_H(1)
Turn on delay for de-bounce time
when turn-on delay mode is enabled
by detecting SR current inversion for
HA and HB version
From VDS falling below VTH_ON to
VGATE rising above VG_HG (With 50mV
overdrive), CGATE=0nF
380
ns
VTH_OFF1_A(1)
First level Turn-Off Threshold for LA
and HA version
RDRAIN = 0Ω (includes comparator
input offset voltage)
130
mV
VTH_OFF2_HA(1)
Second level Turn-Off Threshold for
HA version
RDRAIN = 0Ω (includes comparator
input offset voltage)
228
mV
VTH_OFF1_B(1)
First level Turn-Off Threshold for LB
and HB version
RDRAIN = 0Ω (includes comparator
input offset voltage)
100
mV
VTH_OFF2_HB(1)
Second level Turn-Off Threshold for
HB version
RDRAIN = 0Ω (includes comparator
input offset voltage)
175
mV
Comparator delay for VTH_OFF1
From VDS rising above VTH_OFF to
VGATE falling below VG_LW (With 10mV
overdrive), CGATE=0nF
80
ns
Drain voltage high detect threshold
VDS Rising
tOFF_DLY(1)
VTH_HGH
tDB_HGH_H(1)
0.65
VTH_HGH detection blanking time for HA
From VDS falling below VTH_ON
and HB version
0.8
0.95
V
400
ns
50
%
200
ns
Minimum On-Time and Maximum On-Time
KTON(1)
Ratio between tON_MIN and SR
conduction time of previous switching
cycle
Adaptive minimum on time ratio
tON_MIN_LH(1)
Minimum On-Time Lower Limit for HA
and HB version
tON_MIN_UH
Minimum On-Time Upper Limit for HA
and HB version
tSR_CNDT_H
Minimum SR conduction time to
enable SR for HA and HB version
The duration from turn-on trigger to
VDS rising above VTH_HGH
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5
0.96
1.2
1.44
s
380
600
820
ns
FAN6248
Symbol
Parameter
Conditions
Min
Maximum SR turn-on time for HA and
HB version
Typ
Max
Unit
15
s
Dead time regulation target for HA and From VGATE falling below VG_LW to
HB version
VDS rising above VTH_HGH
200
ns
tDEAD_H_ LIGHT(1)
Dead time regulation target under light
load condition for HA and HB version
From VGATE falling below VG_LW to
VDS rising above VTH_HGH
250
ns
tTSDT(1)
Too small dead time threshold to
speed up IOFFSET change (Speed up 2
times)
From VGATE falling below VG_LW to
VDS rising above VTH_HGH
35
ns
KINV(1)
Adaptive SR current inversion
detection time Ratio between TINV and
SR conduction time of previous
switching cycle
VGATE > VG_HG and VDS >VTH_OFF
12.5
%
tSR_MAX_H(1)
Regulated Dead Time
tDEAD_H(1)
Green Mode Control
tGRN_ENT_H
Non-Switching Period to Enter Green
Mode for HA and HB version
Non switching cycles between burst
switching bundles
60
80
100
µs
tGRN_ENT_DBNC_H
De-bounce time to Enter Green Mode
for HA and HB version
De-bounce time after tGRN.ENT_H
130
180
230
µs
tGRN_EXT_H
Non-Switching Period to Exit Green for Non switching cycles between burst
HA and HB version
switching bundles
30
40
50
µs
ηCSW_EXT
Continuous switching cycles to exit
Green Mode
7
11
15
cycle
Switching period to be recognized as
normal switching for HA and HB
version
13
20
27
µs
9
10.5
12
V
1.5
V
tS_NORMAL_H
Output Driver Section
VGATE_MAX
Gate clamping voltage
12VtDEAD_H)
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11
FAN6248
VDS_SR
ISD_SR
Turn-off trigger is prohibited
during TON_MIN
VTH_HGH
VTH_OFF
VDrain
VTH_ON
Virtual VTH_OFF
TON_MIN=50% of TSRCOND of
previous cycle
VTH_ON
SR conduction time = TSRCOND
VGS.SR
tON_DLY
TDEAD≈200ns
VGS.SR
TDEAD
IDS_SR
Figure 20. Dead time control to maintain TDEAD≈200ns
ISD.SR
Minimum Turn-on Time
When SR gate is turned on, there may exist severe
Figure 21. Minimum turn-on time
oscillation in drain-to-source voltage of SR MOSFET, which
results in several mis-triggering turn-off as shown in Figure
IDS_SR
Capacitive current spike
Capacitive current spike
21. To provide stable SR control without mis-trigger, it is
desirable to have large turn-off blanking time (=minimum
turn-on time) until the drain voltage oscillation attenuates.
However, too large blanking time results in problems at light
t
VDS_SR
load condition where the SR conduction time is shorter than
the minimum turn-on time. To solve this issue, FAN6248
has adaptive minimum turn-on time where the turn-off
V
blanking time changes in accordance with the SR conduction
VGATE
time TSRCOND measured in previous switching cycle. The SR
VGATE_SR1
VGATE_SR1
conduction time is measured by the time from SR gate rising
Figure 22. Capacitive current spike at light load condition
edge to the instant when drain sensing voltage VDS_SR is
higher than VTH_HGH. From the previous cycle TSRCOND
measurement result, the minimum turn-on time is defined by tON_DLY to tON_DLY2 in next cycle. As a result, SR mis-trigger
is prevented. To exit the SR current inversion detection
50% of TSRCOND.
mode, seven consecutive switching cycles without
capacitive current spike are required.
Capacitive Current Spike Detection
At heavy load condition, the body diode of SR MOSFET
in LLC resonant converter starts conducting right after the Light Load Detection (LLD)
To guarantee stable operation under light load condition,
primary side switching transition takes place. However,
when the resonance capacitor voltage amplitude is not large FAN6248 adopts a light load detection function. The
enough at light load condition, the voltage across the modulation current IOFFSET is mainly used for the adaptive
magnetizing inductance of the transformer is smaller than dead time control. When the output load is heavy,
the reflected output voltage. Thus, the secondary side SR IOFFSET_STEP decilines due to large di/dt in the secondary side
body diode conduction is delayed until the magnetizing current to maintain 200ns of tDEAD. On the contrary,
inductor voltage builds up to the reflected output voltage. IOFFSET_STEP increases at light load condition by small di/dt of
However, the primary side switching transition can cause SR current. FAN6248 can detect light load condition by
capacitive current spike and turn on the body diode of SR using this IOFFSET_STEP as shown in Figure 23. When SR turnMOSFET for a short time as shown in Figure 22, which off threshold voltage is VTH_OFF1 and the modulation current
induces SR mis-trigger signal. Finally, the SR mis-trigger becomes IOFFEST_STEP8, the light load detection is triggerd. In
makes inversion current in the secondary side. If a proper this mode, the turn-on delay is changed to tON_DLY2 to prevent
algorithm is not to prevent the mis-trigger by the capacitive the SR inversion current, and dead time target becomes to
250ns of tDEAD_LIGHT in FAN6248HA and HB version.
current spike, severe SR current inversion can happen.
To prevent the SR mis-trigger, FAN6248 has a capacitive
current spike detection method. When SR current inversion
occurs by the mis-tirgger signal, the drain sensing voltage of
SR MOSFET becomes positive. In this condition, if VDS_SR is
higher than VTH_OFF for (TSRCOND*KINV), SR current inversion
is detected. Then, FAN6248 increases turn-on delay from
ON_DLY2
TH_ON
Green Mode
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12
FAN6248
When the power supply system operates at very light load
condition, FAN6248 disables SR operation and enters into
green mode operation. Once FAN6248 is in the green mode,
all the major blocks are disabled to minimize the operating
current. When VDS_SR has no switching operation long than
tGRN_ENT during the burst mode of the primary side LLC
controller, the green mode is enabled after tGRN_ENT_DBNC of
debounce time. After then, FAN6248 exits the green mode
when the non-switching time in the burst mode is less than
tGRN_EXT_H or 11 consecutive switching cycles are detected as
shown in Figure 24.
Virtual VTH_OFF
Heavy Load
VTH_OFF2
VTH_OFF2-ROFFSET x IOFFSET_STEP1
VTH_OFF2-ROFFSET x IOFFSET_STEP2
VTH_OFF2
Range
VTH_OFF2-ROFFSET x IOFFSET_STEP13
VTH_OFF1
VTH_OFF2-ROFFSET x IOFFSET_STEP15
VTH_OFF1-ROFFSET x IOFFSET_STEP2
VTH_OFF1
Range
VTH_OFF1-ROFFSET x IOFFSET_STEP8
LLD Trigger
Light Load
VTH_OFF1-ROFFSET x IOFFSET_STEP14
VTH_OFF1-ROFFSET x IOFFSET_STEP15
Figure 23. Light load detection
VGATE1
Green Exit
ηCSW_EXT=11 cycles
VDS_SR1
IDS_SR1
Figure 24. Green mode exit
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13
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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