FAN6300AMY

Highly Integrated Quasi-Resonant Current Mode PWM Controller FAN6300A / FAN6300H The highly integrated FAN6300A/H of PWM controller provides several features to enhance the performance of flyback converters. FAN6300A is applied on quasiresonant flyback converters where maximum operating frequency is below 100 kHz. FAN6300H is suitable for high−frequency operation (up to 190 kHz). A built−in HV startup circuit can provide more startup current to reduce the startup time of the controller. Once the VDD voltage exceeds the turn−on threshold voltage, the HV startup function is disabled immediately to reduce power consumption. An internal valley voltage detector ensures power system operates at quasi−resonant operation over a wide−range of line voltage and any load conditions, as well as reducing switching loss to minimize switching voltage on drain of power MOSFET. To minimize standby power consumption and light−load efficiency, a proprietary green−mode function provides off−time modulation to decrease switching frequency and perform extended valley voltage switching to keep to a minimum switching voltage. The operating frequency is limited by minimum tOFF time, which is 38 ms to 8 ms in FAN6300A and 13 ms to 3 ms in FAN6300H, so FAN6300H can operate at higher switching frequency than FAN6300A. FAN6300A/H controller also provides many protection functions. Pulse−by−pulse current limiting ensures the fixed−peak current limit level, even when a short circuit occurs. Once an open−circuit failure occurs in the feedback loop, the internal protection circuit disables PWM output immediately. As long as VDD drops below the turn−off threshold voltage, the controller also disables PWM output. The gate output is clamped at 18 V to protect the power MOS from high gate−source voltage conditions. The minimum tOFF time limit prevents the system frequency from being too high. If the DET pin triggers OVP, internal OTP is triggered and the power system enters latch−mode until AC power is removed. The FAN6300A/H controller is available in the 8−pin SOIC8 package. High−Voltage Startup Quasi−Resonant Operation Cycle−by−Cycle Current Limiting Peak−Current−Mode Control Leading−Edge Blanking (LEB) Internal Minimum tOFF Internal 5 ms Soft−Start Over Power Compensation GATE Output Maximum Voltage Auto−Recovery Over−Current Protection (FB Pin) Auto−Recovery Open−Loop Protection (FB Pin) © Semiconductor Components Industries, LLC, 2021 June, 2021 − Rev. 1 SOIC8 CASE 751EB MARKING DIAGRAM 6300x = Specific Device Code (x = A or H) A = Assembly Location L = Wafer Lot Traceability YW = Date Code X = Manufacture Flow • = Pb Free 6300x ALYWX • PIN ASSIGNMENT DET 1 FB 2 8 HV 7 NC FAN6300H CS 3 6 VDD GND 4 5 GATE (Top View) ORDERING INFORMATION See detailed ordering and shipping information on page 11 of this data sheet. Features • • • • • • • • • • • www.onsemi.com • VDD Pin and Output Voltage (DET Pin) OVP Latched • Low Frequency Operation (below 100 kHz) • for FAN6300A High Frequency Operation (up to 190 kHz) for FAN6300H Applications • AC/DC NB Adapters • Open−Frame SMPS 1 Publication Order Number: FAN6300H/D FAN6300A / FAN6300H APPLICATION DIAGRAM Figure 1. Typical Application INTERNAL BLOCK DIAGRAM HV VDD 8 6 Internal Bias OVP IH V 4 .2V FB 2 27 V 2R Soft-Start 5 ms Timer 52 ms R Latched Two Steps UVLO 16 V/ 10 V/ 8 V FBOLP 2 .1 ms 30 μs Starter CS 3 DRV Blanking Circuit S Over-Power Compensation PWM Current Limit R ID ET 0.3 V V D ET t OFF Blanking S/H Valley Detector tTIME-OUT V D ET Latched 2. 5V DETOVP DET 1 Internal OTP 0 .3 V 5V 5 Q 18 V Latched t OFF-MIN SE T I D ET Latched 4 7 GND NC Figure 2. Functional Block Diagram www.onsemi.com 2 CLR Q GATE FAN6300A / FAN6300H PIN CONFIGURATION Figure 3. Pin Configuration PIN DEFINITIONS Pin # Pin Name Description 1 DET This pin is connected to an auxiliary winding of the transformer via resistors of the divider for the following purposes: − Generates a ZCD signal once the secondary−side switching current falls to zero. − Produces an offset voltage to compensate the threshold voltage of the peak current limit to provide a constant power limit. The offset is generated in accordance with the input voltage when PWM signal is enabled. − Detects the valley voltage of the switching waveform to achieve the valley voltage switching and minimize the switching losses. A voltage comparator and a 2.5 V reference voltage develop a output OVP protection. The ratio of the divider decides what output voltage to stop gate, as an optical coupler and secondary shunt regulator are used. 2 FB The feedback pin should to be connected to the output of the error amplifier for achieving the voltage control loop. The FB should be connected to the output of the optical coupler if the error−amplifier is equipped at the secondary− side of the power converter. The input impedance of this pin is a 5 kW equivalent resistance. A 1/3 attenuator connected between the FB and the PWM circuit is used for the loop−gain attenuation. FAN6300A/H performs an open−loop protection once the FB voltage is higher than a threshold voltage (around 4.2 V) more than 55 ms. 3 CS Input to the comparator of the over−current protection. A resistor senses the switching current and the resulting voltage is applied to this pin for the cycle−by−cycle current limit. 4 GND The power ground and signal ground. A 0.1 mF decoupling capacitor placed between VDD and GND is recommended. 5 GATE Totem−pole output generates the PWM signal to drive the external power MOSFET. The clamped gate output voltage is 18 V. 6 VDD Power Supply. The threshold voltages for startup and turn−off are 16 V and 10 V, respectively. The startup current is less than 20 mA and the operating current is lower than 4.5 mA. 7 NC No connect 8 HV High−voltage startup www.onsemi.com 3 FAN6300A / FAN6300H ABSOLUTE MAXIMUM RATINGS Symbol Max. Unit VDD DC Supply Voltage 30 V VHV Maximum Voltage on HV Pin 500 V VH Maximum Voltage on GATE Pin −0.3 25.0 V VL VFB, VCS, VDET (Maximum Voltage on Low Power Pins) −0.3 7.0 V PD Power Dissipation 400 mW 150 °C 150 °C Lead Temperature (Soldering 10 seconds) 270 °C Human Body Model, JEDEC:JESD22−A114 3.0 kV Charged Device Model, JEDEC:JESD22−C101 1.5 TJ TSTG TL ESD Parameter Min. Operating Junction Temperature Storage Temperature Range −55 Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to GND pin. RECOMMENDED OPERATING CONDITIONS Symbol TA Parameter Operating Ambient Temperature Min Max Unit −40 105 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 4 FAN6300A / FAN6300H ELECTRICAL CHARACTERISTICS (Unless otherwise specified, VDD = 10 ~ 25 V, TA = −40 ~ +105°C (TJ = TA)) Symbol Parameter Conditions Min Typ Max Unit 25 V VDD SECTION VOP VDD−ON Continuously Operating Voltage Turn−On Threshold Voltage 15 16 17 V VDD−PWM−OFF PWM Off Threshold Voltage 9 10 11 V V VDD−OFF 8 9 IDD−ST Startup Current VDD = VDD−ON − 0.16 V, GATE Open 10 20 mA IDD−OP Operating Current VDD = 15 V, fS = 60 kHz, CL = 2 nF 4.5 5.5 mA Green−Mode Operating Supply Current (Average) VDD = 15 V, fS = 2 kHz, CL = 2 nF 3.5 mA Operating Current at PWM−Off Phase VDD = VDD−PWM−OFF − 0.5 V 90 mA V IDD−GREEN IDD−PWM−OFF Turn−Off Threshold Voltage 7 70 80 VDD−OVP VDD Over−Voltage−Protection (Latch−Off) 26 27 28 tVDD−OVP VDD OVP Debounce Time 100 150 200 IDD−LATCH VDD OVP Latch−Up Holding Current VDD = 5 V 42 ms mA HV STARTUP CURRENT SOURCE SECTION VHV−MIN IHV IHV−LC Minimum Startup Voltage on Pin HV Supply Current Drawn from Pin HV VAC = 90 V (VDC = 120 V), VDD = 0 V Leakage Current after Startup VHV = 500 V, VDD = VDD−OFF + 1 V 1.5 1 50 V 4.0 mA 20 mA FEEDBACK INPUT SECTION AV Internal Voltage to Current Sense Attenuation ZFB Input Impedance AV = DVCS/DVFB , 0 < VCS < 0.9 1/2.75 1/3.00 1/3.25 3 V/V 7 kW IOZ Bias Current 1.2 2 mA VOZ Zero Duty−Cycle Input Voltage 0.8 1.0 1.2 V VFB−OLP Open Loop Protection Threshold Voltage 3.9 4.2 4.5 V tD−OLP Debounce Time for Open Loop/Overload Protection 46 52 62 ms tSS FB = VOZ 5 Internal Soft−Start Time 5 ms DET PIN OVP AND VALLEY DETECTION SECTION VDET−OVP Comparator Reference Voltage 2.45 2.50 2.55 V AV Open−Loop Gain (Note 3) 60 dB BW Gain Bandwidth (Note 3) 1 MHz VV−HIGH Output High Voltage VV−LOW Output Low Voltage tDET−OVP 4.5 V 0.5 200 ms Maximum Source Current VDET = 0 V 1 mA VDET−HIGH Upper Clamp Voltage IDET = −1 mA 5 V VDET−LOW Lower Clamp Voltage IDET = 1 mA IDET−SOURCE Output OVP (Latched) Debounce Time 100 tVALLEY−DELAY Delay Time from Valley−Signal Detected to Output Turn−On (Note 3) 0.1 150 V 0.3 V 200 ns ms tOFF−BNK Leading−Edge−Blanking Time for DET when PWM MOS Turns Off (Note 3) FAN6300A 4.0 FAN6300H 1.5 tTIME−OUT Time−Out after tOFF−MIN FAN6300A 9 FAN6300H 5 www.onsemi.com 5 ms FAN6300A / FAN6300H ELECTRICAL CHARACTERISTICS (continued) (Unless otherwise specified, VDD = 10 ~ 25 V, TA = −40 ~ +105°C (TJ = TA)) (continued) Symbol Parameter Conditions Min Typ Max Unit 38 45 54 ms OSCILLATOR SECTION tON−MAX Maximum On−Time tOFF−MIN Minimum Off−Time VFB ≥ VN, FAN6300A 8 ms VFB ≥ VN, FAN6300H 3 ms VFB = VG, FAN6300A 38 ms VFB = VG, FAN6300H 13 VN Beginning of Green Mode at FB Voltage Level VG Beginning of Green Mode at FB Voltage Level 1.0 Green Mode VFB Hysteresis Voltage 0.05 VFB < VG 1.8 VFB > VFB−OLP 25 DVFBG tSTARTER 1.95 Start Timer (Time−Out Timer) 2.10 ms 2.25 V 1.2 1.4 V 0.10 0.20 V 2.1 2.4 ms 30 45 ms 1.5 V OUTPUT SECTION VOL Output Voltage Low VDD = 15 V, IO = 150 mA VOH Output Voltage High VDD = 12 V, IO = 150 mA 7.5 V tr Rising Time 145 200 ns tf Falling Time 55 120 ns 16.7 18.0 19.3 V 20 150 200 ns 0.85 VCLAMP Gate Output Clamping Voltage CURRENT SENSE SECTION tPD VLIMIT VSLOPE Delay to Output Limit Voltage on CS Pin for Over−Power Compensation IDET < 74.41 mA 0.82 0.88 V IDET = 550 mA 0.380 0.415 0.450 V Slope Compensation (Note 3) tON = 45 ms 0.3 V 0.1 tON = 0 ms tBNK Leading−Edge Blanking Time (MOS Turns ON) 525 VCS−H VCS Clamped High Voltage once CS Pin Floating CS Pin Floating tCS−H Delay Time once CS Pin Floating CS Pin Floating 625 4.5 V 725 5.0 ns V 150 ms INTERNAL OVER−TEMPERATURE PROTECTION SECTION TOTP Internal Threshold Temperature for OTP (Note 3) 125 °C TOTP−HYST Hysteresis Temperature for Internal OTP (Note 3) 5 °C Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 3. Guaranteed by design. www.onsemi.com 6 FAN6300A / FAN6300H TYPICAL PERFORMANCE CHARACTERISTICS 10.00 17.0 9.80 VDD−PWM−OFF (V) VDD−ON (V) 16.5 16.0 15.5 9.60 9.40 9.20 15.0 −40 −25 −10 5 20 35 50 65 80 95 9.00 −40 −25 −10 110 125 5 Temperature (°C) 50 65 80 95 110 125 95 110 125 Figure 7. Startup Current 8.1 18 8.0 16 7.9 14 IDD−ST (mA) VDD−OFF (V) 35 Temperature (°C) Figure 6. Turn−Off Threshold Voltage 7.8 7.7 12 10 8 7.6 7.5 −40 −25 −10 5 20 35 50 65 80 95 6 −40 −25 −10 110 125 5 20 35 50 65 80 Temperature (°C) Temperature (°C) Figure 4. Turn−On Threshold Voltage Figure 5. PWM−Off Threshold Voltage 4.0 4.50 3.5 4.20 3.0 3.90 IHV (mA) IDD−OP (mA) 20 3.60 2.5 2.0 3.30 1.5 3.00 −40 −25 −10 5 20 35 50 65 80 95 1.0 −40 −25 −10 110 125 Temperature (°C) 5 20 35 50 65 80 95 110 125 Temperature (°C) Figure 8. Operating Current Figure 9. Supply Current Drawn from HV Pin www.onsemi.com 7 FAN6300A / FAN6300H TYPICAL PERFORMANCE CHARACTERISTICS (continued) 0.32 0.40 0.31 0.35 VDET−LOW (V) IHV−LC (mA) 0.30 0.29 0.28 0.27 0.30 0.25 0.20 0.15 0.26 0.25 −40 −25 −10 5 20 35 50 65 80 95 0.10 −40 −25 −10 110 125 5 Temperature (°C) 50 65 80 95 110 125 Figure 11. Lower Clamp Voltage 2.52 8.70 2.51 8.40 tOff−min (ms) VDET−OVP (V) 35 Temperature (°C) Figure 10. Leakage Current after Startup 2.50 8.10 7.80 2.49 2.48 −40 −25 −10 5 20 35 50 65 80 95 7.50 −40 −25 −10 110 125 5 Temperature (°C) 20 35 50 65 80 95 110 125 Temperature (°C) Figure 12. Comparator Reference Voltage Figure 13. Minimum Off Time (VFB > VN) 42.0 2.50 2.40 tSTARTER (ms) 40.0 tOFF−MIN (ms) 20 38.0 36.0 34.0 2.30 2.20 2.10 2.00 32.0 −40 −25 −10 5 20 35 50 65 80 95 1.90 −40 −25 −10 110 125 5 20 35 50 65 80 95 Temperature (°C) Temperature (°C) Figure 14. Minimum Off Time (VFB = VG) Figure 15. Start Timer (VFB < VG) www.onsemi.com 8 110 125 FAN6300A / FAN6300H OPERATION DESCRIPTION The FAN6300A/H PWM controller integrates designs to enhance the performance of flyback converters. An internal valley voltage detector ensures power system operates at Quasi−Resonant (QR) operation across a wide range of line voltage. The following descriptions highlight some of the features of the FAN6300A/H. Startup Current For startup, the HV pin is connected to the line input or bulk capacitor through an external diode and resistor, RHV, which are recommended as 1N4007 and 100 kW. Typical startup current drawn from the HV pin is 1.2 mA and it charges the hold−up capacitor through the diode and resistor. When the VDD voltage level reaches VDD−ON, the startup current switches off. At this moment, the VDD capacitor only supplies the FAN6300A/H to maintain VDD until the auxiliary winding of the main transformer provides the operating current. Figure 17. First Valley Switching Green−Mode Operation The proprietary green−mode function provides off−time modulation to linearly decrease the switching frequency under light−load conditions. VFB, which is derived from the voltage feedback loop, is taken as the reference. In Figure 18, once VFB is lower than VN, tOFF−MIN increases linearly with lower VFB. The valley voltage detection signal does not start until tOFF−MIN finishes. Therefore, the valley detect circuit is activated after tOFF−MIN finishes, which decreases the switching frequency and provides extended valley voltage switching. However, in very light load condition, it might fail to detect the valley voltage due to too low of IDET−SOURCE after the tOFF−MIN. Under this condition, an internal tTIME−OUT signal initiates a new cycle start after a 9 ms delay (with 5 ms delay for H version). Figure 19 and Figure 20 show the two different conditions. Valley Detection The DET pin is connected to an auxiliary winding of the transformer via resistors of the divider to generate a valley signal once the secondary−side switching current discharges to zero. It detects the valley voltage of the switching waveform to achieve the valley voltage switching. This ensures QR operation, minimizes switching losses, and reduces EMI. Figure 16 shows divider resistors RDET and RA. When VAUX (in Figure 16) is negative, the DET pin voltage is clamped to VDET−LOW (0.3 V) by the sourcing current IDET−SOURCE. The valley of the drain voltage of the main power switch is detected when the sourcing current exceeds 30 mA during off time of the GATE signal. Reducing RDET makes the valley easier to be detected. tO F F -M I N 2 .1 m s 38/ 13 m s 8 / 3m s 1 .2 V 2 .1 V Figure 18. VFB vs. tOFF−MIN Curve Figure 16. Valley Detect Section The internal timer (minimum tOFF time) prevents gate retriggering within 8 ms (3 ms for H version) after the gate signal going−low transition. The minimum tOFF limit prevents system frequency being too high. Figure 17 shows a typical drain voltage waveform with first valley switching. www.onsemi.com 9 VF B FAN6300A / FAN6300H Gate Output The BiCMOS output stage is a fast totem−pole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 18 V Zener diode to protect power MOSFET transistors against undesired over−voltage gate signals. Over−Power Compensation When CS pin signal hits a VLIMIT threshold, GATE signal is terminated to limit the input power. To compensate the variation of over−power limit over wide AC input range, the current limit VLIMIT is adjusted according to IDET−SROUCE during on time of the GATE signal. During the GATE−on time, the amplitude of VAUX is proportional to VIN. IDET−SROUCE is dominated by VAUX/RDET at this duration. VLIMIT decreases linearly when IDET−SROUCE is higher than 74.41 mA. This results in a lower current limit at high−line input. Adjusting RDET affects the variation of VLIMIT across the input voltage range. Figure 19. Operation in Extended Valley Voltage Detection Mode Figure 20. Internal tTIME−OUT Initiates New Cycle after Failure to Detect Valley Voltage (with 5 ms Delay for FAN6300H version) Peak−Current−Mode PWM Peak−current−mode control is utilized to regulate output voltage and provide pulse−by−pulse current limiting. The switch current is detected by a sense resistor into the CS pin. The PWM duty cycle is determined by this current sense signal and VFB. When the voltage on CS reaches around (VFB−1.2)/3, the PWM signal is turned off immediately. Figure 21. H/L Line Constant Power Limit Compensated by DET Pin Leading−Edge Blanking (LEB) VDD Over−Voltage Protection Each time the power MOFFET switches on, a turn−on spike occurs on the sense resistor. To avoid premature termination of the switching pulse, lead−edge blanking time is built in. During the blanking period, the current limit comparator is disabled; it cannot switch off the gate driver. VDD over−voltage protection prevents damage due to abnormal conditions. Once the VDD voltage is over the VDD over−voltage protection voltage (VDD−OVP) and lasts for tVDD−OVP, the PWM pulse is disabled and the controller latches off. Under−Voltage Lockout (UVLO) Output Over−Voltage Protection The turn−on, PWM−off, and turn−off thresholds are fixed internally at 16/10/8 V. During startup, the startup capacitor must be charged to 16 V through the startup resistor to enable the IC. The hold−up capacitor continues to supply VDD until energy can be delivered from the auxiliary winding of the main transformer. VDD must not drop below 10 V during this startup process. This UVLO hysteresis window ensures that hold−up capacitor is adequate to supply VDD during startup. The output over−voltage protection works by the sampling voltage, as shown in Figure 22, after switch−off sequence. A 4 ms (1.5 ms for H version) blanking time ignores the leakage inductance ringing. A voltage comparator and a 2.5 V reference voltage develop an output OVP protection. The ratio of the divider determines the sampled voltage, as an optical coupler and secondary shunt www.onsemi.com 10 FAN6300A / FAN6300H Short−Circuit and Open−Loop Protection regulator are used. If the DET pin OVP is triggered, the power system enters latch−mode until AC power is removed. The FB voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built−in threshold for longer than tD−OLP, PWM output is turned off. As PWM output is turned off, the supply voltage VDD begins decreasing. When VDD goes below 8 V, the controller is totally shut down. VDD is charged up to the turn−on threshold voltage of 16 V through the startup resistor. This protection feature continues as long as the overloading condition persists. This prevents the power supply from overheating due to overloading. Figure 22. Voltage Sampled after 4 ms (1.5 ms for FAN6300H version) Blanking Time after Switch−Off Sequence ORDERING INFORMATION Device FAN6300AMY FAN6300HMY Operating Temperature Range Package Shipping† −40°C to +105°C 8−Lead, Small Outline Package (SOIC) (Pb−Free) 2500 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 11 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC8 CASE 751EB ISSUE A DOCUMENT NUMBER: DESCRIPTION: 98AON13735G SOIC8 DATE 24 AUG 2017 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. 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