FAN6300SY

FAN6300 Highly Integrated Quasi-Resonant Current Mode PWM Controller Features Description ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ ƒ The highly integrated FAN6300 PWM controller provides several features to enhance the performance of flyback converters. A built-in HV startup circuit can provide more startup current to reduce the startup time of the controller. Once the VDD voltage exceeds the turn-on threshold voltage, the HV startup function is disabled immediately to improve power consumption. An internal valley voltage detector ensures the power system operates at Quasi-Resonant operation in widerange line voltage and any load conditions and reduces switching loss to minimize switching voltage on drain of power MOSFET. High-Voltage Startup Quasi-Resonant Operation Cycle-by-Cycle Current Limiting Peak-Current-Mode Control Leading-Edge Blanking Internal Minimum tOFF Internal 2ms Soft-Start Over-Power Compensation GATE Output Maximum Voltage Auto-Recovery Short-Circuit Protection (FB Pin) Auto-Recovery Open-Loop Protection (FB Pin) VDD Pin & Output Voltage (DET Pin) OVP Latched FAN6300 controller also provides many protection functions. Pulse-by-pulse current limiting ensures the fixed peak current limit level, even when a short circuit occurs. Once an open-circuit failure occurs in the feedback loop, the internal protection circuit disables PWM output immediately. As long as VDD drops below the turn-off threshold voltage, controller also disables PWM output. The gate output is clamped at 18V to protect the power MOS from high gate-source voltage conditions. The minimum tOFF time limit prevents the system frequency from being too high. If the DET pin reaches OVP, internal OTP is triggered, and the power system enters latch-mode until AC power is removed. Applications ƒ ƒ To minimize standby power consumption and light-load efficiency, a proprietary green-mode function provides off-time modulation to decrease switching frequency and perform extended valley voltage switching to keep to a minimum switching voltage. AC/DC NB Adapters Open-Frame SMPS FAN6300 controller is available in 8-pin SOP and DIP packages. Ordering Information Part Number Operating Temperature Range FAN6300SY -40 to +105°C FAN6300DY -40 to +105°C Package Packing Method Green 8-Lead, Small Out-line Package (SOP) Tape & Reel Green 8-Lead, Dual In-line Package (DIP) Tube Eco Status For Fairchild’s definition of “green” Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2008 Fairchild Semiconductor Corporation FAN6300 • Rev. 1.0.3 www.fairchildsemi.com FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller October 2008 FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller Application Diagram Figure 1. Typical Application Internal Block Diagram HV VDD 8 6 FB 2 27V 2R Soft-Start 2ms R Timer 55ms Internal Bias OVP IHV 4.2V Latched Two Steps UVLO 16V/10V/8V FB OLP 500µs 30µs Starter CS 3 DRV Blanking Circuit S PWM Current Limit Over-Power Compensation SET 5 Q GATE 18V R IDET CLR Q Latched 0.3V tOFF-MIN (8µs/38µs) tOFF Blanking (4µs) S/H Valley Detector VDET 1st Valley tOFF-MIN +9µs VDET Latched 2.5V DET OVP DET 1 Internal OTP 0.3V 5V IDET Latched 4 7 GND NC Figure 2. Functional Block Diagram © 2008 Fairchild Semiconductor Corporation FAN6300 • Rev. 1.0.3 www.fairchildsemi.com 2 : Fairchild logo Z: Plant Code X: Year Code Y: Week Code TT: Die Run Code T: Package type (D =DIP, S = SOP) P: Y = Green Package M: Manufacturing flow code Figure 3. Marking Diagram Pin Configuration Figure 4. Pin Configuration Pin Definitions Pin # Name Description This pin is connected to an auxiliary winding of the transformer via resistors of the divider for the following purposes: FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller Marking Information - Generates a ZCD signal once the secondary-side switching current falls to zero. 1 DET - Produces an offset voltage to compensate the threshold voltage of the peak current limit to provide a constant power limit. The offset is generated in accordance with the input voltage when PWM signal is enabled. - Detects the valley voltage of the switching waveform to achieve the valley voltage switching and minimize the switching losses. A voltage comparator and a 2.5V reference voltage develop an output OVP protection. The ratio of the divider decides what output voltage to stop gate, as an optical coupler and secondary shunt regulator are used. The Feedback pin is supposed to be connected to the output of the error amplifier for achieving the voltage control loop. The FB should be connected to the output of the optical coupler if the error-amplifier is equipped at the secondary-side of the power converter. 2 FB For the primary-side control application, this pin is applied to connect a RC network to the ground for feedback-loop compensation. The input impedance of this pin is a 5kΩ equivalent resistance. A 1/3 attenuator connected between the FB and the PWM circuit is used for the loop gain attenuation. FAN6300 performs an open-loop protection once the FB voltage is higher than a threshold voltage (around 4.2V) more than 55ms. © 2008 Fairchild Semiconductor Corporation FAN6300 • Rev. 1.0.3 www.fairchildsemi.com 3 Name Description 3 CS 4 GND The power ground and signal ground. A 0.1µF decoupling capacitor placed between VDD and GND is recommended. 5 GATE Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped gate output voltage is 18V. 6 VDD 7 NC No connect. 8 HV High-voltage startup. Input to the comparator of the over-current protection. A resistor senses the switching current and the resulting voltage is applied to this pin for the cycle-by-cycle current limit. The threshold voltage for peak current limit is 0.8V. Power supply. The threshold voltages for startup and turn-off are 16V and 10V. The startup current is less than 20µA and the operating current is lower than 4.5mA. © 2008 Fairchild Semiconductor Corporation FAN6300 • Rev. 1.0.3 FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller Pin # www.fairchildsemi.com 4 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD Parameter Min. DC Supply Voltage Max. Unit 30 V VHV HV Pin 500 V VH GATE Pin -0.3 25.0 V VL VFB, VCS, VDET -0.3 7.0 V PD Power Dissipation TJ Operating Junction Temperature TSTG TL ESD Storage Temperature Range -55 Lead Temperature, Soldering 10 Seconds 400 mW +150 °C +150 °C +270 °C Human Body Model, JEDEC:JESD22-A114 2.5 Charged Device Model, JEDEC:JESD22-C101 1.5 KV Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to GND pin. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperature © 2008 Fairchild Semiconductor Corporation FAN6300 • Rev. 1.0.3 Min. Max. Unit -40 +105 °C FAN6300 — Highly Integrated Quasi-Resonant Current Mode PWM Controller Absolute Maximum Ratings www.fairchildsemi.com 5 VDD=15V, TA=25℃, unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units 25 V VDD SECTION VOP Continuously Operating Voltage VDD-ON Turn-on Threshold Voltage 15 16 17 V VDD-PWM-OFF PWM Off Threshold Voltage 9 10 11 V VDD-OFF Turn-Off Threshold Voltage 7 8 9 V IDD-ST Startup Current 0V< VDD < VDD-ON GATE Open 10 30 µA IDD-OP Operating Current VDD=15V, fs=60KHz, CL=2nF 4.5 5.5 mA Operating Current at PWM-Off Phase VDD=VDD-PWM-OFF-0.5V 70 80 90 µA IDD-PWM-OFF VDD-OVP VDD Over-Voltage Protection (Latch-Off) 26 27 28 V tVDD-OVP VDD OVP Debounce Time 100 150 200 µs HV STARTUP CURRENT SOURCE SECTION IHV IHV-LC Supply Current Drawn From HV Pin VAC=90V (VDC=120V), VDD=0V Leakage Current After Startup HV=500V, VDD=VDD-OFF +1V 1.2 mA 1 20 µA 1/2.75 1/3.00 1/3.25 V/V 3 5 7 KΩ 1.2 2.0 mA FEEDBACK INPUT SECTION AV Input-voltage to Current Sense Attenuation ZFB Input Impedance IOZ Bias Current VOZ Zero Duty Cycle Input Voltage VFB-OLP Open-Loop Protection Threshold Voltage tD-OLP Debounce Time for Open-Loop / Overload Protection tSS AV=ΔVCS/ΔVFB 0