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FAN6920MR
mWSaver™ Technology Integrated Critical-Mode PFC
and Quasi-Resonant Current-Mode PWM Controller
Features
Description
mWSaver™ Technology Provides Industry's Bestin-Class Standby Power
- Internal High-Voltage JFET Startup
- Adaptive Off-Time Modulation of tOFF-MIN for QR
PWM Stage, Improved Light-Load Efficiency
- PFC Burst or Shutdown at Light-Load Condition
- Optimized for Dual Switch Flyback Design to
Achieve > 90% Efficiency While Meeting 2013
ErP lot 6 Standby Power Requirement
Integrated PFC and Flyback Controller
Critical-Mode PFC Controller
Zero-Current Detection for PFC Stage
Quasi-Resonant Operation for PWM Stage
Internal 5 ms Soft-Start for PWM
Brownout Protection
High / Low Line Over-Power Compensation
Auto-Recovery Over-Current Protection
Auto-Recovery Open-Loop Protection
Externally Auto-Recovery Triggering (RT Pin)
Adjustable Over-Temperature Protection
VDD Pin and Output Voltage OVP (Auto-Recovery)
The highly integrated FAN6920MR combines Power
Factor Correction (PFC) controller and quasi-resonant
PWM controller. Integration provides cost-effective
design and reduces external components.
For PFC, FAN6920MR uses a controlled on-time
technique to provide a regulated DC output voltage and
to perform natural power-factor correction. With an
innovative THD optimizer, FAN6920MR can reduce
input current distortion at zero-crossing duration to
improve THD performance.
For PWM, FAN6920MR provides several functions to
enhance the power system performance: valley detection,
green-mode operation, and high / low line over-power
compensation. Protection functions include secondaryside open-loop and over-current with auto-recovery
protection; external auto-recovery triggering; adjustable
over-temperature protection by the RT pin; and external
NTC resistor, internal over-temperature shutdown, VDD
pin OVP, and the DET pin over-voltage for output OVP,
and brown-in / out for AC input voltage UVP.
The FAN6920MR controller is available in a 16-pin
small-outline package (SOP).
Related Resources
Evaluation Board: FEBFAN6920MR_T02U120A
Internal Over-Temperature Shutdown (140°C)
Applications
AC/DC NB Adapters
Open-Frame SMPS
Battery Charger
Ordering Information
Part Number
OLP Mode
Operating
Temperature Range
Package
Packing
Method
FAN6920MRMY
Recovery
-40°C to +105°C
16-Pin Small Outline Package (SOP)
Tape & Reel
© 2012 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
www.fairchildsemi.com
FAN6920MR — mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
February 2013
BCM Boost PFC
Quasi-Resonant Flyback
NBOOST
RCLAMP
RHV
CCLAMP
NP
VO
NS
+
NCZD
RPFC1
CINF2
CO.PFC
RG1
RPFC2
RCS1
RPFC3
165kΩ
RCZD
FAN6920MR
1 RANGE
HV 16
2
NC 15
RG2
RRT
RCS2
470nF
CCOMP
CINF1
COMP
3 INV
CRT
ZCD 14
4 CSPFC
VIN 13
5 CSPWM
RT 12
6 OPFC
FB 11
7 VDD
DET 10
8 OPWM
GND 9
NTC
RBIAS
RO1
RVIN1
CFB
VAC
RF
RVIN2
NA
CVIN
RDET1
CDD1
CDD2
RDET2
Figure 1. Typical Application Circuit
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
CF
KA431
RO2
FAN6920MR — mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Application Diagram
www.fairchildsemi.com
2
COMP
HV
VDD
2
16
7
RANGE
Multi-Vector Amp.
2.65V
2.75V
RANGE
2.75V
2.9V
Internal
Bias
OVP
IHV
OVP
15
NC
6
OPFC
Two-Step
UVLO
12V/7V/5V
27.5V
Auto-Recovery
UVP
2.3V
VCOMP-H
0.45V
ICOMP-BURST
INV
DRV
Debounce
70µs
VCOMP-L
R
Disable
Function
Debounce
PFC Burst Mode
VCTRL-PFC
VIN
VINV
5V
Timer
50ms
4.2V
FB
11
2.25ms
28µs
2R
Soft-Start
5ms
2.1V/1.75V
Inhibit
Timer
0.2V
Blanking
Circuit
4
Q
PFC Zero-Current
Detector
VCOMP-H
COMP-H
COMP-L
PFC
Current Limit
CLR
Restarter
Sawtooth
Generator
ton-max
THD
Optimizer
CSPFC
15.5V
AutoRecovery
Brownout
2.5V
0.82V
Q
COMP-L
COMP-H
3
SET
S
14
0.7V
Auto-Recovery
ZCD
10V
IZCD
VB
FB OLP
Starter
2.3V/0.8V
R
PWM-ON/OFF
VINV
CSPWM
5
DRV
Blanking
Circuit
S
PWM
Current Limit
Over-Power
Compensation
Auto-Recovery
tOFF
Blanking
(2.5µs)
S/H
Valley
Detector
(30µA)
IDET
1st
Valley
IRT
VINV
IDET
1V/1.2V
Brownout
Comparator
PFC RANGE Control
100µs
10ms
0.5V
Auto-Recovery
Debounce
100mS
1.2V
0.8V
0.7V
Internal
OTP
Debounce
Prog. OTP
/ Externally Triggering
9
12
13
GND
RT
VIN
2.4V/2.25V
Figure 2. Functional Block Diagram
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
1
RANGE
AutoRecovery
Protection
VB & Clamp
Vcomp to 1.6V
Debounce
Time
100µA
5V
OPWM
Q
DET Pin OVP
VDD Pin OVP
Internal OTP
Startup
Brownout
Protection
tOFF-MIN
+9µs
CLR
(RT Pin) Prog. OTP
(RT Pin) Externally Triggering
Auto-Recovery
2.5V
10
8
Auto-Recovery
VDET
DET OVP
DET
Q
17.5V
R
IDET
tOFF-MIN
(5µs/20.5µs/2.25ms)
SET
PFC Burst Mode
FAN6920MR — mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Internal Block Diagram
www.fairchildsemi.com
3
16
- Fairchild Logo
Z - Plant Code
X - Year Code
Y - Week Code
TT - Die Run Code
F - Frequency (M = Low, H = High Level)
O - OLP Mode (L = Latch, R = Recovery)
T - Package Type (M = SOP)
P - Y = Green Compound
M - Manufacturing Flow Code
ZXYTT
FAN6920FO
TPM
1
Figure 3. Marking Diagram
Pin Configuration
RANGE
1
16
HV
COMP
2
15
N.C.
3
14
ZCD
CSPFC
4
13
VIN
CSPWM
5
12
RT
OPFC
6
11
FB
VDD
7
10
DET
OPWM
8
9
GND
INV
Figure 4. Pin Configuration
Pin Definitions
Pin #
Name
Description
1
The RANGE pin’s impedance changes according to VIN pin voltage level. When the input voltage
RANGE detected by the VIN pin is higher than a threshold voltage, it sets to low impedance; whereas it
sets to high impedance if input voltage is at a high level.
2
COMP
Output pin of the error amplifier. It is a transconductance-type error amplifier for PFC output
voltage feedback. Proprietary multi-vector current is built-in to this amplifier; therefore, the
compensation for PFC voltage feedback loop allows a simple compensation circuit between this
pin and GND.
3
INV
Inverting input of the error amplifier. This pin is used to receive PFC voltage level by a voltage
divider and provides PFC output over- and under-voltage protections. This pin also controls the
PWM startup. Once the FAN6920MR is turned on and VINV exceeds in 2.3 V, PWM starts.
4
Input to the PFC over-current protection comparator that provides cycle-by-cycle current limiting
CSPFC protection. When the sensed voltage across the PFC current-sensing resistor reaches the internal
threshold (0.82 V typical), the PFC switch is turned off to activate cycle-by-cycle current limiting.
5
Input to the comparator of the PWM over-current protection and performs PWM current-mode
control with FB pin voltage. A resistor is used to sense the switching current of the PWM switch
CSPWM and the sensing voltage is applied to the CSPWM pin for the cycle-by-cycle current limit, currentmode control, and high / low line over-power compensation according to DET pin source current
during PWM tON time.
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
FAN6920MR — mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Marking Information
www.fairchildsemi.com
4
Pin #
Name
Description
6
OPFC
Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage is
15.5 V.
7
VDD
Power supply. The threshold voltages for startup and turn-off are 12 V and 7 V, respectively. The
startup current is less than 30 µA and the operating current is lower than 10 mA.
8
OPWM
Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped
gate output voltage is 17.5 V.
9
GND
The power ground and signal ground.
DET
This pin is connected to an auxiliary winding of the PWM transformer through a resistor divider for
the following purposes:
Producing an offset voltage to compensate the threshold voltage of PWM current limit for overpower compensation. The offset is generated in accordance with the input voltage when the
PWM switch is on.
Detecting the valley voltage signal of drain voltage of the PWM switch to achieve the valley
voltage switching and minimize the switching loss on the PWM switch.
Providing output over-voltage protection. A voltage comparator is built in to the DET pin. The
DET pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. This
flat voltage is reflected to the secondary winding during PWM inductor discharge time. If output
over voltage and this flat voltage are higher than 2.5 V, the controller stops all PFC and PWM
switching operation. The protection mode is auto-recovery.
11
FB
Feedback voltage pin used to receive the output voltage level signal to determine PWM gate duty
for regulating output voltage. The FB pin voltage can also activate open-loop, overload protection
and output-short circuit protection if the FB pin voltage is higher than a threshold of around 4.2 V
for more than 50 ms. The input impedance of this pin is a 5 kΩequivalent resistance. A 1/3
attenuator is connected between the FB pin and the input of the CSPWM/FB comparator.
12
RT
Adjustable over-temperature protection and external protection triggering. A constant current flows
out from the RT pin. When RT pin voltage is lower than 0.8 V (typical), protection is activated and
stops PFC and PWM switching operation. This protection is auto-recovery.
13
VIN
Line-voltage detection for brownin / out protections. This pin can receive the AC input voltage level
through a voltage divider. The voltage level of the VIN pin is not only used to control RANGE pin’s
status, but it can also perform brownin / out protection for AC input voltage UVP.
14
ZCD
Zero-current detection for the PFC stage. This pin is connected to an auxiliary winding coupled to
PFC inductor winding to detect the ZCD voltage signal once the PFC inductor current discharges
to zero. When the ZCD voltage signal is detected, the controller starts a new PFC switching cycle.
When the ZCD pin voltage is pulled to under 0.2 V (typical), it disables the PFC stage and the
controller stops PFC switching. This can be realized with an external circuit if disabling the PFC
stage is desired.
15
NC
No connection
16
HV
High-voltage startup pin is connected to the AC line voltage through a resistor (100 kΩtypical) for
providing a high charging current to VDD capacitor.
10
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
FAN6920MR — mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Pin Definitions (Continued)
www.fairchildsemi.com
5
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
30
V
VDD
DC Supply Voltage
VHV
HV
500
V
VH
OPFC, OPWM
-0.3
25.0
V
VL
INV, COMP, CSPFC, DET, FB, CSPWM, RT, VIN, RANGE
-0.3
7.0
V
Input Voltage to ZCD Pin
-0.3
12.0
V
VZCD
Power Dissipation
800
mW
θJA
PD
Thermal Resistance (Junction-to-Air)
104
°C/W
θJC
Thermal Resistance (Junction-to-Case)
TJ
TSTG
TL
41
°C/W
Operating Junction Temperature
-40
+150
°C
Storage Temperature Range
-55
+150
°C
+260
°C
Lead Temperature (Soldering, 10 Seconds)
(3)
ESD
Human Body Model, JESD22-A114 (All Pins Except HV Pin)
4500
Charged Device Model, JESD22-C101 (All Pins Except HV Pin)(3)
1250
V
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
2. All voltage values, except differential voltages, are given with respect to the GND pin.
3. All pins including HV pin: CDM=750 V, HBM 1000 V.
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
FAN6920MR — mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Absolute Maximum Ratings
www.fairchildsemi.com
6
VDD=15 V and TA=25°C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
25
V
VDD Section
VOP
Continuously Operating Voltage
VDD-ON
Turn-On Threshold Voltage
10.5
12.0
13.5
V
VDD-PWM-OFF
PWM Off Threshold Voltage
6
7
8
V
VDD-OFF
Turn-Off Threshold Voltage
4
5
6
V
20
30
µA
10
mA
IDD-ST
Startup Current
VDD=VDD-ON - 0.16 V,
Gate Open
IDD-OP
Operating Current
VDD=15 V, OPFC,
OPWM=100 kHz,
CL-PFC, CL-PWM=2 nF
IDD-GREEN
Green-Mode Operating Supply Current
(Average)
VDD=15 V,
OPWM=450 Hz,
CL-PWM=2 nF
IDD-PWM-OFF
Operating Current at PWM-Off Phase
VDD=VDD-PWM-OFF 0.5 V
5.5
mA
70
120
170
µA
VDD-OVP
VDD Over-Voltage Protection
(Auto-Recovery)
26.5
27.5
28.5
V
tVDD-OVP
VDD OVP Debounce Time
100
150
200
µs
HV Startup Current Source Section
IHV
Supply Current Drawn from HV Pin
VAC=90 V,
(VDC=120 V), VDD=0 V
1.3
HV=500 V,
VDD=VDD-OFF +1 V
mA
1.0
µA
VIN and RANGE Section
VVIN-UVP
VVIN-RE-UVP
tVIN-UVP
Threshold Voltage for AC Input UnderVoltage Protection
Under-Voltage Protection Reset
Voltage
Under-Voltage Protection Debounce
Time
0.95
1.00
1.05
V
VVIN-UVP
+0.15 V
VVIN-UVP
+0.20 V
VVIN-UVP
+0.25 V
V
70
100
130
ms
VVIN-RANGE-H
High VVIN Threshold for RANGE
Comparator
2.40
2.45
2.50
V
VVIN-RANGE-L
Low VVIN Threshold for RANGE
Comparator
2.20
2.25
2.30
V
60
90
120
ms
tRANGE
Range-Enable / Disable Debounce
Time
VRANGE-OL
Output Low Voltage of RANGE Pin
IO=1 mA
0.5
V
IRANGE-OH
Output High Leakage Current of
RANGE Pin
RANGE=5 V
50
nA
PFC Maximum On Time
RMOT=24 k
28
µs
tON-MAX-PFC
22
25
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
FAN6920MR — mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Electrical Characteristics
www.fairchildsemi.com
7
VDD=15V and TA=25°C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
100
125
150
µmho
2.465
2.500
2.535
V
RANGE=Open
2.70
2.75
2.80
RANGE=Ground
2.60
2.65
2.70
VINV-H / VREF,
RANGE=Open
1.06
1.14
VINV-H / VREF,
RANGE=Ground
1.04
1.08
PFC STAGE
Voltage Error Amplifier Section
Gm
Transconductance(4)
VREF
Feedback Comparator Reference
Voltage
VINV-H
Clamp High Feedback Voltage
VRATIO
VINV-L
Clamp High Output Voltage Ratio
(4)
Clamp Low Feedback Voltage
V
V/V
2.35
2.45
RANGE=Open
2.25
2.90
2.95
V
RANGE=Ground
2.75
2.80
50
70
90
µs
VINV-OVP
Over-Voltage Protection for INV Input
tINV-OVP
Over-Voltage Protection Debounce Time
VINV-UVP
Under-Voltage Protection for INV Input
0.35
0.45
0.55
V
VINV-PWMON
PWM ON Threshold Voltage on INV Pin
2.2
2.3
2.4
V
VHYST-PWMON
Hysteresis for PWM ON Threshold
Voltage on INV Pin
V
VINV-
VINV-
VINV-
PWMON
PWMON
PWMON
-1.6
-1.5
-1.4
50
70
90
µs
V
tINV-UVP
Under-Voltage Protection Debounce
Time
VINV-BO
PWM and PFC Off Threshold for
Brownout Protection
1.15
1.20
1.25
V
VCOMP-BO
Limited Voltage on COMP Pin for
Brownout Protection
1.55
1.60
1.65
V
Internal Bias Current for PFC Burst Mode
120
150
180
µA
ICOMP-BURST
Comparator Output High Voltage
VCOMP-H
Comparator Output High Voltage at PFC
Burst Mode
VCOMP-L
Comparator Output Low Voltage at PFC
Burst Mode
VOZ
Zero Duty Cycle Voltage on COMP Pin
Comparator Output Source Current
4.80
2.20
2.30
2.40
VFB=1.3 V, VVIN=1.6 V
2.00
2.10
2.20
VFB=1.3 V, VVIN=2 V
1.80
1.90
2.00
RANGE=Open,
VFB=1.3 V
0.9
1.0
1.1
V
1.10
1.25
1.40
V
15
30
45
µA
mA
VINV=2.3 V,
VCOMP=1.5 V
VINV=1.5 V
ICOMP
Comparator Output Sink Current
5.20
VFB=1.3 V, VVIN=1.2 V
0.50
0.75
1.00
RANGE=Open,
VINV=2.75 V,
VCOMP=5 V
20
30
40
RANGE=Ground,
VINV=2.65 V,
VCOMP=5 V
20
V
µA
30
40
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
FAN6920MR — mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Electrical Characteristics (Continued)
www.fairchildsemi.com
8
VDD=15 V and TA=25°C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
0.77
0.82
0.87
V
PFC Current-Sense Section
VCSPFC
Threshold Voltage for Peak Current
Cycle-by-Cycle Limit
VCOMP=5 V
tPD
Propagation Delay
110
200
ns
tBNK
Leading-Edge Blanking Time
110
180
250
ns
AV
CSPFC Compensation Ratio for THD
0.90
0.95
1.00
V/V
14.0
15.5
17.0
V
1.5
V
PFC Output Section
VZ
PFC Gate Output Clamping Voltage
VDD=25 V
VOL
PFC Gate Output Voltage Low
VDD=15 V,
IO=100 mA
VOH
PFC Gate Output Voltage High
VDD=15 V,
IO=100 mA
8
tR
PFC Gate Output Rising Time
VDD=12 V, CL=3 nF,
20~80%
30
65
100
ns
tF
PFC Gate Output Falling Time
VDD=12 V, CL=3 nF,
80~20%
30
50
70
ns
Input Threshold Voltage Rising Edge
VZCD Increasing
1.9
2.1
2.3
V
VZCD-HYST
Threshold Voltage Hysteresis
VZCD Decreasing
0.25
0.35
0.45
V
VZCD-HIGH
Upper Clamp Voltage
IZCD=3 mA
8
10
VZCD-LOW
Lower Clamp Voltage
0.35
0.45
0.55
V
VZCD-SSC
Starting Source Current Threshold
Voltage
0.70
0.90
1.10
V
200
ns
V
PFC Zero-Current Detection Section
VZCD
tDELAY
tRESTART-PFC
tINHIB
Maximum Delay from ZCD to Output
Turn-On
VCOMP=5 V,
fS=60 kHz
Restart Time
Inhibit Time (Maximum Switching
Frequency Limit)
VZCD-DIS
PFC Enable / Disable Function
Threshold Voltage
tZCD-DIS
PFC Enable / Disable Function
Debounce Time
VCOMP=5 V
VZCD=100 mV
100
V
300
500
700
µs
1.5
2.5
3.5
µs
0.15
0.20
0.25
V
100
150
200
µs
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
FAN6920MR — mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Electrical Characteristics (Continued)
www.fairchildsemi.com
9
VDD=15 V and TA=25°C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
1/2.75
1/3.00
1/3.25
V/V
3
5
7
kΩ
1.2
2.0
mA
PWM STAGE
Feedback Input Section
AV
Input-Voltage to Current Sense
Attenuation(4)
AV=VCS /VFB ,
0 < VCS < 0.9
ZFB
Input Impedance(4)
VFB > VG
IOZ
Bias Current
VFB=VOZ
VOZ
Zero Duty Cycle Input Voltage
0.7
0.9
1.1
V
VFB-OLP
Open-Loop Protection Threshold
Voltage
3.9
4.2
4.5
V
tFB-OLP
The Debounce Time for Open-Loop
Protection
40
50
60
ms
tFB-SS
Internal Soft-Start Time(4)
4
5
6
ms
2.45
2.50
2.55
VFB=0 V~3.6 V
DET Pin OVP and Valley Detection Section
VDET-OVP
Comparator Reference Voltage
V
Av
Open-Loop Gain(4)
60
dB
BW
Gain Bandwidth(4)
1
MHz
tDET-OVP
IDET-SOURCE
VDET-LOW
tVALLEY-DELAY
Output OVP (Auto-Recovery) Debounce
Time
100
Maximum Source Current
VDET=0 V
Lower Clamp Voltage
IDET=1 mA
Delay Time from Valley Signal Detected
to Output Turn-On(4)
tOFF-BNK
Leading-Edge Blanking Time for DETOVP (2.5 V) and Valley Signal when
PWM MOS Turns Off(4)
tTIME-OUT
Time-Out After tOFF-MIN(4)
150
200
µs
1
mA
0.15
0.25
0.35
V
150
200
250
ns
2.5
µs
8
9
10
µs
38
45
52
µs
PWM Oscillator Section
tON-MAX-PWM
Maximum On-Time
tOFF-MIN
Minimum Off-Time
VFB ≧ VN, TA=25°C
5
VFB=VG
µs
20.5
VN
Beginning of Green-On Mode at FB
Voltage Level
1.95
2.10
2.25
V
VG
Beginning of Green-Off Mode at FB
Voltage Level
1.00
1.15
1.30
V
ΔVG
Hysteresis for Beginning of Green-Off
Mode at FB Voltage Level(4)
0.1
V
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
FAN6920MR — mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Electrical Characteristics (Continued)
www.fairchildsemi.com
10
VDD=15 V and TA=25°C unless otherwise noted.
Symbol
VCTRL-PFC-BM
Parameter
Threshold Voltage on FB Pin for PFC
Burst Mode
Conditions
Min.
Typ.
Max.
RANGE Pin
Internally Open
1.65
1.70
1.75
RANGE Pin
Internally Ground
1.60
1.65
1.70
1.75
1.80
1.85
Unit
V
VCTRL-PFC-ON
Threshold Voltage on FB Pin for PFC
Normal operating
tPFC-BM
Debounce Time for PFC Burst Mode
PFC Normal
Operating Burst
Mode
100
ms
tPFC-ON
Debounce Time for PFC Recovery to
Normal Operating
PFC Burst Mode
Normal Operating
200
µs
VFB ＜ VG, TA=25°C
tSTARTER-PWM Start Timer (Time-Out Timer)
VFB ＞ VFB-OLP,
TA=25°C
V
1.85
2.25
2.65
ms
22
28
34
µs
16.0
17.5
19.0
V
1.5
V
PWM Output Section
VCLAMP
PWM Gate Output Clamping Voltage
VDD=25 V
VOL
PWM Gate Output Voltage Low
VDD=15 V,
IO=100 mA
VOH
PWM Gate Output Voltage High
VDD=15 V,
IO=100 mA
tR
PWM Gate Output Rising Time
CL =3 nF,
VDD=12 V, 20~80%
80
110
ns
tF
PWM Gate Output Falling Time
CL=3 nF, VDD=12 V,
20~80%
40
70
ns
150
200
ns
8
V
Current Sense Section
tPD
VLIMIT
VSLOPE
tON-BNK
VCS-FLOATING
tCS-H
Delay to Output
Limit Voltage on CSPWM Pin for OverPower Compensation
Slope Compensation(4)
IDET ＜ 75 µA,
TA=25°C
0.81
0.84
0.87
IDET=185 µA,
TA=25°C
0.69
0.72
0.75
IDET=350 µA,
TA=25°C
0.55
0.58
0.61
IDET=550 µA,
TA=25°C
0.37
0.40
0.43
tON =45 µs,
RANGE=Open
0.25
0.30
0.35
tON=0 µs
0.05
0.10
0.15
V
Leading-Edge Blanking Time
300
CSPWM Pin Floating VCSPWM Clamped
High Voltage
CSPWM Pin
Floating
Delay Time, CS Pin Floating
CSPWM Pin
Floating
4.5
ns
5.0
150
V
V
µs
Continued on the following page…
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
FAN6920MR — mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Electrical Characteristics (Continued)
www.fairchildsemi.com
11
VDD=15 V and TA=25°C unless otherwise noted.
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
125
140
155
°C
RT Pin Over-Temperature Protection Section
TOTP
Internal Threshold Temperature for
OTP(4)
TOTP-HYST
Hysteresis Temperature for Internal
OTP(4)
IRT
VRT-AR
VRT-OTP-LEVEL
30
Internal Source Current of RT Pin
°C
90
100
110
µA
Protection Triggering Voltage
0.75
0.80
0.85
V
Threshold Voltage for Two-Level
Debounce Time
0.45
0.50
0.55
V
tRT-OTP-H
Debounce Time for OTP
10
tRT-OTP-L
Debounce Time for Externally Triggering VRT < VRT-OTP-LEVEL
Note:
4. Guaranteed by design.
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
70
110
ms
150
µs
FAN6920MR — mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Electrical Characteristics (Continued)
www.fairchildsemi.com
12
12.5
7.85
7.8
VDD-PWM-OFF (V)
VDD-ON (V)
12
11.5
11
7.75
7.7
7.65
7.6
7.55
10.5
7.5
10
7.45
-40
-30
-15
0
25
50
75
85
100
125
-40
-30
-15
0
Temperature (ºC)
25
50
75
85
100
125
Temperature (ºC)
Figure 5. Turn-On Threshold Voltage
Figure 6. PWM-Off Threshold Voltage
6
29.0
28.5
VDD-OVP (V)
VDD-OFF (V)
5
4
3
2
28.0
27.5
1
27.0
-40 -25 -10
0
-40
-30
-15
0
25
50
75
85
100
5
125
Figure 7. Turn-Off Threshold Voltage
35
50
65
80
95 110 125
Figure 8. VDD Over-Voltage Protection Threshold
16.0
8.0
14.0
7.0
IDD-OP (mA)
IDD-ST (mA)
20
Temperature(oC)
Temperature (ºC)
12.0
10.0
8.0
6.0
6.0
5.0
4.0
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
Temperature(oC)
20
35
50
65
80
95 110 125
Temperature(oC)
Figure 9. Startup Current
Figure 10. Operating Current
2.60
17.0
16.5
16.0
VZ(V)
VREF (V)
2.55
2.50
15.5
15.0
2.45
14.5
14.0
2.40
-40 -25 -10
5
20
35
50
65
80
-40 -25 -10
95 110 125
Figure 11. PFC Output Feedback Reference Voltage
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
5
20
35
50
65
80
95 110 125
Temperature(oC)
Temperature(oC)
Figure 12. PFC Gate Output Clamping Voltage
FAN6920MR — mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Typical Performance Characteristics
www.fairchildsemi.com
13
28.0
0.95
tON-MAX-PFC ( msec)
27.0
0.90
VCSPFC (V)
26.0
25.0
24.0
0.85
0.80
23.0
22.0
0.75
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
5
20
Temperature(oC)
35
50
65
80
95 110 125
Temperature(oC)
Figure 13. PFC Maximum On-Time
Figure 14. PFC Peak Current Limit Voltage
45
19.0
44
tON-MAX-PWM (µs)
18.5
VCLAMP (V)
18.0
17.5
17.0
43
42
41
40
16.5
39
16.0
-40 -25 -10
5
20
35
50
65
80
38
95 110 125
-40
-30
-15
0
o
Temperature( C)
50
75
85
100
125
Figure 16. PWM Maximum On-Time
2.3
1.4
2.2
1.3
VG(V)
VN(V)
Figure 15. PWM Gate Output Clamping Voltage
2.1
2.0
1.2
1.1
1.9
1.0
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
Temperature(oC)
5
20
35
50
65
80
95 110 125
Temperature(oC)
Figure 17. Beginning of Green-On Mode at VFB
Figure 18. Beginning of Green-Off Mode at VFB
21.5
5
4.9
21
4.8
20.5
tOFF,MIN (µs)
tOFF,MIN (µs)
25
Temperature (ºC)
4.7
4.6
4.5
20
19.5
4.4
19
4.3
18.5
4.2
18
-40
-30
-15
0
25
50
75
85
100
125
-40
Temperature (ºC)
-15
0
25
50
75
85
100
125
Temperature (ºC)
Figure 19. PWM Minimum Off-Time for VFB > VN
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
-30
Figure 20. PWM Minimum Off-Time for VFB=VG
FAN6920MR — mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Typical Performance Characteristics (Continued)
www.fairchildsemi.com
14
0.295
2.60
VDET-OVP (V)
VDET-LOW (V)
0.29
0.285
0.28
2.55
2.50
2.45
0.275
2.40
0.27
-40
-30
-15
0
25
50
75
85
100
-40 -25 -10
125
5
35
50
65
80
95 110 125
Figure 22. Reference Voltage for Output
Over-Voltage Protection of DET Pin
Figure 21. Lower Clamp Voltage of DET Pin
110
0.90
105
0.85
VRT-LATCH (V)
IRT ( mA)
20
Temperature(oC)
Temperature (ºC)
100
95
90
0.80
0.75
0.70
-40 -25 -10
5
20
35
50
65
80
95 110 125
-40 -25 -10
Temperature(oC)
20
35
50
65
80
95 110 125
Temperature(oC)
Figure 24. Over-Temperature Protection
Threshold Voltage of RT Pin
Figure 23. Internal Source Current of RT Pin
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
5
FAN6920MR — mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Typical Performance Characteristics (Continued)
www.fairchildsemi.com
15
PFC Stage
Multi-Vector Error Amplifier and THD Optimizer
VCOMP
RS
PFC
MOS Filp-Flop
For better dynamic performance, faster transient
response, and precise clamping on the PFC output,
FAN6920MR uses a transconductance type amplifier
with proprietary innovative multi-vector error amplifier.
The schematic diagram of this amplifier is shown in
Figure 25. The PFC output voltage is detected from the
INV pin by an external resistor divider circuit that
consists of R1 and R2. When PFC output variation
voltage reaches 6% over or under the reference voltage
of 2.5 V, the multi-vector error amplifier adjusts its
output sink or source current to increase the loop
response to simplify the compensated circuit.
2.65V
PFC VO
Error
Amplifier
R1
2.5V
3
THD
Optimizer
4
RS
+
INV
R2
+
CSPFC
Sawtooth
Generator
FAN6920MR
Figure 26. Multi-Vector Error Amplifier with
THD Optimizer
IL,AVG (Fixed On-Time)
IL,AVG (with THD Optimizer)
PFC VO
2.35V
R1
COMP
2
CCOMP
2.5V
CO
INV
3
Error
Amplifier
Gate Signal
with
THD Optimizer
VCOMP
R2
Sawtooth
FAN6920MR
Gate Signal with
Fixed On-Time
Figure 27. Operation Waveforms of Fixed On-Time
with and without THD Optimizer
Figure 25. Multi-Vector Error Amplifier
The feedback voltage signal on the INV pin is compared
with reference voltage 2.5 V, which makes the error
amplifier source or sink current to charge or discharge
its output capacitor CCOMP. The COMP voltage is
compared with the internally generated sawtooth
waveform to determine the on-time of PFC gate.
Normally, with lower feedback loop bandwidth, the
variation of the PFC gate on-time should be very small
and almost constant within one input AC cycle.
However, the power factor correction circuit operating at
light-load condition has a defect, zero crossing
distortion; which distorts input current and makes the
system’s Total Harmonic Distortion (THD) worse. To
improve the result of THD at light-load condition,
especially at high input voltage, an innovative THD
optimizer is inserted by sampling the voltage across the
current-sense resistor. This sampling voltage on
current-sense resistor is added into the sawtooth
waveform to modulate the on-time of PFC gate, so it is
not constant on-time within a half AC cycle. The method
of operation block between THD optimizer and PWM is
shown in Figure 26. After THD optimizer processes,
around the valley of AC input voltage, the compensated
on-time becomes wider than the original. The PFC ontime, which is around the peak voltage, is narrowed by
the THD optimizer. The timing sequences of the PFC
MOS and the shape of the inductor current are shown in
Figure 27. Figure 28 shows the difference between
calculated fixed on-time mechanism and fixed on-time
with THD optimizer during a half AC cycle.
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
OFF
ON
Input Current
1.8
1.5
Current (A)
1.2
0.9
0.6
PO : 90W
Input Voltage : 90VAC
PFC Inductor : 460mH
CS Resistor : 0.15
0.3
0
0
0.0014
0.0028
0.0042
0.0056
Time (Seconds)
0.0069
0.0083
Fixed On-time with THD Optimizer
Fixed On time
Figure 28. Calculated Waveforms of Fixed On-Time
with and without THD Optimizer During a Half
AC Cycle
FAN6920MR — mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Functional Description
www.fairchildsemi.com
16
VZCD
A built-in low-voltage MOSFET can be turned on or off
according to VVIN voltage level and PFC status. The
drain pin of this internal MOSFET is connected to the
RANGE pin. Figure 29 shows the status curve of VVIN
voltage level and RANGE impedance (open or ground).
10V
2.1V
1.75V
PFC Burst Mode Condition
PFC Normal Mode Condition
VDS
RANGE=
Ground
t
PFCVO
VIN,MAX
RANGE=
Open
VVIN-RANGE-L
VVIN
VVIN-RANGE-H
Figure 29. Hysteresis Behavior between RANGE Pin
and VIN Pin Voltage
t
PFC
Gate
Zero-Current Detection (ZCD Pin)
Figure 30 shows the internal block of zero-current
detection. The detection function is performed by
sensing the information on an auxiliary winding of the
PFC inductor. Referring to Figure 31, when PFC MOS is
off, the stored energy of the PFC inductor starts to
release to the output load. Then the drain voltage of
PFC MOS starts to decrease since the PFC inductor
resonates with parasitic capacitance. Once the ZCD pin
voltage is lower than the triggering voltage (1.75 V
typical), the PFC gate signal is sent again to start a new
switching cycle.
If PFC operation needs to be shut down due to
abnormal condition, pull the ZCD pin LOW, voltage
under 0.2 V (typical), to activate the PFC disable
function to stop PFC switching operation.
For preventing excessive high switching frequency at
light load, a built-in inhibit timer is used to limit the
minimum tOFF time. Even if the ZCD signal has been
detected, the PFC gate signal is not sent during the
inhibit time (2.5 µs typical).
Inhibit
Time
t
Figure 31. Operation Waveforms of PFC
Zero-Current Detection
Protection for PFC Stage
PFC Output Voltage UVP and OVP (INV Pin)
FAN6920MR provides several kinds of protection for
PFC stage. PFC output over- and under-voltage are
essential for PFC stage. Both are detected and
determined by INV pin voltage, as shown in Figure 32.
When INV pin voltage is over 2.75 V or under 0.45 V,
due to overshoot or abnormal conditions, and lasts for a
de-bounce time around 70 µs; the OVP or UVP circuit is
activated to stop PFC switching operation immediately.
The INV pin is not only used to receive and regulate
PFC output voltage; it can also perform PFC output
OVP/ UVP protection. For failure-mode test, this pin can
shut down PFC switching if pin floating occurs.
VO
0.25V
PFC Gate
Drive
Q
VREF (2.5V)
R
S
RZCD
Lb
Ccomp
FAN6920MR
OVP = (VINV ≥ 2.75V)
UVP = (VINV ≤ 0.45V)
1:n
Figure 32. Internal Block of PFC Overand Under-Voltage Protection
Figure 30. Internal Block of the Zero-Current
Detection
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
CO
3
FAN6920MR
2.1V
PFC Gate On
Voltage
Detector
Error
Amplifier
10V
S
INV
2
VAC
5
1.75V
Vcomp
COMP
ZCD
0.2V
Q R
Debounce
Time
Driver
FAN6920MR —mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
RANGE Pin
www.fairchildsemi.com
17
During PFC stage switching operation, the PFC switch
current is detected by the current-sense resistor on the
CSPFC pin and the detected voltage on this resistor is
delivered to the input terminal of a comparator and
compared with a threshold voltage 0.82 V (typical).
Once the CSPFC pin voltage is higher than the
threshold voltage, the PFC gate is turned off
immediately.
The PFC peak switching current is adjustable by the
current-sense resistor. Figure 33 shows the measured
waveform of PFC gate and CSPFC pin voltage.
AC Input
VCOMP-BO
VCOMP
1.6V
VVIN-UVP
VVIN
VVIN-RE-UVP
0V
PFC MOS Current Limit
0.82V
VINV-BO
2.5V
VINV
1.2V
CSPFC
OPWM
OPFC
OPFC
Brownout
Protection
Debounce
Time 100ms
Brownout Protection (VIN Pin)
VDD
VDD Hiccup Mode
Brownout
Brown-In
AC Input
OPWM
OPFC
Figure 35. Measured Waveform of Brownout / In
Protection (Adapter Application)
The measured waveforms of brownout / in protection
are shown in Figure 35.
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
Hiccup
Mode
Figure 34. Operation Waveforms of Brownout /
In Protection
Figure 33. Cycle-by-Cycle Current Limiting
With AC voltage detection, FAN6920MR can perform
brownout / in protection (AC voltage UVP). Figure 34
shows the key operation waveforms of brownout / in
protection. Both use the VIN pin to detect AC input
voltage level and the VIN pin is connected to AC input
by a resistor divider (refer to Figure 1); therefore, the
VVIN voltage is proportional to the AC input voltage.
When the AC voltage drops and VVIN voltage is lower
than 1 V for 100 ms, the UVP protection is activated and
the COMP pin voltage is clamped to around 1.6 V.
Because PFC gate duty is determined by comparing the
sawtooth waveform and COMP pin voltage, lower
COMP voltage results in narrow PFC on-time, so that
the energy converged is limited and the PFC output
voltage decreases. When INV pin voltage is lower than
1.2 V, FAN6920MR stops all PFC and PWM switching
operation immediately until VDD voltage drops to turn-off
voltage then rises to turn-on voltage again (UVLO).
When the brownout protection is activated, all switching
operation is turned off and VDD voltage enters Hiccup
Mode up and down continuously. Once VVIN voltage is
higher than 1.3 V (typical) and VDD reaches turn-on
voltage again, the PWM and PFC gate is sent.
Brownout
Protection
FAN6920MR —mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
PFC Peak Current Limiting (CSPFC Pin)
www.fairchildsemi.com
18
2.3
VINV
Enter PFC Burst Mode
2.1
1.9
VCOMP-H (V)
To minimize the power dissipation at light-load
condition, the FAN6920MR PFC control enters burstmode operation. As the load decreases, the PWM
feedback voltage (VFB) decreases. When VFB < VCTRLPFC-BM for 100 ms, the device enters PFC burst mode,
the VCOMP pulls high to VCOMP-H, and PFC output voltage
increases. When the PFC feedback voltage on INV pin
(VINV) triggers the OVP threshold voltage (VINV-OVP),
VCOMP pulls low to VCOMP-L, the OPFC pin switching
stops and the PFC output voltages start to drop. Once
the VINV drops below the feedback comparator reference
voltage (VREF), VCOMP pulls high to VCOMP-H and OPFC
starts switching again. Burst-mode operation alternately
enables and disables switching of the power MOSFET
to reduce the switching loss at light-load condition.
1.7
1.5
1.3
VOZ
1.1
0.9
0.7
1.2
1.7
2.2
2.7
3.2
3.7
4.2
VVIN(V)
Figure 37. VCOMP-H Voltage vs. VVIN Voltage
Characteristic Curve
PWM Stage
VINV-OVP
HV Startup and Operating Current (HV Pin)
VREF
VCOMP
VCOMP-H
VCOMP-L
OPFC
Normal
Mode
PFC Burst Mode
Figure 36. PFC Burst Mode Behavior
The VCOMP-H is adjusted by the VIN pin voltage, as
shown in Figure 37. Since the VIN pin is connected to
rectified AC input line voltage through the resistive
divider, a higher line voltage generates a higher VIN pin
voltage. The VCOMP-H decreases as VIN pin voltage
increases, limiting the PFC choke current at a higher
input voltage to reduce acoustic noise. If the VCOMP-H is
below the PFC VOZ, the PFC automatically shuts down
at light load with high line voltage input condition.
The HV pin is connected to the AC line through a
resistor (refer to Figure 1). With a built-in high-voltage
startup circuit, when AC voltage is applied to the power
system, FAN6920MR provides a high current to charge
the external VDD capacitor to speed up controller’s
startup time and build up normal rated output voltage
within three seconds. To save power consumption, after
VDD voltage exceeds turn-on voltage and enters normal
operation; this high-voltage startup circuit is shut down
to avoid power loss from startup resistor.
Figure 38 shows the characteristic curve of VDD voltage
and operating current IDD. When VDD voltage is lower
than VDD-PWM-OFF, FAN6920MR stops all switching
operation and turns off unnecessary internal circuits to
reduce operating current. By doing so, the period from
VDD-PWM-OFF to VDD-OFF can be extended and the hiccup
mode frequency can be decreased to reduce the input
power in case of output short circuit. Figure 39 shows
the typical waveforms of VDD voltage and gate signal
with hiccup mode operation.
IDD
IDD-OP
IDD-PWM-OFF
IDD-ST
VDD
VDD-OFF VDD-PWM-OFF VDD-ON
Figure 38. VDD vs. IDD-OP Characteristic Curve
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
FAN6920MR —mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
PFC Burst Mode
www.fairchildsemi.com
19
IDD-OP
VDD-PWM-OFF
VDD-OFF
IDD-PWM-OFF IDD-ST
Gate
Figure 39. Typical Waveform of VDD Voltage and
Gate Signal at Hiccup Mode Operation
PWM switch start to resonate concurrently. When the
drain voltage on the PWM switch falls, the voltage
across on auxiliary winding VAUX also decreases since
the auxiliary winding is coupled to the primary winding.
Once the VAUX voltage resonates and falls to negative,
VDET voltage is clamped by the DET pin (refer to Figure
41) and FAN6920MR is forced to flow out a current IDET.
FAN6920MR reflects and compares this IDET current. If
this source current rises to a threshold current, the
PWM gate signal is sent out after a fixed delay time
(200 ns typical).
Auxiliary
Winding
Green-Mode Operation and PFC-ON / OFF Control
(FB Pin)
Green mode further reduces power loss in the system
(e.g. switching loss). Through off-time modulation to
regulate switching frequency according to FB pin
voltage. When output loading decreases, FB voltage
lowers due to secondary feedback movement and the
tOFF-MIN is extended. After tOFF-MIN (determined by FB
voltage), the internal valley-detection circuit is activated
to detect the valley on the drain voltage of the PWM
switch. When the valley signal is detected, FAN6920MR
outputs a PWM gate signal to turn on the switch and
begin a new switching cycle.
With green mode operation and valley detection, at
light-load condition; the power system can perform
extended valley switching a DCM operation and can
further reduce switching loss for better conversion
efficiency. The FB pin voltage versus tOFF-MIN time
characteristic curve is shown in Figure 40. As Figure 40
shows, FAN6920MR can narrow down to 2.25 ms tOFF
time, which is around 440 Hz switching frequency.
Referring to Figure 1 and Figure 2, FB pin voltage is not
only used to receive secondary feedback signal to
determine gate on-time, but also determines PFC stage
operating mode.
tOFF-MIN
DET
10
0.3V
IDET
+
VDET
+
RDET
VAUX
RA
FAN6920MR
-
Figure 41. Valley Detection
Start to
Idet flow out
detect valley from DET pin
VAUX
0V
Delay time and
then trigger
gate signal
VDET
Valley
switching
0V
OPWM
tOFF
Figure 42. Measured Waveform of Valley Detection
High / Low Line Over-Power Compensation (DET Pin)
2.25ms
PFC On
PFC Burst
Mode
20.5µs
VCTRL-PFC
ΔVCTRL
5µs
1.2V(VG)
2.1V(VN)
VFB
Figure 40. VFB Voltage vs. tOFF-MIN Time
Characteristic Curve
Valley Detection (DET Pin)
When FAN6920MR operates in Green Mode, tOFF-MIN is
determined by the Green Mode circuit, according to the
FB pin voltage level. After tOFF-MIN, the internal valleydetection circuit is activated. During tOFF of the PWM
switch, when transformer inductor current discharges to
zero, the transformer inductor and parasitic capacitor of
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
Generally, when the power switch turns off, there is a
delay from gate signal falling edge to power switch off.
This delay is produced by an internal propagation delay
of the controller and the turn-off delay of the PWM
switch due to gate resistor and gate-source capacitor
CISS. At different AC input voltages, this delay produces
different maximum output power with the same PWM
current limit level. Higher input voltage generates higher
maximum output power because applied voltage on
primary winding is higher and causes higher rising slope
inductor current. It results in higher peak inductor
current at the same delay. Furthermore, under the same
output wattage, the peak switching current at high line is
lower than that at low line. Therefore, to make the
maximum output power close at different input voltages,
the controller needs to regulate VLIMIT voltage of the
CSPWM pin to control the PWM switch current.
Referring to Figure 43, during tON of the PWM switch,
the input voltage is applied to primary winding and the
voltage across on auxiliary winding VAUX is proportional
to primary winding voltage. As the input voltage
increases, the reflected voltage on auxiliary winding
FAN6920MR —mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
VDD-ON
www.fairchildsemi.com
20
As the input voltage increases, the reflected voltage on
the auxiliary winding VAUX becomes higher as well as
the current IDET and the controller regulates the VLIMIT to
a lower level.
The RDET resistor is connected from auxiliary winding to
the DET pin. Engineers can adjust this RDET resistor to
get proper VLIMIT voltage to fit the specification of overpower or over-current protection. The characteristic
curve of IDET current vs. VLIMIT voltage on CSPWM pin is
shown in Figure 44.
I DET VIN N A N P RDET
(1)
where VIN is input voltage; NA is turn number of
auxiliary winding; and NP is turn number of primary
winding.
VAUX
0V
VDET
VAUX= -[VIN*(Na/Np)]
0V
tON
tOFF
Figure 43. Relationship between VAUX and VIN
Protection for PWM Stage
VDD Pin Over-Voltage Protection (OVP)
VDD over-voltage protection prevents device damage
once VDD voltage is higher than device stress rating
voltage. In the case of VDD OVP, the controller stops all
switching operation immediately and enters autorecovery protection.
Adjustable Over-Temperature Protection and
Externally Protection Triggering (RT Pin)
Figure 45 is a typical application circuit with an internal
block of RT pin. As shown, a constant current IRT flows
out from the RT pin, so the voltage VRT on the RT pin
can be obtained as IRT current multiplied by the resistor,
which consists of NTC resistor and RA resistor. If the RT
pin voltage is lower than 0.8 V and lasts for a debounce
time, auto-recovery protection is activated and stops all
PFC and PWM switching.
Generally, the external protection triggering needs to
activate rapidly since it is usually used to protect the
power system from abnormal conditions. Therefore, the
protection debounce time of the RT pin is set to around
110 µs once the RT pin voltage is lower than 0.5 V.
For over-temperature protection,
because the
temperature does not change immediately; the RT pin
voltage is reduced slowly as well. The debounce time
for adjustable OTP should not need a fast reaction. To
prevent improper protection triggering on the RT pin due
to exacting test condition (e.g. lightning test); when the
RT pin triggering voltage is higher than 0.5 V, the
protection debounce time is set to around 10 ms. To
avoid improper triggering on the RT pin, add a small
value capacitor (e.g. 1000 pF) paralleled with NTC and
the RA resistor.
900
800
700
VLIMIT(mV)
When the PFC or PWM switches are turned on, a
voltage spike is induced on the current-sense resistor
due to the reciprocal effect by reverse-recovery energy
of the output diode and COSS of power MOSFET. To
prevent this spike, a leading-edge blanking time is builtin and a small RC filter (e.g. 100 Ω, 470 pF) is
recommended between the CSPWM pin and GND.
RT pin is usually used to achieve over-temperature
protection with a NTC resistor and provide external
protection triggering for additional protection. Engineers
can use an external triggering circuit (e.g. transistor) to
pull the RT pin low and activate controller auto-recovery
protection.
DET pin voltage is clamped
during tON period.
OPWM
Leading-Edge Blanking (LEB)
600
500
400
FAN6920MR
Adjustable Over-Temperature Protection
and External Protection Triggering
IRT=100µA
300
0
100
200
300
400
500
600
IDET(µA)
12
Figure 44. IDET Current vs. VLIMIT Voltage
Characteristic Curve
NTC
RRT
RT
0.8V
0.5V
AutoRecovery
Protection
Debounce
Time
100µs
10ms
Figure 45. Adjustable Over-Temperature Protection
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
FAN6921 —mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
VAUX becomes higher as well. FAN6920MR also clamps
the DET pin voltage and flows out current IDET. Since the
current IDET is in accordance with VAUX voltage,
FAN6920MR depends on this current during tON to
regulate the current limit level of the PWM switch to
perform high / low line over-power compensation.
www.fairchildsemi.com
21
Referring to Figure 46, during the discharge time of
PWM transformer inductor; the voltage across on
auxiliary winding is reflected from secondary winding
and therefore the flat voltage on the DET pin is
proportional to the output voltage. FAN6920MR can
sample this flat voltage level after a tOFF blanking time to
perform output over-voltage protection. This tOFF
blanking time is used to ignore the voltage ringing from
leakage inductance of PWM transformer. The sampling
flat voltage level is compared with internal threshold
voltage 2.5 V and, once the protection is activated,
FAN6920MR enters auto-recovery protection.
The controller can protect rapidly by this kind of cycleby-cycle sampling method in the case of output over
voltage. The protection voltage level can be determined
by the ratio of external resistor divider RA and RDET. The
flat voltage on DET pin can be expressed by the
following equation:
VDET N A N S VO
RA
RDET RA
(2)
VO
t
NA
NS
t
PFC _ VO
VDET
VO
NA
NP
NA
RA
N S RDET R A
FB
Open-Loop
Short Circuit / Overload
Figure 47. FB Pin Open-Loop, Short Circuit,
and Overload Protection
Referring to Figure 47; outside of FAN6920MR, the FB
pin is connected to the collector of transistor of an optocoupler. Inside, the FB pin is connected to an internal
voltage bias through a resistor of around 5 k.
As the output loading is increased, the output voltage is
decreased and the sink current of the transistor of the
opto-coupler on primary side is reduced. The FB pin
voltage is increased by internal voltage bias. In the case
of an open loop, output short-circuit, or overload
condition; this sink current is further reduced and the FB
pin voltage is pulled HIGH by internal bias voltage.
When the FB pin voltage is higher than 4.2 V for 50 ms,
the FB pin protection is activated.
PWM
Gate
VAUX
VO
Sampling
Here
Under-Voltage Lockout (UVLO, VDD Pin)
Referring to Figure 38 and Figure 39, the turn-on and
turn-off VDD threshold voltages are fixed at 18 V and
10 V, respectively. During startup, the hold-up capacitor
(VDD capacitor) is charged by HV startup current until
VDD voltage reaches the turn-on voltage. Before the
output voltage rises to rated voltage and delivers energy
to the VDD capacitor from auxiliary winding, this hold-up
capacitor must sustain the VDD voltage energy for
operation. When VDD voltage reaches turn-on voltage,
FAN6920MR starts all switching operation if no
protection is triggered before VDD voltage drops to turnoff voltage VDD-PWM-OFF.
tOFF
Blanking
0.3V
t
Figure 46. Operation Waveform of Output
Over-Voltage Detection
© 2010 Fairchild Semiconductor Corporation
FAN6920MR • Rev. 1.0.8
FAN6920MR —mWSaver™ Technology Integrated Critical-Mode PFC and Quasi-Resonant Current-Mode PWM Controller
Open-Loop, Short-Circuit, and Overload Protection
(FB Pin)
Output Over-Voltage Protection (DET Pin)
www.fairchildsemi.com
22
10.00
9.80
8.89
16
A
8.89
9
1.75
B
6.00
4.00
3.80
1
PIN #1
(0.30)
0.51
1.27 0.31
3.85
7.35
8
0.25
1.27
0.65
LAND PATTERN RECOMMENDATION
C B A
TOP VIEW
1.75 MAX
1.50
1.25
SEE DETAIL A
0.25
0.05
C
FRONT VIEW
0.50
0.25
R0.10
GAGE PLANE
R0.10
0.90
0.50
0.36
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
0.10 C
0.25
0.19
NOTES:
A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AC, ISSUE C.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS ARE EXCLUSIVE OF BURRS,
MOLD FLASH AND TIE BAR PROTRUSIONS
D) CONFORMS TO ASME Y14.5M-2009
E) LANDPATTERN STANDARD:
SOIC127P600X175-16AM
F) DRAWING FILE NAME: M16AREV13.
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