FAN6921MRMY

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Integration provides cost effect design and allows for fewer external components. Integrated PFC and Flyback Controller Critical Mode PFC Controller Zero-Current Detection for PFC Stage Quasi-Resonant Operation for PWM Stage Internal Minimum tOFF 8 µs for QR PWM Stage Internal 10 ms Soft-Start for PWM Brownout Protection High / Low Line Over-Power Compensation Auto-Recovery Over-Current Protection Auto-Recovery Open-Loop Protection Externally Latch Triggering (RT Pin) Adjustable Over-Temperature Latched (RT Pin) VDD Pin and Output Voltage OVP (Latched) Internal Over-Temperature Shutdown (140°C) Applications    For PFC, FAN6921MR uses a controlled on-time technique to provide a regulated DC output voltage and to perform natural power factor correction. With an innovative THD optimizer, FAN6921MR can reduce input current distortion at zero-crossing duration to improve THD performance. For PWM, FAN6921MR provides several functions to enhance the power system performance: valley detection, green-mode operation, high / low line over power compensation. FAN6921MR provides many protection functions as well: secondary-side open-loop and over-current with auto recovery protection, external latch triggering, adjustable over-temperature protection by RT pin and external NTC resistor, internal overtemperature shutdown, VDD pin OVP, and DET pin overvoltage for output OVP, and brown-in / out for AC input voltage UVP. The FAN6921MR controller is available in a 16-pin small outline package (SOP). AC/DC NB Adapters Open-Frame SMPS Battery Charger Ordering Information Part Number OLP Mode Operating Temperature Range Package Packing Method FAN6921MRMY Recovery -40°C to +105°C 16-Pin Small Outline Package (SOP) Tape & Reel © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.4 www.fairchildsemi.com FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Current Mode PWM Controller February 2013 Figure 1. Typical Application © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.4 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller Application Diagram www.fairchildsemi.com 2 Figure 2. Functional Block Diagram © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.4 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller Internal Block Diagram www.fairchildsemi.com 3 Figure 3. Marking Diagram Pin Configuration Figure 4. Pin Configuration Pin Definitions Pin # Name Description 1 RANGE RANGE pin’s impedance changes according to VIN pin voltage level. When the input voltage detected by VIN pin is lower than a threshold voltage, it sets to high impedance; whereas it sets to low impedance if input voltage is high level. 2 COMP Output pin of the error amplifier. It is a transconductance type error amplifier for PFC output voltage feedback. Proprietary multi-vector current is built-in to this amplifier. Therefore the compensation for PFC voltage feedback loop allows a simple compensation circuit between this pin and GND. 3 INV 4 CSPFC 5 Input to the comparator of the PWM over-current protection and performs PWM current-mode control with FB pin voltage. A resistor is used to sense the switching current of PWM switch and CSPWM the sensing voltage is applied to the CSPWM pin for the cycle-by-cycle current limit, currentmode control, and high / low line over-power compensation according to DET pin source current during PWM tON time. FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller Marking Information Inverting input of the error amplifier. This pin is used to receive PFC voltage level by a voltage divider and provides PFC output over- and under-voltage protections. Input to the PFC over-current protection comparator that provides cycle-by-cycle current limiting protection. When the sensed voltage across the PFC current sensing resistor reaches the internal threshold (0.82 V typical), the PFC switch is turned off to activate cycle-by-cycle current limiting. Continued on the following page… © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.4 www.fairchildsemi.com 4 Pin # Name Description 6 OPFC Totem-pole driver output to drive the external power MOSFET. The clamped gate output voltage is 15.5 V. 7 VDD Power supply. The threshold voltage for startup and turn-off is 18 V and 7.5 V, respectively. The startup current is less than 30μA and the operating current is lower than 10 mA. 8 OPWM 9 GND The power ground and signal ground. DET This pin is connected to an auxiliary winding of the PWM transformer through a resistor divider for the following purposes:  Producing an offset voltage to compensate the threshold voltage of PWM current limit for providing over-power compensation. The offset is generated in accordance with the input voltage when PWM switch is on.  Detecting the valley voltage signal of drain voltage of the PWM switch to achieve the valley voltage switching and minimize the switching loss on PWM switch.  Providing output over-voltage protection. A voltage comparator is built-in to the DET pin. The DET pin detects the flat voltage through a voltage divider paralleled with auxiliary winding. This flat voltage is reflected to the secondary winding during PWM inductor discharge time. If output OVP and this flat voltage is higher than 2.5 V, the controller enters latch mode and stops all PFC and PWM switching operation. 11 FB Feedback voltage pin. This pin is used to receive output voltage level signal to determine PWM gate duty for regulating output voltage. The FB pin voltage can also activate open-loop, over-load protection, and output-short circuit protection if the FB pin voltage is higher than a threshold of around 4.2 V for more than 50 ms.The input impedance of this pin is a 5 kΩ equivalent resistance. A 1/3 attenuator is connected between the FB pin and the input of the CSPWM/FB comparator. 12 RT Adjustable over-temperature protection and external latch triggering. A constant current is flowed out of the RT pin. When RT pin voltage is lower than 0.8 V (typical), latch mode protection is activated and stops all PFC and PWM switching operation until the AC plug is removed. 13 VIN Line-voltage detection for brown-in / out protections. This pin can receive the AC input voltage level through a voltage divider. The voltage level of the VIN pin is not only used to control RANGE pin’s status, but it can also perform brown-in / out protection for AC input voltage UVP. 14 ZCD Zero-current detection for the PFC stage. This pin is connected to an auxiliary winding coupled to PFC inductor winding to detect the ZCD voltage signal once the PFC inductor current discharges to zero. When the ZCD voltage signal is detected, the controller starts a new PFC switching cycle. When the ZCD pin voltage is pulled to under 0.2 V (typical), it disables the PFC stage and the controller stops PFC switching. This can be realized with an external circuit if disabling the PFC stage is desired. 15 NC No connection 16 HV High-voltage startup. HV pin is connected to the AC line voltage through a resistor (100 kΩ typical) for providing a high charging current to VDD capacitor. 10 Totem-pole output generates the PWM signal to drive the external power MOSFET. The clamped gate output voltage is 17.5 V. © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.4 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller Pin Definitions (Continued) www.fairchildsemi.com 5 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD Parameter Min. DC Supply Voltage Max. Unit 30 V VHV HV 500 V VH OPFC, OPWM -0.3 25.0 V VL Others (INV, COMP, CSPFC, DET, FB, CSPWM, RT) -0.3 7.0 V Input Voltage to ZCD Pin -0.3 12.0 V VZCD Power Dissipation 800 mW θJA PD Thermal Resistance (Junction-to-Air) 104 °C/W θJC Thermal Resistance (Junction-to-Case) TJ TSTG TL 41 °C/W Operating Junction Temperature -40 +150 °C Storage Temperature Range -55 +150 °C +260 °C Lead Temperature (Soldering 10 Seconds) (3) ESD Human Body Model, JESD22-A114 (All Pins Except HV Pin) 4500 Charged Device Model, JESD22-C101 (All Pins Except HV Pin)(3) 1250 V Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 2. All voltage values, except differential voltages, are given with respect to GND pin. 3. All pins including HV pin: CDM=750 V, HBM 1000 V. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperature © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.4 Min. Max. Unit -40 +105 °C FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller Absolute Maximum Ratings www.fairchildsemi.com 6 VDD=15 V, TA=-40°C~105°C (TA=TJ), unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units 25 V 19.5 V VDD Section VOP Continuously Operating Voltage VDD-ON Turn-On Threshold Voltage 16.5 VDD-PWM-OFF PWM Off Threshold Voltage 9 10 11 V VDD-OFF Turn-Off Threshold Voltage 6.5 7.5 8.5 V 20 30 µA 10 mA IDD-ST Startup Current VDD=VDD-ON - 0.16 V, Gate Open IDD-OP Operating Current VDD=15 V, OPFC, OPWM=100 kHz, CL-PFC, CL-PWM=2 nF IDD-GREEN Green-Mode Operating Supply Current (Average) VDD=15 V, OPWM=450 Hz, CL-PWM=2 nF IDD-PWM-OFF Operating Current at PWM-Off Phase VDD=VDD-PWM-OFF - 0.5 V 18.0 5.5 mA 70 120 170 µA VDD-OVP VDD Over-Voltage Protection (Latch-Off) 26.5 27.5 28.5 V tVDD-OVP VDD OVP Debounce Time 100 150 200 µs IDD-LATCH VDD Over-Voltage Protection Latch-Up Holding Current VDD=7.5 V 120 µA HV Startup Current Source Section VHV-MIN IHV Minimum Startup Voltage on HV Pin Supply Current Drawn from HV Pin 50 VAC=90 V (VDC=120 V), VDD=0 V 1.3 HV=500 V, VDD= VDD-OFF +1 V V mA 1 µA VIN and RANGE Section VVIN-UVP Threshold Voltage for AC Input Under-Voltage Protection 0.95 1.00 1.05 V VVIN-RE-UVP Under-Voltage Protection Reset Voltage (for Startup) VVIN-UVP +0.25V VVIN-UVP +0.30V VVIN-UVP +0.35V V 70 100 130 ms tVIN-UVP Under-Voltage Protection Debounce Time (No Need at Startup and Hiccup Mode) VVIN-RANGE-H High VVIN Threshold for RANGE Comparator 2.40 2.45 2.50 V VVIN-RANGE-L Low VVIN Threshold for RANGE Comparator 2.05 2.10 2.15 V 70 100 130 ms tRANGE Range-Enable/ Disable Debounce Time VRANGE-OL Output Low Voltage of RANGE Pin IO=1 mA 0.5 V IRANGE-OH Output High Leakage Current of RANGE Pin RANGE=5 V 50 nA PFC Maximum On Time RMOT=24 kΩ 28 µs tON-MAX-PFC 22 25 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller Electrical Characteristics Continued on the following page… © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.4 www.fairchildsemi.com 7 VDD=15 V, TA=-40°C ~105°C (TA=TJ), unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units 100 125 150 µmho 2.465 2.500 2.535 V PFC Stage Voltage Error Amplifier Section Gm Transconductance(4) VREF Feedback Comparator Reference Voltage VINV-H Clamp High Feedback Voltage VRATIO VINV-L (4) Clamp High Output Voltage Ratio RANGE=Open 2.70 2.75 2.80 RANGE=Ground 2.60 2.65 2.70 VINVH / VREF, RANGE=Open 1.06 1.14 VINVH / VREF, RANGE=Ground 1.04 1.08 Clamp Low Feedback Voltage V V/V 2.35 2.45 RANGE=Open 2.25 2.90 2.95 V RANGE=Ground 2.75 2.80 50 70 90 µs 0.35 0.45 0.55 V 50 70 90 µs VINV-OVP Over-Voltage Protection for INV Input tINV-OVP Over-Voltage Protection Debounce Time VINV-UVP Under-Voltage Protection for INV Input tINV-UVP Under-Voltage Protection Debounce Time VINV-BO PWM and PFC Off Threshold for Brownout Protection 1.15 1.20 1.25 V VCOMP-BO Limited Voltage on COMP Pin for Brownout Protection 1.55 1.60 1.65 V VCOMP Comparator Output High Voltage 4.8 6.0 V Zero Duty Cycle Voltage on COMP Pin 1.10 1.25 1.40 V 15 30 45 µA 0.50 0.75 1.00 mA RANGE=Open, VINV=2.75 V, VCOMP=5 V 20 30 40 RANGE=Ground, VINV=2.65 V, VCOMP=5 V 20 30 40 VOZ Comparator Output Source Current ICOMP Comparator Output Sink Current VINV=2.3 V, VCOMP=1.5 V VINV=1.5 V V µA PFC Current Sense Section VCSPFC Threshold Voltage for Peak Current Cycle-by-Cycle Limit tPD Propagation Delay tBNK Leading-Edge Blanking Time AV CSPFC Compensation Ratio for THD VCOMP=5 V 0.82 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller Electrical Characteristics (Continued) V 110 200 ns 110 180 250 ns 0.90 0.95 1.00 V/V Continued on the following page… © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.4 www.fairchildsemi.com 8 VDD=15 V, TA=-40°C ~105°C (TA=TJ), unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units 14.0 15.5 17.0 V 1.5 V PFC Output Section VZ PFC Gate Output Clamping Voltage VDD= 25 V VOL PFC Gate Output Voltage Low VDD=15 V, IO=100 mA VOH PFC Gate Output Voltage High VDD=15 V, IO=100 mA 8 tR PFC Gate Output Rising Time VDD=12 V, CL=3 nF, 20~80% 30 65 100 ns tF PFC Gate Output Falling Time VDD=12 V, CL=3 nF, 80~20% 30 50 70 ns Input Threshold Voltage Rising Edge VZCD Increasing 1.9 2.1 2.3 V Threshold Voltage Hysteresis VZCD Decreasing 0.25 0.35 0.45 V VZCD-HIGH Upper Clamp Voltage IZCD=3 mA 8 10 VZCD-LOW Lower Clamp Voltage 0.40 0.65 0.90 V VZCD-SSC Starting Source Current Threshold Voltage 1.3 1.4 1.5 V 200 ns V PFC Zero Current Detection Section VZCD VZCD-HYST tDELAY tRESTART-PFC Maximum Delay from ZCD to Output Turn-On VCOMP=5 V, fS=60 kHz 100 V Restart Time 300 500 700 µs Inhibit Time (Maximum Switching VCOMP=5 V Frequency Limit) 1.5 2.5 3.5 µs VZCD-DIS PFC Enable/ Disable Function Threshold Voltage 0.15 0.2 0.25 V tZCD-DIS PFC Enable/ Disable Function Debounce Time 100 150 200 µs tINHIB VZCD=100 mV Continued on the following page… © 2009 Fairchild Semiconductor Corporation FAN6921MR Rev. 1.0.4 FAN6921MR — Integrated Critical Mode PFC and Quasi-Resonant Flyback PWM Controller Electrical Characteristics (Continued) www.fairchildsemi.com 9 VDD=15 V, TA=-40°C ~105°C (TA=TJ), unless otherwise specified. Symbol Parameter Conditions Min. Typ. Max. Units 1/2.75 1/3.00 1/3.25 V/V 3 5 7 kΩ 1.2 2.0 mA PWM STAGE Feedback Input Section AV Input-Voltage to Current Sense Attenuation(4) AV=△VCSPWM /△VFB, 0