FAN73833M

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This literature is subject to all applicable copyright laws and is not for resale in any manner. FAN73833 Half-Bridge Gate-Drive IC Features Description  Floating Channel for Bootstrap Operation to +600V The FAN73833 is a half-bridge gate-drive IC for driving MOSFETs and IGBTs, operating up to +600 V.  Typically 350 mA / 650 mA Sourcing/Sinking Current Driving Capability for Both Channels  Extended Allowable Negative VS Swing to -9.8 V for Signal Propagation at VDD=VBS=15 V  3.3 V and 5 V Input Logic Compatible An advanced level-shift circuit allows high-side gate driver operation up to VS=-9.8 V (typical) for VBS=15 V.  Outputs in Phase with Input Signals  Built-in UVLO Functions for Both Channels  Built-on Shoot-Through Prevention Circuit  Built-in Common-Mode dv/dt Noise Canceling Circuit  Internal Dead-Time Typically 400 ns Applications Fairchild’s high-voltage process and common-mode noise canceling technique provide stable operation of high-side driver under high dv/dt noise circumstances. The UVLO circuits for both channels prevent malfunction when VDD and VBS are lower than the specified threshold voltage. Output drivers typically source/sink 350 mA / 650 mA, respectively, which is suitable for all kinds of half- and full-bridge inverters.  SMPS  Motor Drive Inverter 8-SOP  Fluorescent Lamp Ballast  HID Ballast Ordering Information Part Number FAN73833M FAN73833MX Package Operating Temperature Range 8-SOP -40°C to +125°C © 2008 Fairchild Semiconductor Corporation FAN73833 • Rev. 1.0.2 Packing Method Tube Tape & Reel www.fairchildsemi.com FAN73833 — Half-Bridge Gate-Drive IC October 2012 FAN73833 — Half-Bridge Gate-Drive IC Typical Application Circuit RBOOT Up to 600V DBOOT VDD LIN 1 LIN VB 8 HIN 2 HIN HO 7 3 VDD VS 6 CBOOT 4 COM Load LO 5 Figure 1. Application Circuit for Half-Bridge Internal Block Diagram 8 VB 7 HO 6 VS 3 VDD 5 LO 4 COM UVLO HIN R S Q HS(ON/OFF) 2 UVLO 100K SHOOT-THROUGH PREVENTION LS(ON/OFF) 1 100K DELAY DEAD-TIME { 400ns } DRIVER LIN DRIVER PULSE GENERATOR SCHMITT TRIGGER INPUT R NOISE CANCELLER Figure 2. Functional Block Diagram © 2008 Fairchild Semiconductor Corporation FAN73833 • Rev.1.0.2 www.fairchildsemi.com 2 FAN73833 — Half-Bridge Gate-Drive IC Pin Configuration 1 HIN 2 VDD 3 COM 4 FAN73833 LIN 8 VB 7 HO 6 VS 5 LO Figure 3. Pin Configuration (Top View) Pin Definitions Pin # Name Description 1 LIN Logic Input for Low-Side Driver 2 HIN Logic Input for High-Side Driver 3 VDD Low-Side Supply Voltage 4 COM Logic Ground and Low-Side Driver Return 5 LO Low-Side Driver Output 6 VS High-Side Floating Supply Return 7 HO High-Side Driver Output 8 VB High-Side Floating Supply © 2008 Fairchild Semiconductor Corporation FAN73833 • Rev.1.0.2 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified. Symbol Parameter VS High-side offset voltage VB High-side floating supply voltage Min. Max. Unit VB-25 VB+0.3 V -0.3 625 V VS-0.3 VB+0.3 V VHO High-side floating output voltage HO VDD Low-side and logic-fixed supply voltage -0.3 25 V VLO Low-side output voltage LO -0.3 VDD+0.3 V VIN Logic input voltage (HIN/LIN) -0.3 VDD+0.3 V VDD-25 VDD+0.3 V COM Logic ground and low-side driver return dVS/dt Allowable offset voltage slew rate PD(1)(2)(3) Power dissipation 50 V/ns 0.625 W JA Thermal resistance, junction-to-ambient 200 C/W TJ Junction temperature 150 C TSTG Storage temperature 150 C -55 Notes: 1. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR-4 glass epoxy material). 2. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages 3. Do not exceed PD under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter Min. Max. Unit VB High-side floating supply voltage VS+11 VS+20 V VS High-side floating supply offset voltage 6-VDD 600 V VDD Low-side supply voltage 11 20 V VHO High-side (HO) output voltage VS VB V VLO Low-side (LO) output voltage COM VDD V VIN Logic input voltage (HIN/LIN) COM VDD V TA Ambient temperature -40 125 C © 2008 Fairchild Semiconductor Corporation FAN73833 • Rev.1.0.2 www.fairchildsemi.com 4 FAN73833 — Half-Bridge Gate-Drive IC Absolute Maximum Ratings VBIAS (VDD, VBS) = 15.0 V, andTA=25C, unless otherwise specified. The VIN and IIN parameters are referenced to COM. The VO and IO parameters are referenced to VS and COM and are applicable to respective outputs HO and LO. Symbol Parameter Condition Min. Typ. Max. Unit SUPPLY CURRENT SECTION IQBS Quiescent VBS supply current VIN=0 V or 5 V 35 100 µA IQDD Quiescent VDD supply current VIN=0 V or 5 V 80 200 µA IPBS Operating VBS supply current fIN=20 kHz, rms value 420 750 µA IPDD Operating VDD supply current fIN=20 kHz, rms value 420 750 µA ILK Offset supply leakage current VB=VS=600 V 10 µA POWER SUPPLY SECTION VDDUV+ VBSUV+ VDD and VBS supply under-voltage  positive going threshold 8.2 9.2 10.1 V VDDUVVBSUV- VDD and VBS supply under-voltage  negative going threshold 7.2 8.3 9.2 V VDDUVH VBSUVH VDD supply under-voltage lockout  hysteresis 0.9 V GATE DRIVER OUTPUT SECTION VOH High-level output voltage, VBIAS-VO VOL Low-level output voltage, VO IO+(4) IO-(4) VS IO=20 mA 1.0 V 0.6 V Output high short-circuit pulse current VO=0 V, VIN=5 V with PW