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FAN7388
3 Half-Bridge Gate-Drive IC
Features
Description
Floating Channel for Bootstrap Operation to +600 V
The FAN7388 is a monolithic three half-bridge gate-drive
IC designed for high-voltage, high-speed driving MOSFETs and IGBTs operating up to +600 V.
Typically 350 mA / 650 mA Sourcing/Sinking Current
Driving Capability for All Channels
3 Half-Bridge Gate Driver
Extended Allowable Negative VS Swing to -9.8 V for
Signal Propagation at VBS=15 V
Matched Propagation Delay Time Maximum: 50 ns
3.3 V and 5 V Input Logic Compatible
Built-in Shoot-Through Prevention Circuit for All
Channels with 270 ns Typical Dead Time
Built-in Common Mode dv/dt Noise Canceling Circuit
Built-in UVLO Functions for All Channels
Applications
Fairchild’s high-voltage process and common-mode
noise canceling technique provide stable operation of
high-side drivers under high-dv/dt noise circumstances.
An advanced level-shift circuit allows high-side gate
driver operation up to VS=-9.8 V (typical) for VBS=15 V.
The UVLO circuits prevent malfunction when VDD and
VBS are lower than the specified threshold voltage.
Output drivers typically source/sink 350 mA / 650 mA,
respectively, which is suitable for three-phase half-bridge
applications in motor drive systems.
3-Phase Motor Inverter Driver
Related Resources
20-SOIC
AN-6076 - Design and Application Guide of Bootstrap
Circuit for High-Voltage Gate-Drive IC
AN-9052 - Design Guide for Selection of Bootstrap
Components
AN-8102 - Recommendations to Avoid Short Pulse
Width Issues in HVIC Gate Driver Applications
Ordering Information
Part Number
Package
Operating
Temperature Range
Packing Method
FAN7388MX
20-SOIC
-40°C to +125°C
Tape & Reel
© 2008 Fairchild Semiconductor Corporation
FAN7388 • Rev. 1.3
www.fairchildsemi.com
FAN7388 — 3 Half-Bridge Gate-Drive IC
April 2016
+15V
Up to 600V
1
HIN1
VB1
20
UL
2
LIN1
HO1
19
VU
3-Phase
BLDC Motor
Controller VL
3
HIN2
VS1
18
VS1
4
LIN2
LO1
17
Q1
Q3
WU
5
HIN3
VB2
16
Q5
WL
6
LIN3
HO2
15
7
LO3
VS2
14
8
VS3
9
HO3
10
VB3
FAN7388
UU
Q1
Q3
Q5
IU
VS1
U
3-Phase Inverter
VS2
IV
VS2
V
W
Q4
LO2
13
Q6
Q2
VS3
IW
VDD 12
Q4
GND 11
Q6
Q2
VS3
FAN7388 Rev.00
Figure 1. 3-Phase BLDC Motor Drive Application
Internal Block Diagram
VB1
UVLO
HIN1
NOISE
CANCELLER
VDD_UVLO
R R
S
Q
VS1
VDD
ULIN
DELAY
HIN3
VDD
DRIVER
SCHMITT
TRIGGER INPUT
LO1
GND
U Phase Driver
SHOOT-THOUGH
PREVENTION
VB2
VDD
LIN2
V Phase Driver
VHIN
VLIN
LIN3
HO1
UVLO
HIN2
LIN1
DRIVER
PULSE
GENERATOR
UHIN
HO2
VS2
LO2
CONTROL LOGIC
VB3
VDD
W Phase Driver
WHIN
WLIN
HO3
VS3
LO3
FAN7388 Rev.01
Figure 2. Functional Block Diagram
© 2008 Fairchild Semiconductor Corporation
FAN7388 • Rev.1.3
www.fairchildsemi.com
2
FAN7388 — 3 Half-Bridge Gate-Drive IC
Typical Application Circuit
FAN7388 — 3 Half-Bridge Gate-Drive IC
Pin Configuration
HIN1 1
20 VB1
LIN1 2
19 HO1
HIN2 3
18 VS1
HIN3 5
LIN3 6
LO3 7
VS3
FAN7388
LIN2 4
17 LO1
16 VB2
15 HO2
14 VS2
13 LO2
8
HO3 9
12 VDD
11 GND
VB3 10
FAN7388 Rev.00
Figure 3. Pin Configuration (Top View)
Pin Definitions
Pin #
Name
Description
1
HIN1
Logic input 1 for high-side gate 1 driver
2
LIN1
Logic input 1 for low-side gate 1 driver
3
HIN2
Logic input 2 for high-side gate 2 driver
4
LIN2
Logic input 2 for low-side gate 2 driver
5
HIN3
Logic input 3 for high-side gate 3 driver
6
LIN3
Logic input 3 for low-side gate 3 driver
7
LO3
Low-side gate driver 3 output
8
VS3
High-side driver 3 floating supply offset voltage
9
HO3
High-side driver 3 gate driver output
10
VB3
High-side driver 3 floating supply voltage
11
GND
Ground
12
VDD
Logic and all low-side gate drivers power supply voltage
13
LO2
Low-side gate driver 2 output
14
VS2
High-side driver 2 floating supply offset voltage
15
HO2
High-side driver 2 gate driver output
16
VB2
High-side driver 2 floating supply voltage
17
LO1
Low-side gate driver 1 output
18
VS1
High-side driver 1 floating supply offset voltage
19
HO1
High-side driver 1 gate driver output
20
VB1
High-side driver 1 floating supply voltage
© 2008 Fairchild Semiconductor Corporation
FAN7388 • Rev.1.3
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The
absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified.
Symbol
Parameter
Min.
Max.
Unit
-0.3
625.0
V
VB
High-Side Floating Supply Voltage of VB1,2,3
VS
High-Side Floating Supply Offset Voltage of VS1,2,3
VB1,2,3-25
VB1,2,3+0.3
V
High-Side Floating Output Voltage
VS1,2,3-0.3
VB1,2,3+0.3
V
VHO1,2,3
VDD
VLO1,2,3
VIN
dVS/dt
Low-Side and Logic-fixed Supply Voltage
-0.3
25.0
V
Low-Side Output Voltage
-0.3
VDD+0.3
V
Logic Input Voltage (HIN1,2,3 and LIN1,2,3)
-0.3
VDD+0.3
V
50
V/ns
Allowable Offset Voltage Slew Rate
Dissipation(1)(2)(3)
PD
Power
JA
Thermal Resistance, Junction-to-ambient
TJ
Junction Temperature
TSTG
Storage Temperature
-55
1.47
W
85
C/W
+150
C
+150
C
Notes:
1. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR-4 glass epoxy material).
2. Refer to the following standards:
JESD51-2: Integral circuits thermal test method environmental conditions - natural convection
JESD51-3: Low effective thermal conductivity test board for leaded surface-mount packages.
3. Do not exceed PD under any circumstances.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
Parameter
VB1,2,3
High-Side Floating Supply Voltage
VS1,2,3
High-Side Floating Supply Offset Voltage
VDD
Supply Voltage
Min.
Max.
Unit
VS1,2,3+10
VS1,2,3+20
V
6-VDD
600
V
10
20
V
VHO1,2,3
High-Side Output Voltage
VS1,2,3
VB1,2,3
V
VLO1,2,3
Low-Side Output Voltage
GND
VDD
V
VIN
Logic Input Voltage (HIN1,2,3 and LIN1,2,3)
GND
VDD
V
TA
Ambient Temperature
-40
+125
°C
© 2008 Fairchild Semiconductor Corporation
FAN7388 • Rev.1.3
www.fairchildsemi.com
4
FAN7388 — 3 Half-Bridge Gate-Drive IC
Absolute Maximum Ratings
VBIAS (VDD, VBS1,2,3)=15.0 V, TA=25C, unless otherwise specified. The VIN and IIN parameters are referenced to
GND. The VO and IO parameters are referenced to GND and VS1,2,3 and are applicable to the respective outputs
LO1,2,3 and HO1,2,3.
Symbol
Characteristics
Condition
Min. Typ. Max. Unit
LOW-SIDE POWER SUPPLY SECTION
IQDD
Quiescent VDD Supply Current
VLIN1,2,3=0 V or 5 V
160
350
µA
IPDD1,2,3
Operating VDD Supply Current for each
Channel
fLIN1,2,3=20 kHz, rms Value
500
900
µA
VDDUV+
VDD Supply Under-Voltage Positive-Going
Threshold
VDD=Sweep, VBS=15 V
7.2
8.2
9.0
V
VDDUV-
VDD Supply Under-Voltage Negative-Going
VDD=Sweep, VBS=15 V
Threshold
6.8
7.8
8.5
V
VDDHYS
VDD Supply Under-Voltage Lockout
Hysteresis
VDD=Sweep, VBS=15 V
0.4
V
BOOTSTRAPPED POWER SUPPLY SECTION
IQBS1,2,3
Quiescent VBS Supply Current for each
Channel
VHIN1,2,3=0 V or 5 V
50
120
µA
IPBS1,2,3
Operating VBS Supply Current for each
Channel
fHIN1,2,3=20 kHz, rms Value
400
800
µA
VBSUV+
VBS Supply Under-Voltage Positive-going
Threshold
VDD=15 V, VBS=Sweep
7.2
8.2
9.0
V
VBSUV-
VBS Supply Under-Voltage Negative-going
Threshold
VDD=15 V, VBS=Sweep
6.8
7.8
8.5
V
VBSHYS
VBS Supply Under-Voltage Lockout
Hysteresis
VDD=15 V, VBS=Sweep
Offset Supply Leakage Current
VB1,2,3=VS1,2,3=600 V
10
µA
ILK
0.4
V
GATE DRIVER OUTPUT SECTION
VOH
High-Level Output Voltage, VBIAS-VO
IO=20 mA
1.0
V
VOL
Low-Level Output Voltage, VO
IO=20 mA
0.6
V
IO+
Output HIGH Short-Circuit Pulsed
Current(4)
VO=0 V, VIN=5 V with PW