FAN73901MX

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It has a buffered output stage with all NMOS transistors designed for high pulse current driving capability and minimum cross-conduction.  Typically 2.5 A / 2.5 A Sourcing/Sinking Current Driving Capability  Common-Mode dv/dt Noise Canceling Circuit  Built-in Under-Voltage Lockout for Both Channels  Matched Propagation Delay for Both Channels  3.3 V and 5 V Input Logic Compatible  Output In-Phase with Input Applications Fairchild’s high-voltage process and common-mode noise canceling techniques provide stable operation of the high-side driver under high dv/dt noise circumstances. An advanced level-shift circuit offers high-side gate driver operation up to VS=-9.8 V (typical) for VBS=15 V. The UVLO circuit prevents malfunction when VDD and VBS are lower than the specified threshold voltage.  Half-Bridge Driver  HID Lamp Ballast  SMPS The high current and low output voltage drop features mak sFAN73901 suitable for switching power supply, motor driver, and high-power DC-DC converter applications.  Motor Driver 8-SOP Ordering Information Part Number FAN73901M FAN73901MX Package Operating Temperature Range 8-SOP -40C ~ 125C © 2008 Fairchild Semiconductor Corporation FAN73901 • Rev. 1.0.1 Packing Method Tube Tape & Reel www.fairchildsemi.com FAN73901 — High- and Low Side, Gate-Drive IC September 2013 FAN73901 — High- and Low Side, Gate-Drive IC Typical Application Circuit 15V FAN73901 RBOOT Up to 600V DBOOT HIN 1 HIN VB 8 LIN 2 LIN HO 7 Controller Q1 R1 CBOOT 3 COM VS 4 LO VDD 5 R2 6 OUTPUT Load C1 Q2 R3 R4 FAN73901 Rev.01 Figure 1. Application Circuit for Half-Bridge Internal Block Diagram FAN73901 8 VB 7 HO 6 VS 5 VDD 4 LO 3 COM UVLO NOISE CANCELLER R S DRIVER 200K PULSE GENERATOR HIN 1 R Q UVLO DRIVER DELAY LIN 2 200K FAN73901 Rev.01 Figure 2. Functional Block Diagram © 2008 Fairchild Semiconductor Corporation FAN73901 • Rev. 1.0.1 www.fairchildsemi.com 2 FAN73901 — High- and Low Side, Gate-Drive IC Pin Configuration HIN 1 8 VB LIN 2 7 HO COM 3 6 VS LO 4 5 VDD FAN73901 FAN73901 Rev.01 Figure 3. Pin Assignments (Top View) Pin Definitions Pin # Name 1 HIN Logic Input for High-Side Gate Driver Output 2 LIN Logic Input for Low-Side Gate Driver Output 3 COM Low-Side Driver Return 4 LO Low-Side Driver Output 5 VDD Low-Side and Logic Part Supply Voltage 6 VS High-Voltage Floating Supply Return 7 HO High-Side Driver Output 8 VB High-Side Floating Supply © 2008 Fairchild Semiconductor Corporation FAN73901 • Rev. 1.0.1 Description www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified. Symbol Characteristics VS High-Side Floating Supply Offset Voltage VB High-Side Floating Supply Voltage Min. Max. Unit VB-25 VB+0.3 V -0.3 625.0 V VS-0.3 VB+0.3 V VHO High-Side Floating Output Voltage HO VDD Low-Side and Logic Fixed Supply Voltage -0.3 25.0 V VLO Low-Side Output Voltage LO -0.3 VDD+0.3 V VIN Logic Input Voltage (HIN and LIN) -0.3 VDD+0.3 V 50 V/ns dVS/dt Allowable Offset Voltage Slew Rate Dissipation(1)(2)(3) PD Power 0.625 W JA Thermal Resistance, Junction-to-Ambient 200 C/W TJ Junction Temperature +150 C TSTG Storage Temperature +150 C Notes: 1. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR-4 glass epoxy material). 2. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages. 3. Do not exceed PD under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Unit VB High-Side Floating Supply Voltage VS+10 VS+20 V VS High-Side Floating Supply Offset Voltage 6-VDD 600 V VHO High-Side Output Voltage VS VB V VDD Low-Side and Logic Supply Voltage 10 20 V VLO Low-Side Output Voltage COM VDD V VIN Logic Input Voltage (HIN and LIN) COM VDD V TA Operating Ambient Temperature -40 +125 C © 2008 Fairchild Semiconductor Corporation FAN73901 • Rev. 1.0.1 www.fairchildsemi.com 4 FAN73901 — High- and Low Side, Gate-Drive IC Absolute Maximum Ratings VBIAS (VDD, VBS)=15.0 V, VS=COM, TA=25C, unless otherwise specified. The VIL, VIH, and IIN parameters are referenced to COM and are applicable to the respective input signals HIN and LIN. The VO and IO parameters are referenced to COM and VS is applicable to the respective output signals HO and LO. Symbol Characteristics Test Condition Min. Typ. Max. Unit POWER SUPPLY SECTION (VDD AND VBS) VDDUV+ VBSUV+ VDD and VBS Supply Under-Voltage Positive-Going Threshold 8.0 8.8 9.8 V VDDUVVBSUV- VDD and VBS Supply Under-Voltage Negative-Going Threshold 7.4 8.3 9.0 V VDDUVH VDD and VBS Supply Under-Voltage VBSUVH Lockout Hysteresis Voltage 0.5 ILK Offset Supply Leakage Current VB=VS=600 V IQBS Quiescent VBS Supply Current VIN=0V or 5 V IQDD Quiescent VDD Supply Current VIN=0V or 5 V IPBS Operating VBS Supply Current fIN=20 kHz, rms value IPDD Operating VDD Supply Current fIN=20 kHz, rms value 530 V 50 µA 80 µA 75 110 µA 530 640 µA 640 µA 45 LOGIC INPUT SECTION (HIN, LIN) VIH Logic "1" Input Voltage 2.5 VIL Logic "0" Input Voltage IIN+ Logic "1" Input Bias Current VIN=5 V IIN- Logic "0" Input Bias Current VIN=0 V RIN Input Pull-Down Resistance 100 V 1.2 V 25 50 µA 1.0 2.0 200 µA K GATE DRIVER OUTPUT SECTION (HO, LO) VOH High-Level Output Voltage, VBIAS-VO No Load 1.0 V VOL Low-Level Output Voltage, VO No Load 35 mV IO+ Output High, Short-Circuit Pulsed Current(4) VO=0 V, VIN=5 V with PW