FAN7390AMX1

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It has a buffered output stage with all NMOS transistors designed for high pulse current driving capability and minimum cross-conduction.  Typically 4.5 A / 4.5 A Sourcing / Sinking Current Driv- ing Capability  Common-Mode dv/dt Noise-Canceling Circuit  Built-in Under-Voltage Lockout for Both Channels  Matched Propagation Delay for Both Channels  Logic (VSS) and Power (COM) Ground ±5V Offset  3.3 V and 5 V Input Logic Compatible  Output In-phase with Input Applications  Plasma Display Panel (PDP) Sustain Driver  High Intensity Discharge (HID) Lamp Ballast  SMPS  Motor Driver Fairchild’s high-voltage process and common-mode noise canceling techniques provide stable operation of the high-side driver under high-dv/dt noise circumstances. An advanced level-shift circuit offers high-side gate driver operation up to VS=-9.8 V (typical) for VBS=15 V. The UVLO circuit prevents malfunction when VDD and VBS are lower than the specified threshold voltage. The high-current and low-output voltage-drop feature make this device suitable for the PDP sustain pulse driver, motor driver, switching power supply, and highpower DC-DC converter applications. 14-SOP Ordering Information Part Number Package Operating Temperature Range Packing Method FAN7390AMX1 14-SOP -40C ~ 125C Tape & Reel  © 2012 Fairchild Semiconductor Corporation FAN7390A Rev. 1.0.0 www.fairchildsemi.com FAN7390A — High-Current, High & Low Side, Gate-Drive IC October 2012 15V RBOOT DBOOT FAN7390A Up to 600V HIN 1 HIN NC 14 LIN 2 LIN VB 3 VSS HO 12 4 NC VS 5 COM NC 10 6 LO NC 9 7 VDD NC 8 Controller VSS 13 Q1 R1 R2 CBOOT 11 OUTPUT Load C1 Q2 R3 R4 FAN7390A Rev.04 Figure 1. Application Circuit for Half-Bridge (Referenced 14-SOP) Internal Block Diagram FAN7390A 13 VB 12 HO 11 VS 7 VDD 6 LO 5 COM UVLO NOISE CANCELLER R S DRIVER 200K PULSE GENERATOR HIN 1 R Q UVLO DRIVER VSS/COM LEVEL SHIFT DELAY LIN 2 200K VSS 3 Pin 4, 8, 9, 10 and 14 are no connection FAN7390A Rev.01 Figure 2. Functional Block Diagram (Referenced 14-SOP) © 2012 Fairchild Semiconductor Corporation FAN7390A Rev. 1.0.0 www.fairchildsemi.com 2 FAN7390A — High-Current, High & Low Side, Gate-Drive IC Typical Application Circuit FAN7390A — High-Current, High & Low Side, Gate-Drive IC Pin Configurations HIN 1 14 NC LIN 2 13 VB VSS 3 12 HO NC 4 11 VS COM 5 10 NC LO 6 9 NC VDD 7 8 NC FAN7390A FAN7390A Rev.02 Figure 3. Pin Assignments (Top View) Pin Definitions 14-Pin Name Description 1 HIN Logic Input for High-Side Gate Driver Output 2 LIN Logic Input for Low-Side Gate Driver Output 3 VSS Logic Ground 5 COM Low-Side Driver Return 6 LO Low-Side Driver Output 7 VDD Low-Side and Logic Part Supply Voltage 11 VS High-Voltage Floating Supply Return 12 HO High-Side Driver Output 13 VB High-Side Floating Supply 4, 8, 9, 10, 14 NC No Connect © 2012 Fairchild Semiconductor Corporation FAN7390A Rev. 1.0.0 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. TA=25°C, unless otherwise specified. Symbol Characteristics VS High-Side Floating Supply Offset Voltage VB High-Side Floating Supply Voltage Min. Max. Unit VB-VSHUNT VB+0.3 V -0.3 625.0 V VS-0.3 VB+0.3 V VHO High-Side Floating Output Voltage, HO Pin VDD Low-Side and Logic Fixed Supply Voltage -0.3 VSHUNT V VLO Low-Side Output Voltage, LO Pin -0.3 VDD+0.3 V VIN Logic Input Voltage (HIN and LIN) VSS-0.3 VDD+0.3 V VSS Logic Ground VDD-25 VDD+0.3 V Allowable Offset Voltage Slew Rate 50 V/ns Power Dissipation 1.0 W JA Thermal Resistance, Junction-to-Ambient 110 C/W TJ Junction Temperature +150 C TSTG Storage Temperature +150 C dVS/dt PD(1)(2)(3) Notes: 1. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR-4 glass epoxy material). 2. Refer to the following standards: JESD51-2: Integral circuits thermal test method environmental conditions - natural convection; and JESD51-3: Low effective thermal conductivity test board for leaded surface mount packages. 3. Do not exceed PD maximum under any circumstances. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol Parameter Min. Max. Unit VB High-Side Floating Supply Voltage VS+10 VS+20 V VS High-Side Floating Supply Offset Voltage 6-VDD 600 V VHO High-Side Output Voltage VS VB V VDD Low-Side and Logic Supply Voltage 10 20 V VLO Low-Side Output Voltage COM VDD V VIN Logic Input Voltage (HIN and LIN) VSS VDD V TA Operating Ambient Temperature -40 +125 C © 2012 Fairchild Semiconductor Corporation FAN7390A Rev. 1.0.0 www.fairchildsemi.com 4 FAN7390A — High-Current, High & Low Side, Gate-Drive IC Absolute Maximum Ratings VBIAS (VDD, VBS)=15.0 V, VS=VSS=COM, TA=25C, unless otherwise specified. The VIL, VIH, and IIN parameters are referenced to VSS/COM and are applicable to the respective input signals HIN and LIN. The VO and IO parameters are referenced to COM and VS is applicable to the respective output signals HO and LO. Symbol Characteristics Condition Min. Typ. Max. Unit POWER SUPPLY SECTION (VDD AND VBS) VDDUV+ VBSUV+ VDD and VBS Supply Under-Voltage  Positive-Going Threshold 8.0 8.8 9.8 VDDUVVBSUV- VDD and VBS Supply Under-Voltage  Negative-Going Threshold 7.4 8.3 9.0 VDDUVH VDD and VBS Supply Under-Voltage  VBSUVH Lockout Hysteresis Voltage V 0.5 ILK Offset Supply Leakage Current VB=VS=600 V 50 IQBS Quiescent VBS Supply Current VIN=0 V or 5 V 45 80 IQDD Quiescent VDD Supply Current VIN=0 V or 5 V 75 110 IPBS Operating VBS Supply Current fIN=20 kHz, rms value 530 640 IPDD Operating VDD Supply Current fIN=20 kHz, rms value 530 640 23 25 µA µA SHUNT REGULATOR SECTION VSHUNT VDD=Sweep or VBS=Sweep, ISHUNT=5 mA VDDand VBS Shunt Regulator Clamping Voltage 21 V LOGIC INPUT SECTION (HIN, LIN) VIH Logic "1" Input Voltage VIL Logic "0" Input Voltage 2.5 IIN+ Logic "1" Input Bias Current VIN=5 V 25 50 IIN- Logic "0" Input Bias Current VIN=0 V 1.0 2.0 RIN Input Pull-down Resistance 1.2 100 200 V µA K GATE DRIVER OUTPUT SECTION (HO, LO) VOH High-Level Output Voltage, VBIAS-VO No Load 1.0 V VOL Low-Level Output Voltage, VO No Load 35 mV IO+ Output High, Short-Circuit Pulsed Current(4) VO=0 V, VIN=5 V,PW