FAN7392N

High-Current, High- & Low-Side, Gate-Drive IC FAN7392 Description The FAN7392 is a monolithic high− and low−side gate drive IC, that can drive high−speed MOSFETs and IGBTs that operate up to +600 V. It has a buffered output stage with all NMOS transistors designed for high pulse current driving capability and minimum cross−conduction. ON Semiconductor’s high−voltage process and common−mode noise canceling techniques provide stable operation of the high−side driver under high dv/dt noise circumstances. An advanced level−shift circuit offers high−side gate driver operation up to VS = −9.8 V (typical) for VBS = 15 V. Logic inputs are compatible with standard CMOS or LSTTL output, down to 3.3 V logic. The UVLO circuit prevents malfunction when VCC and VBS are lower than the specified threshold voltage. The high−current and low−output voltage drop feature makes this device suitable for half− and full−bridge inverters, like switching−mode power supply and high−power DC−DC converter applications. Features • • • • • • • • • • • www.onsemi.com PDIP−14 14−PDIP CASE 646−06 SOIC−16 16−SOP CASE 751BH−01 MARKING DIAGRAM 14 $Y &Z&2K FAN7392N $Y&Z&2K FAN7392 FAN7392N FAN7392MX 1 Floating Channel for Bootstrap Operation to +600 V 3 A/3 A Sourcing/Sinking Current Driving Capability Common−Mode dv/dt Noise Canceling Circuit 3.3 V Logic Compatible Separate Logic Supply (VDD) Range from 3.3 V to 20 V Under−Voltage Lockout for VCC and VBS Cycle−by−Cycle Edge−Triggered Shutdown Logic Matched Propagation Delay for Both Channels Outputs In−phase with Input Signals Available in 14−DIP and 16−SOP (Wide) Packages This is a Pb−Free Device FAN7392N FAN7392 &Z &2 &K = Device Code = Assembly Plant Code = 2−Digit Date Code = 2−Digits Lot Run Traceability Code ORDERING INFORMATION See detailed ordering and shipping information on page 15 of this data sheet. Applications • • • • • • High−Speed Power MOSFET and IGBT Gate Driver Server Power Supply Uninterrupted Power Supply (UPS) Telecom System Power Supply Distributed Power Supply Motor Drive Inverter © Semiconductor Components Industries, LLC, 2009 May, 2021 − Rev. 2 1 Publication Order Number: FAN7392/D FAN7392 TYPICAL APPLICATION DIAGRAMS Up to 600 V Q1 15 V 8 NC HO 7 9 VDD VB 6 HIN 10 HIN VS 5 SD 11 SD NC 4 LIN 12 LIN VCC 3 13 VSS COM 2 R1 C BOOT Controller Load D BOOT R BOOT 15 V C1 Q2 R2 14 NC 1 LO Figure 1. Typical Application Circuit (Referenced 14−DIP) Up to 600 V Q1 9 NC HO 8 10 NC VB 7 VDD VS 6 HIN 12 HIN NC 5 SD 13 SD NC 4 LIN 14 LIN VCC 3 15 VSS COM 2 15 V R1 C BOOT 11 Controller Load DBOOT RBOOT 15 V C1 Q2 R2 16 NC 1 LO Figure 2. Application Circuit for Half−Bridge (Referenced 16−SOP) www.onsemi.com 2 FAN7392 INTERNAL BLOCK DIAGRAM 6 VB 7 HO 5 VS 3 V CC 1 LO 2 COM UVLO 10 SCHMITT TRIGGER INPUT LIN 12 SD 11 V SS 13 R DRIVER NOISE CANCELLER R Q S HS(ON/OFF) UVLO CYCLE−By−CYCLE EDGE TRIGGERED SHUTDOWN LS(ON/OFF) VSS/COM LEVEL SHIFT DELAY DRIVER HIN 9 PULSE GENERATOR V DD Pin 4, 8, and 14 are no connection Figure 3. Functional Block Diagram (Referenced 14−Pin) 7 VB 8 HO 6 VS 3 V CC 1 LO 2 COM UVLO 12 SCHMITT TRIGGER INPUT LIN 14 SD 13 V SS 15 R DRIVER NOISE CANCELLER R S Q HS(ON/OFF) UVLO CYCLE−By−CYCLE EDGE TRIGGERED SHUTDOWN LS(ON/OFF) VSS/COM LEVEL SHIFT DELAY Pin 4, 5, 9, 10 and 16 are no connection Figure 4. Functional Block Diagram (Referenced 16−SOP) www.onsemi.com 3 DRIVER HIN 11 PULSE GENERATOR V DD FAN7392 PIN CONFIGURATION COM 2 13 VSS VCC 3 12 LIN NC 4 VS 5 11 SD 10 HIN VB 6 9 VDD HO 7 8 NC 16 NC COM 2 15 VSS VCC 3 14 LIN NC 4 NC 5 FAN7392M 14 NC FAN7392 LO 1 LO 1 13 SD 12 HIN VS 6 11 VDD VB 7 10 NC HO 8 9 NC (a) 14−DIP (b) 16−SOP (Wide Body) Figure 5. Pin Configurations (Top View) PIN DEFINITIONS 14−Pin 16−Pin Name Description 1 1 LO 2 2 COM Low−Side Return 3 3 VCC Low−Side Supply Voltage 5 6 VS High−Voltage Floating Supply Return 6 7 VB High−Side Floating Supply 7 8 HO High−Side Driver Output 9 11 VDD Logic Supply Voltage 10 12 HIN Logic Input for High−Side Gate Driver Output Low−Side Driver Output 11 13 SD Logic Input for Shutdown Function 12 14 LIN Logic Input for Low−Side Gate Driver Output 13 15 VSS Logic Ground 4, 8, 14 4, 5, 9, 10, 16 NC No Connect www.onsemi.com 4 FAN7392 ABSOLUTE MAXIMUM RATINGS (TA = 25°C, unless otherwise noted) Symbol Min Max Unit VB High−Side Floating Supply Voltage −0.3 625.0 V VS High−Side Floating Offset Voltage VB − 25.0 VB + 0.3 V VHO High−Side Floating Output Voltage VS − 0.3 VB + 0.3 V VCC Low−Side Supply Voltage −0.3 25.0 V VLO Low−Side Floating Output Voltage −0.3 VCC + 0.3 V VDD Logic Supply Voltage VSS Logic Supply Offset Voltage VIN Logic Input Voltage (HIN, LIN and SD) dVS/dt PD qJA TJ TSTG Characteristics −0.3 VSS + 25.0 V VCC − 25.0 VCC + 0.3 V VSS − 0.3 VDD + 0.3 V − ±50 V/ns 14−PDIP − 1.6 W 16−SOP − 1.3 14−PDIP − 75 16−SOP − 95 − +150 °C −55 +150 °C Allowable Offset Voltage Slew Rate Power Dissipation (Note 1, 2, 3) Thermal Resistance Maximum Junction Temperature Storage Temperature °C/W Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Mounted on 76.2 x 114.3 x 1.6 mm PCB (FR−4 glass epoxy material). 2. Refer to the following standards: JESD51−2: Integral circuits thermal test method environmental conditions − natural convection; and JESD51−3: Low effective thermal conductivity test board for leaded surface−mount packages. 3. Do not exceed power dissipation (PD) under any circumstances. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VB High−Side Floating Supply Voltage VS + 10 VS + 20 V VS High−Side Floating Supply Offset Voltage 6 − VCC 600 V VHO High−Side Output Voltage VS VB V VCC Low−Side Supply Voltage 10 20 V VLO Low−Side Output Voltage VDD Logic Supply Voltage 0 VCC V VSS + 3 VSS + 20 V VSS Logic Supply Offset Voltage −5 5 V VIN Logic Input Voltage VSS VDD V TA Operating Ambient Temperature −40 +125 °C Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability. www.onsemi.com 5 FAN7392 ELECTRICAL CHARACTERISTICS (VBIAS (VCC, VBS, VDD) = 15.0 V, VSS = COM = 0 V and TA=25°C, unless otherwise specified. The VIH, VIL, and IIN parameters are referenced to VSS and are applicable to the respective input leads: HIN, LIN, and SD. The VO and IO parameters are referenced to VS and COM and are applicable to the respective output leads: HO and LO.) Symbol Characteristics Test Condition Min Typ Max Unit LOW−SIDE POWER SUPPLY SECTION IQCC Quiescent VCC Supply Current VIN = 0 V or VDD − 40 80 mA IQDD Quiescent VDD Supply Current VIN = 0 V or VDD − − 10 mA IPCC Operating VCC Supply Current fIN = 20 kHz, rms, VIN = 15 VPP − 430 − mA IPDD Operating VDD Supply Current fIN = 20 kHz, rms, VIN = 15 VPP − 300 − mA ISD Shutdown Supply Current SD=VDD − 120 − mA VCCUV+ VCC Supply Under−Voltage Positive−Going Threshold Voltage VIN = 0 V, VCC = Sweep 7.7 8.8 9.9 V VCCUV− VCC Supply Under−Voltage Negative−Going Threshold Voltage VIN = 0 V, VCC = Sweep 7.3 8.4 9.5 V VCCUVH VCC Supply Under−Voltage Lockout Hysteresis Voltage VIN = 0 V, VCC = Sweep − 0.4 − V BOOTSTRAPPED SUPPLY SECTION IQBS Quiescent VBS Supply Current VIN = 0 V or VDD − 60 130 mA IPBS Operating VBS Supply Current fIN = 20 kHz, rms value − 500 − mA VBSUV+ VBS Supply Under−Voltage Positive−Going Threshold Voltage VIN = 0 V, VBS = Sweep 7.7 8.8 9.9 V VBSUV− VBS Supply Under−Voltage Negative−Going Threshold Voltage VIN = 0 V, VBS = Sweep 7.3 8.4 9.5 V VBSUVH VBS Supply Under−Voltage Lockout Hysteresis Voltage VIN = 0 V, VBS = Sweep − 0.4 − V Offset Supply Leakage Current VB = VS = 600 V − − 50 mA VDD = 3 V 2.4 − − V VDD = 15 V 9.5 − − V VDD = 3 V − − 0.8 V ILK INPUT LOCIC SECTION (HIN, LIN, AND SD) VIH Logic “1” Input Threshold Voltage VIL Logic “0” Input Threshold Voltage VDD = 15 V − − 4.5 V IIN+ Logic Input High Bias Current VIN = VDD − 20 40 mA IIN− Logic Input Low Bias Current VIN = 0 V − − 3 mA RIN Logic Input Pull−Down Resistance 375 750 − kW − − 1.5 V GATE DRIVER OUTPUT SECTION VOH High−Level Output Voltage (VBIAS − VO) No Load (IO = 0 A) VOL Low−Level Output Voltage No Load (IO = 0 A) − − 200 mV IO+ Output High, Short−Circuit Pulsed Current (Note 4) VO = 0 V, PW ≤ 10 ms 2.5 3.0 − A IO− Output Low, Short−Circuit Pulsed Current (Note 4) VO = 15 V, PW ≤ 10 ms 2.5 3.0 − A −5.0 − 5.0 V − −9.8 −7.0 V VSS/COM −VS VSS−COM/COM−VSS Voltage Endurability Allowable Negative VS Pin Voltage for HIN Signal Propagation to HO Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. This parameter guaranteed by design. www.onsemi.com 6 FAN7392 DYNAMIC ELECTRICAL CHARACTERISTICS (VBIAS (VCC, VBS, VDD) = 15.0 V, VSS = COM = 0V, CLOAD = 1000 pF, TA = 25°C, unless otherwise specified.) Symbol Characteristics Test Condition Min Typ Max Unit ton Turn−On Propagation Delay Time VS = 0 V − 130 180 ns toff Turn−Off Propagation Delay Time VS = 0 V − 150 200 ns tsd Shutdown Propagation Delay Time (Note 5) − 130 180 tr Turn−On Rise Time − 25 50 tf Turn−Off Fall Time − 20 45 Delay Matching, HO & LO Turn−On/Off − − 35 MT 5. This parameter guaranteed by design. www.onsemi.com 7 FAN7392 180 200 160 180 140 160 tOFF (ns) tON (ns) TYPICAL CHARACTERISTICS 120 140 120 100 80 −40 −20 0 20 40 60 80 100 100 −40 120 −20 0 Temperature (°C) 40 40 30 30 tF (ns) tR (ns) 50 20 80 100 120 20 10 10 −20 0 20 40 60 80 100 0 −40 120 −20 0 Temperature (°C) 20 40 60 80 100 120 Temperature (°C) Figure 8. Turn−On Rise Time vs. Temperature Figure 9. Turn−Off Fall Time vs. Temperature 30 MTOFF (ns) 30 MTON (ns) 60 Figure 7. Turn−Off Propagation Delay vs. Temperature 50 20 10 0 −40 40 Temperature (°C) Figure 6. Turn−On Propagation Delay vs. Temperature 0 −40 20 20 10 −20 0 20 40 60 80 100 0 −40 120 −20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) Figure 10. Turn−On Delay Matching vs. Temperature Figure 11. Turn−Off Delay Matching vs. Temperature www.onsemi.com 8 FAN7392 TYPICAL CHARACTERISTICS (continued) 180 40 160 140 IIN+ (mA) tSD (ns) 30 120 10 100 80 −40 20 −20 0 20 40 60 80 100 0 −40 120 −20 0 20 40 60 80 100 120 Temperature (°C) Temperature (°C) Figure 12. Shutdown Propagation Delay vs. Temperature Figure 13. Logic Input High Bias Current vs. Temperature 80 120 60 100 50 80 IQBS (mA) IQCC (mA) 70 40 30 40 20 20 10 0 −40 60 −20 0 20 40 60 80 100 0 −40 120 −20 0 Figure 14. Quiescent VCC Supply Current vs. Temperature 800 800 600 600 IPBS (mA) 1000 IPCC (mA) 40 60 80 100 120 Figure 15. Quiescent VBS Supply Current vs. Temperature 1000 400 200 0 −40 20 Temperature (°C) Temperature (°C) 400 200 −20 0 20 40 60 80 100 0 −40 120 Temperature (°C) −20 0 20 40 60 80 100 Temperature (°C) Figure 16. Operating VCC Supply Current vs. Temperature Figure 17. Operating VBS Supply Current vs. Temperature www.onsemi.com 9 120 FAN7392 TYPICAL CHARACTERISTICS (continued) 9.5 9.0 VCCUV− (V) VCCUV+ (V) 9.5 9.0 8.5 8.5 8.0 8.0 7.5 −40 −20 0 20 40 60 80 100 120 −40 −20 0 Temperature (°C) 20 40 60 80 100 120 Temperature (°C) Figure 18. VCC UVLO+ vs. Temperature Figure 19. VCC UVLO− vs. Temperature 9.5 9.0 VBSUV− (V) VBSUV+ (V) 9.5 9.0 8.5 8.5 8.0 8.0 7.5 −40 −20 0 20 40 60 80 100 120 −40 −20 0 Temperature (°C) 20 40 60 80 100 120 Temperature (°C) Figure 20. VBS UVLO+ vs. Temperature Figure 21. VBS UVLO− vs. Temperature 1.5 20 15 10 VOH (V) VOL (mV) 1.0 0.5 5 0 −5 −10 −15 0.0 −40 −20 0 20 40 60 80 100 −20 −40 120 Temperature (°C) −20 0 20 40 60 80 100 Temperature (°C) Figure 22. High−Level Output Voltage vs. Temperature Figure 23. Low−Level Output Voltage vs. Temperature www.onsemi.com 10 120 FAN7392 TYPICAL CHARACTERISTICS (continued) 11 10 VDD = 15 V VDD = 15 V 9 10 9 VIL (V) VIH (V) 8 8 7 6 5 7 6 −40 4 −20 0 20 40 60 80 100 3 −40 120 −20 0 20 Figure 24. Logic High Input Voltage vs. Temperature Logic Threshold Voltage (V) VS (V) −9 −10 −11 100 120 −20 0 20 40 60 80 100 10 8 6 4 2 0 120 VIH VIL 0 Figure 26. Allowable Negative VS Voltage vs. Temperature −6 −8 −10 −12 −14 −16 12 13 14 15 16 4 6 8 10 12 14 16 18 Figure 27. Input Logic (HIN & LIN) Threshold Voltage vs. VDD Supply Voltage VCC = VBS COM = 0 V TA = 25°C −4 11 2 VDD Logic Supply Voltage (V) Temperature (°C) VS (V) 80 12 −8 10 60 Figure 25. Logic Low Input Voltage vs. Temperature −7 −12 −40 40 Temperature (°C) Temperature (°C) 17 18 19 20 Supply Voltage (V) Figure 28. Allowable Negative Vs Voltage for HIN Signal Propagation to High Side vs. Supply Voltage www.onsemi.com 11 20 FAN7392 SWITCHING TIME DEFINITIONS 15 V 8 NC HO 7 9 VDD VB 6 HIN 10 HIN VS 5 SD 11 SD NC 4 LIN 12 LIN VCC 3 13 VSS COM 2 14 NC LO 1 HO 1 nF 10 mF 100 nF 15 V (0 to 600 V) 10 mF 15 V 10 mF 100 nF LO 1 nF Figure 29. Switching Time Test Circuit (Referenced 14−DIP) HIN LIN SD HO LO Shutdown Skip Figure 30. Input/Output Timing Diagram HIN LIN 50% 50% t ON t R t OFF t F 90% HO LO 90% 10% 10% Figure 31. Switching Time Waveform Definitions www.onsemi.com 12 FAN7392 SWITCHING TIME DEFINITIONS (continued) 50% SD t SD 90% HO LO Figure 32. Shutdown Waveform Definition HIN LIN 50% 50% LO 10% MT HO 10% 90% 90% LO MT Figure 33. Delay Matching Waveform Definitions www.onsemi.com 13 HO FAN7392 APPLICATION INFORMATION Figure 36 and Figure 37 show the commutation of the load current between high−side switch, Q1, and low−side freewheelling diode, D3, in same inverter leg. The parasitic inductances in the inverter circuit from the die wire bonding to the PCB tracks are jumped together in LC and LE for each IGBT. When the high−side switch, Q1, and low−side switch, Q4, are turned on, the VS1 node is below DC+ voltage by the voltage drops associated with the power switch and the parasitic inductances of the circuit due to load current is flows from Q1 and Q4, as shown in Figure 36. When the high−side switch, Q1, is turned off and Q4, remained turned on, the load current to flows the low−side freewheeling diode, D3, due to the inductive load connected to VS1 as shown in Figure 37. The current flows from ground (which is connected to the COM pin of the gate driver) to the load and the negative voltage present at the emitter of the high−side switching device. In this case, the COM pin of the gate driver is at a higher potential than the VS pin due to the voltage drops associated with freewheeling diode, D3, and parasitic elements, LC3 and LE3. Negative VS Transient The bootstrap circuit has the advantage of being simple and low cost, but has some limitations. The biggest difficulty with this circuit is the negative voltage present at the emitter of the high−side switching device when high−side switch is turned−off in half−bridge application. If the high−side switch, Q1, turns−off while the load current is flowing to an inductive load, a current commutation occurs from high−side switch, Q1, to the diode, D2, in parallel with the low−side switch of the same inverter leg. Then the negative voltage present at the emitter of the high−side switching device, just before the freewheeling diode, D2, starts clamping, causes load current to suddenly flow to the low−side freewheeling diode, D2, as shown in Figure 34. DC+ Bus Q1 D1 iLOAD ifreewheeling VS DC+ Bus Load L C1 V LC1 L C2 Q2 Q1 D1 Q2 D2 i LOAD D2 L E1 V LE1 V S1 i freewheeling V S2 Load L C3 Figure 34. Half−Bridge Application Circuits L E2 V LC4 D3 This negative voltage can be trouble for the gate driver’s output stage, there is the possibility to develop an over−voltage condition of the bootstrap capacitor, input signal missing and latch−up problems because it directly affects the source VS pin of the gate driver, as shown in Figure 35. This undershoot voltage is called “negative VS transient”. L C4 Q4 Q3 D4 L E3 V LE4 L E4 Figure 36. Q1 and Q4 Turn−On DC+ Bus L C1 Q1 L C2 Q2 Q1 GND D1 D2 i LOAD i freewheeling L E1 V S1 L C3 VS L E2 V S2 Load V LC3 V LC4 Q3 D3 GND L E3 Freewheeling V LE3 D4 V LE4 Figure 37. Q1 Turn−Off and D3 Conducting Figure 35. VS Waveforms During Q1 Turn−Off www.onsemi.com 14 L C4 Q4 L E4 FAN7392 • To minimize noise coupling, the ground plane should not The FAN7392 has a negative VS transient performance curve, as shown in Figure 38. • −100 −90 −80 Placement of Components The recommended placement and selection of component as follows: • Place a bypass capacitor between the VDD and VSS pins. A ceramic 1 mF capacitor is suitable for most applications. This component should be placed as close as possible to the pins to reduce parasitic elements. • The bypass capacitor from VCC to COM supports both the low−side driver and bootstrap capacitor recharge. A value at least ten times higher than the bootstrap capacitor is recommended. • The bootstrap resistor, RBOOT, must be considered in sizing the bootstrap resistance and the current developed during initial bootstrap charge. If the resistor is needed in series with the bootstrap diode, verify that VB does not fall below COM (ground). Recommended use is typically 5~10 W that increase the VBS time constant. If the voltage drop of of bootstrap resistor and diode is too high or the circuit topology does not allow a sufficient charging time, a fast recovery or ultra−fast recovery diode can be used. • The bootstrap capacitor, CBOOT, uses a low−ESR capacitor, such as ceramic capacitor. −70 −60 VS (V) be placed under or near the high−voltage floating side. To reduce the EM coupling and improve the power switch turn−on/off performance, the gate drive loops must be reduced as much as possible. −50 −40 −30 −20 −10 0 0 100 200 300 400 500 600 700 800 900 1000 Pulse Width (ns) Figure 38. Negative VS Transient Characteristic Even though the FAN7392 has been shown able to handle these negative VS tranient conditions, it is strongly recommended that the circuit designer limit the negative VS transient as much as possible by careful PCB layout to minimized the value of parasitic elements and component use. The amplitude of negative VS voltage is proportional to the parasitic inductances and the turn−off speed, di/dt, of the switching device. It is strongly recommended that the placement of components is as follows: • Place components tied to the floating voltage pins (VB and VS) near the respective high−voltage portions of the device and the FAN7392. NC (not connected) pins in this package maximize the distance between the high−voltage and low−voltage pins (see Figure 5). • Place and route for bypass capacitors and gate resistors as close as possible to gate drive IC. • Locate the bootstrap diode, DBOOT, as close as possible to bootstrap capacitor, CBOOT. • The bootstrap diode must use a lower forward voltage drop and minimal switching time as soon as possible for fast recovery or ultra−fast diode. GENERAL GUIDELINES Printed Circuit Board Layout The relayout recommended for minimized parasitic elements is as follows: • Direct tracks between switches with no loops or deviation. • Avoid interconnect links. These can add significant inductance. • Reduce the effect of lead−inductance by lowering package height above the PCB. • Consider co−locating both power switches to reduce track length. ORDERING INFORMATION Device FAN7392N Operating Temperature Range Package Shipping† −40°C~125°C PDIP−14 14−PDIP (Pb−Free) 1500 Units / Tube SOIC−16 16−SOP (Pb−Free) 1000 / Tape & Reel FAN7392MX †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 15 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PDIP−14 CASE 646−06 ISSUE S 1 SCALE 1:1 D A 14 8 E H E1 1 NOTE 8 7 b2 c B TOP VIEW END VIEW WITH LEADS CONSTRAINED NOTE 5 A2 A NOTE 3 L SEATING PLANE A1 C D1 e M eB END VIEW 14X b SIDE VIEW 0.010 M C A M B M NOTE 6 DATE 22 APR 2015 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: INCHES. 3. DIMENSIONS A, A1 AND L ARE MEASURED WITH THE PACKAGE SEATED IN JEDEC SEATING PLANE GAUGE GS−3. 4. DIMENSIONS D, D1 AND E1 DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS ARE NOT TO EXCEED 0.10 INCH. 5. DIMENSION E IS MEASURED AT A POINT 0.015 BELOW DATUM PLANE H WITH THE LEADS CONSTRAINED PERPENDICULAR TO DATUM C. 6. DIMENSION eB IS MEASURED AT THE LEAD TIPS WITH THE LEADS UNCONSTRAINED. 7. DATUM PLANE H IS COINCIDENT WITH THE BOTTOM OF THE LEADS, WHERE THE LEADS EXIT THE BODY. 8. PACKAGE CONTOUR IS OPTIONAL (ROUNDED OR SQUARE CORNERS). DIM A A1 A2 b b2 C D D1 E E1 e eB L M INCHES MIN MAX −−−− 0.210 0.015 −−−− 0.115 0.195 0.014 0.022 0.060 TYP 0.008 0.014 0.735 0.775 0.005 −−−− 0.300 0.325 0.240 0.280 0.100 BSC −−−− 0.430 0.115 0.150 −−−− 10 ° MILLIMETERS MIN MAX −−− 5.33 0.38 −−− 2.92 4.95 0.35 0.56 1.52 TYP 0.20 0.36 18.67 19.69 0.13 −−− 7.62 8.26 6.10 7.11 2.54 BSC −−− 10.92 2.92 3.81 −−− 10 ° GENERIC MARKING DIAGRAM* 14 XXXXXXXXXXXX XXXXXXXXXXXX AWLYYWWG STYLES ON PAGE 2 1 XXXXX A WL YY WW G = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. DOCUMENT NUMBER: DESCRIPTION: 98ASB42428B PDIP−14 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com PDIP−14 CASE 646−06 ISSUE S DATE 22 APR 2015 STYLE 1: PIN 1. COLLECTOR 2. BASE 3. EMITTER 4. NO CONNECTION 5. EMITTER 6. BASE 7. COLLECTOR 8. COLLECTOR 9. BASE 10. EMITTER 11. NO CONNECTION 12. EMITTER 13. BASE 14. COLLECTOR STYLE 2: CANCELLED STYLE 3: CANCELLED STYLE 4: PIN 1. DRAIN 2. SOURCE 3. GATE 4. NO CONNECTION 5. GATE 6. SOURCE 7. DRAIN 8. DRAIN 9. SOURCE 10. GATE 11. NO CONNECTION 12. GATE 13. SOURCE 14. DRAIN STYLE 5: PIN 1. GATE 2. DRAIN 3. SOURCE 4. NO CONNECTION 5. SOURCE 6. DRAIN 7. GATE 8. GATE 9. DRAIN 10. SOURCE 11. NO CONNECTION 12. SOURCE 13. DRAIN 14. GATE STYLE 6: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. NO CONNECTION 7. ANODE/CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. NO CONNECTION 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 7: PIN 1. NO CONNECTION 2. ANODE 3. ANODE 4. NO CONNECTION 5. ANODE 6. NO CONNECTION 7. ANODE 8. ANODE 9. ANODE 10. NO CONNECTION 11. ANODE 12. ANODE 13. NO CONNECTION 14. COMMON CATHODE STYLE 8: PIN 1. NO CONNECTION 2. CATHODE 3. CATHODE 4. NO CONNECTION 5. CATHODE 6. NO CONNECTION 7. CATHODE 8. CATHODE 9. CATHODE 10. NO CONNECTION 11. CATHODE 12. CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 9: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. NO CONNECTION 5. ANODE/CATHODE 6. ANODE/CATHODE 7. COMMON ANODE 8. COMMON ANODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. NO CONNECTION 12. ANODE/CATHODE 13. ANODE/CATHODE 14. COMMON CATHODE STYLE 10: PIN 1. COMMON CATHODE 2. ANODE/CATHODE 3. ANODE/CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. NO CONNECTION 7. COMMON ANODE 8. COMMON CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. ANODE/CATHODE 12. ANODE/CATHODE 13. NO CONNECTION 14. COMMON ANODE STYLE 11: PIN 1. CATHODE 2. CATHODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE 7. CATHODE 8. ANODE 9. ANODE 10. ANODE 11. ANODE 12. ANODE 13. ANODE 14. ANODE STYLE 12: PIN 1. COMMON CATHODE 2. COMMON ANODE 3. ANODE/CATHODE 4. ANODE/CATHODE 5. ANODE/CATHODE 6. COMMON ANODE 7. COMMON CATHODE 8. ANODE/CATHODE 9. ANODE/CATHODE 10. ANODE/CATHODE 11. ANODE/CATHODE 12. ANODE/CATHODE 13. ANODE/CATHODE 14. ANODE/CATHODE DOCUMENT NUMBER: DESCRIPTION: 98ASB42428B PDIP−14 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SOIC−16, 300 mils CASE 751BH−01 ISSUE A DATE 18 MAR 2009 D SYMBOL E1 E MIN NOM MAX 2.49 2.64 A 2.36 A1 0.10 b 0.33 0.41 0.51 c 0.18 0.23 0.28 D 10.08 10.31 10.49 E 10.01 10.31 10.64 E1 7.39 7.49 7.59 0.30 1.27 BSC e h 0.25 L 0.38 θ 0º 0.75 0.81 1.27 8º PIN #1 IDENTIFICATION TOP VIEW h A b e A1 SIDE VIEW c q L END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-013. DOCUMENT NUMBER: DESCRIPTION: 98AON34279E SOIC−16, 300 MILS Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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