DATA SHEET
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Advanced Pulse Frequency
Modulation (PFM) Controller
for Half-Bridge Resonant
Converters
SOP16
CASE 565BF
FAN7631
MARKING DIAGRAM
Description
The FAN7631 is a pulse−frequency modulation controller
for high−efficiency half−bridge resonant converters that includes
a high−side gate drive circuit, an accurate current−controlled
oscillator, and various protection functions. The FAN7631 features
include variable dead time, operating frequency up to 600 kHz,
protections such as LUVLO, and a selectable latch or A/R protection
using the LS pin for user convenience.
The Zero−Voltage−Switching (ZVS) technique reduces
the switching losses and improves the efficiency significantly. ZVS
also reduces the switching noise noticeably, which allows a small
Electromagnetic Interference (EMI) filter.
Offering everything necessary to build a reliable and robust resonant
converter, the FAN7631 simplifies designs and improves productivity
and performance. The FAN7631 can be applied to resonant converter
topologies such as series resonant, parallel resonant, and LLC resonant
converters.
Features
• Variable Frequency Control with 50% Duty Cycle for Half−Bridge
•
•
•
•
•
•
•
•
•
Resonant Converter Topologies
High Efficiency with Zero−Voltage−Switching (ZVS)
Up to 600 kHz Operating Frequency
Built−in High−Side Gate Driver
High Gate−Driving Current: +500 mA/−1000 mA
Programmable Dead Time with a Resistor
Pulse Skipping and Burst Operation for Frequency Limit
(Programmable) at Light−Load Condition
Simple Remote On/Off Control with Latch or Auto−Restart (A/R)
Using FI or LS Pin
Protection Functions: Over−Voltage Protection (OVP), Overload
Protection (OLP), Over−Current Protection (OCP), Abnormal
Over−Current Protection (AOCP), Internal Thermal Shutdown
(TSD), and High Precise Line Under−Voltage Lockout (LUVLO)
Level−Change OCP Function During Startup
$Y&Z&2&K
FAN7631
FAN7631
$Y
&Z
&2
&K
= Device Code
= Logo
= Assembly Plant Code
= 2−Digit Date Code
= 2−Digits Lot Run Traceability Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 17 of
this data sheet.
Related Resources
AN4151 — Half−Bridge LLC Resonant
Converter Design Using FSFR−Series Power
Switch
Applications
•
•
•
•
•
PDP and LCD Tvs
Desktop PCs and Servers
Video Game Consoles
Adapters
Telecom Power Supplies
© Semiconductor Components Industries, LLC, 2011
March, 2022 − Rev. 2
1
Publication Order Number:
FAN7631/D
FAN7631
APPLICATION CIRCUIT DIAGRAM
VIN
CON
2
RT
HO
15
SS
CTR
14
4
OP2
16
1
3
OP1
VOUT
Cr
VCC
7
8
LVCC
FI
LO
SG
PG
LS
CS
OP1
Q2
Lr(LIk)
13
DT
5
6
HVCC
OP2
12
Q1
Remote OFF
(Latch)
11
10
OP3
RCS
9
Remote OFF
(A/R)
OP3
Figure 1. Typical Application Circuit (Resonant Half−Bridge Converter)
BLOCK DIAGRAM
LVCC
HVCC
HO
RT
CTR
DT
LO
CS
SS
PG
SG
LS
LI
CON
Figure 2. Internal Block Diagram
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2
FAN7631
PIN CONFIGURATION
CON
1
16
HVCC
RT
2
15
HO
SS
3
14
CTR
DT
4
13
NC
NC
5
12
LVCC
FI
6
11
LO
SG
7
10
PG
LS
8
9
CS
FAN7631
Figure 3. Package Pin Assignments (SOP16)
PIN DEFINITIONS
Pin No.
Name
Description
1
CON
This pin is used to enable / disable the gate drive outputs for pulse−skipping operation. When the voltage of this
pin is above 0.6 V, the gate drive outputs are enabled. When the voltage of this pin drops below 0.4 V, gate drive
signals for both MOSFETs are disabled.
2
RT
This pin programs the switching frequency. Typically, an opto−coupler is connected to this pin to control the
switching frequency for the output voltage regulation.
3
SS
This pin is used to program the soft−start time and overload protection delay. It also programs the restart delay
when the converter auto recovers from the protection states. Typically, a small capacitor is connected on this pin.
4
DT
This pin is to adjust the dead time using an external resistor.
5
NC
No connection
6
FI
User protection function / fault input. This pin can be used as a latch protection, which is operated when a voltage
applied to this pin is higher than 4VDC.
7
SG
This pin is the ground of the control part.
8
LS
This pin senses the line voltage for line under−voltage lockout (LUVLO).
9
CS
This pin senses the current flowing through the main MOSFET. Typically, negative voltage is applied on this pin.
10
PG
This pin is the power ground. This pin typically connects to the source of the low−side MOSFET.
11
LO
This pin is used for the low−side gate−driving signal.
12
LVCC
13
NC
14
CTR
This pin is connected to the drain of the low−side MOSFET. Typically, a transformer is connected to this pin.
15
HO
This pin is used for the high−side gate−driving signal.
16
HVCC
This pin is for the supply voltage of the control IC and low−side gate−driving circuit.
No connection
This pin is used for the supply voltage of the high−side gate−driving circuit.
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3
FAN7631
ABSOLUTE MAXIMUM RATINGS
Symbol
HVCC to VCTR
HVCC
Min
Max
Unit
High−Side VCC Pin to Center Voltage
Parameter
−0.3
25.0
V
High−Side Floating Supply Voltage
−0.3
625.0
V
VHO
High−Side Gate\−Driving Voltage
VCTR − 0.3
HVCC + 0.3
V
VCTR
High−Side Offset Voltage
HVCC − 25
HVCC + 0.3
V
Allowable Negative VCTR at 15VDC Applied HVCC to CTR Pin
−9.8
−7.0
V
LVCC
Low−Side Supply Voltage
−0.3
25.0
V
VLO
Low−Side Gate Driving Voltage
−0.3
LVCC
V
Control Pin Input Voltage
−0.3
LVCC
V
VCS
Current Sense (CS) Pin Input Voltage
−5.0
1.0
V
VRT
RT Pin Input Voltage
−0.3
5.0
V
fSW
Recommended Switching Frequency
10
600
kHz
VLS
LS Pin Input Voltage
−0.3
LVCC
V
VFI
FI Pin Input Voltage
−0.3
LVCC
V
VSS
SS Pin Input Voltage
−0.3
Internally
Clamped
(Note 1)
V
VDT
DT Pin Input Voltage
−0.3
Internally
Clamped
(Note 1)
V
Allowable CTR Voltage Slew Rate
−
50
V/ns
PD
Total Power Dissipation
−
1.24
W
TJ
Maximum Junction Temperature (Note 2)
−
+150
°C
Recommended Operating Junction Temperature (Note 2)
−40
+130
Storage Temperature Range
−55
+150
VCON
dVCTR/dt
TSTG
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. VSS and VDT are internally clamped at 5.0 V, which has a tolerance between 4.75 V and 5.25 V.
2. The maximum value of the recommended operating junction temperature is limited by thermal shutdown.
THERMAL CHARACTERISTICS
Symbol
qJA
Parameter
Junction−to−Ambient Thermal Impedance
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4
Value
Unit
102
°C/W
FAN7631
ELECTRICAL CHARACTERISTICS (TA = 25°C and LVCC = 17 V unless otherwise specified)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
SUPPLY SECTION
ILK
Offset Supply Leakage Current
HVCC = VCTR
−
−
50
mA
IQHVCC
Quiescent HVCC Supply Current
HVCC, START − 0.1 V, VCTR = 0 V
−
50
120
mA
IQLVCC
Quiescent LVCC Supply Current
LVCC, START − 0.1 V, VCTR = 0 V
−
100
200
mA
IOHVCC
Operating HVCC Supply Current
(RMS Value) (Note 3)
fOSC = 100 kHz, CLoad = 1 nF,
VCON > 0.6 V, VCTR = 0 V
−
3.0
4.5
mA
fOSC = 300 kHz, CLoad = 1 nF,
VCON > 0.6 V, VCTR = 0 V
−
8
10
mA
fOSC = 300 kHz, VCON < 0.4 V,
VCTR = 0 V (No Switching)
−
100
200
mA
fOSC = 100 kHz, CLoad = 1 nF,
VCON > 0.6 V, VCTR = 0 V
−
5
7
mA
fOSC = 300 kHz, CLoad = 1 nF,
VCON > 0.6 V, VCTR = 0 V
−
10
14
mA
fOSC = 300 kHz, VCON < 0.4 V,
VCTR = 0 V (No Switching)
−
2.6
3.5
mA
IOLVCC
Operating LVCC Supply Current
(RMS Value) (Note 3)
UVLO SECTION
LVCC, START
LVCC UVLO Turn−On Threshold
11.2
12.5
13.8
V
LVCC, STOP
LVCC UVLO Turn−Off Threshold
8.9
10.0
11.1
V
LVCC, HYS
LVCC UVLO Hysteresis
−
2.5
−
V
HVCC, START
HVCC UVLO Turn−On Threshold
8.2
9.2
10.2
V
HVCC, STOP
LVCC UVLO Turn−Off Threshold
7.8
8.7
9.6
V
HVCC, HYS
HVCC UVLO Hysteresis
−
0.5
−
V
OSCILLATOR & FEEDBACK SECTION
VBH
Pulse Skip Disable Threshold
Voltage
0.54
0.60
0.66
V
VBL
Pulse Skip Enable Threshold
Voltage
0.36
0.40
0.44
V
VRT
Regulated RT Voltage
1.5
2.0
2.5
V
fOSC
Output Oscillation Frequency
RT = 11.6 kW, CSS = 1 nF
48
50
52
kHz
RT = 2.7 kW, CSS = 1 nF
188
200
212
RT = 11.6 kW, CLoad = 100 pF
49
50
51
RT = 2.7 kW, CLoad = 100 pF
48
50
52
DC
Output Duty Cycle
%
SOFT−START AND RESTART SECTION
ISS1
Soft−Start Current 1
VCSS = 0 V, LVCC = 17 V
3
−
−
mA
ISS2
Soft−Start Current 2
VCSS = 1.6 V, LVCC = 17 V
25
30
35
mA
VSS_START
Soft−Start Start Voltage
CSS = 1 nF, VCON = 3 V
1.5
1.6
1.7
V
VSS_END
Soft−Start End Voltage
CSS = 1 nF, VCON = 3 V
4.0
4.2
4.4
V
Clamped Soft−Start Voltage
CSS = 1 nF, VCON = 3 V
4.75
5.00
5.25
V
kHz
VSSC
fOSC_SS
VRT−CON
Initial Output Oscillation Frequency
During Soft−Start
RT = 11.6 kW, VCSS = 1.6 V
−
300
−
RT = 5.8 kW
−
530
−
RT = 2.7 kW
600
−
−
−
60
120
RT−CON Voltage for Startup
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5
mV
FAN7631
ELECTRICAL CHARACTERISTICS (TA = 25°C and LVCC = 17 V unless otherwise specified) (continued)
Symbol
Parameter
Test Condition
Min
Typ
Max
Unit
OUTPUT SECTION
Peak Sourcing Current
LVCC = HVCC = 17 V,
TJ = 40°C ~ 130°C
500
−
−
mA
Peak Sinking Current
HVCC = 17 V,
TJ = 40°C ~ 130°C
1000
−
−
mA
tr
Rising Time
HVCC = 17 V, CLoad = 1 nF
−
40
−
ns
tf
Falling Time
−
20
−
ns
−
−
1.0
V
Isource
Isink
IO = 20 mA
VHOH
High Level of High−Side Gate
Signal (VHVCC−VHO)
VHOL
Low Level of High−Side Gate
Signal
−
−
0.6
V
VLOH
High Level of Low−Side Gate
Signal (VLVCC−VLO)
−
−
1.0
V
VLOL
Low Level of Low−Side Gate
Signal
−
−
0.6
V
25
30
35
mA
−0.42
−0.37
−0.32
V
150
200
250
ns
−0.62
−0.56
−0.50
V
150
200
250
ns
−1.21
−1.10
−0.99
V
PROTECTION SECTION
IOLP
OLP Sink Current
VOLP
OLP Threshold Voltage
tBOL
OLP Blanking Time (Note 3)
VOCP
OCP Threshold Voltage
tBO
VAOCP
OCP Blanking Time (Note 3)
AOCP Threshold Voltage
tBAO
AOCP Blanking Time (Note 3)
−
50
−
ns
tDA
Delay Time (Low Side) Detecting
from VAOCP to Switch Off (Note 3)
−
250
400
ns
VOVP
LVCC Over−Voltage Protection
21
23
25
V
VLINE
Line UVLO Threshold Voltage
VLS Sweep, 40°C ~ 130°C
2.88
3.00
3.12
V
ILINE
Line UVLO Hysteresis Current
VLS = 2 V
9
10
11
mA
TSD
Thermal Shutdown Temperature
(Note 3)
130
140
150
°C
VFI
Fault Input Threshold Voltage for
Latch Operation
3.8
4.0
4.2
V
ILR
Latch−Protection Sustain LVCC
Supply Current
−
100
150
mA
VLR
Latch−Protection Reset LVCC
Supply Voltage
5
−
−
V
RDT = 2.7 kW, CLoad = 1 nF
100
150
200
ns
RDT = 18 kW, CLoad = 1 nF
250
350
450
Short, CLoad = 1 nF
−
50
−
Open, CLoad = 1 nF
−
1000
−
100
−
600
LVCC = 7.5 V
DEAD−TIME CONTROL SECTION
DT
Dead Time
Recommended Dead Time Range
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. This parameter, although guaranteed, is not tested in production.
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FAN7631
1.20
1.20
1.15
1.15
1.10
1.10
Normalized
Normalized
TYPICAL CHARACTERISTICS (These characteristic graphs are normalized at TA = 25°C)
1.05
1.00
0.95
1.05
1.00
0.95
0.90
0.90
0.85
0.85
0.80
−40
−20
0
25
50
75
100
0.80
−40
120
−20
0
Temperature (°C)
1.20
1.15
1.10
1.10
Normalized
Normalized
1.20
1.05
1.00
0.95
0.95
0.90
0.85
25
50
75
100
0.80
−40
120
−20
0
50
75
100
120
Figure 7. HVCC Stop Voltage vs. Temperature
Figure 6. HVCC Start Voltage vs. Temperature
1.20
1.20
1.15
1.15
1.10
1.10
1.05
1.05
Normalized
Normalized
25
Temperature (°C)
Temperature (°C)
1.00
0.95
0.90
1.00
0.95
0.90
0.85
0.80
120
1.00
0.85
0
100
1.05
0.90
−20
75
Figure 5. LVCC Stop Voltage vs. Temperature
1.15
−40
50
Temperature (°C)
Figure 4. LVCC Start Voltage vs. Temperature
0.80
25
0.85
−40
−20
0
25
50
75
100
0.80
−40
120
Temperature (°C)
−20
0
25
50
75
100
Temperature (°C)
Figure 8. Pulse Skip Disable vs. Temperature
Figure 9. Pulse Skip Enable Voltage
vs. Temperature
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120
FAN7631
1.20
1.20
1.15
1.15
1.10
1.10
Normalized
Normalized
TYPICAL CHARACTERISTICS (These characteristic graphs are normalized at TA = 25°C) (continued)
1.05
1.00
0.95
1.05
1.00
0.95
0.90
0.90
0.85
0.85
0.80
−40
−20
0
25
50
75
100
0.80
−40
120
−20
0
Temperature (°C)
1.20
1.15
1.10
1.10
Normalized
Normalized
1.20
1.05
1.00
0.95
0.95
0.90
0.85
50
75
100
0.80
−40
120
−20
0
50
75
100
120
Figure 13. Output Duty Cycle (RT = 11.6 kW)
vs. Temperature
Figure 12. Output Oscillation Frequency
(RT = 2.7 kW) vs. Temperature
1.20
1.30
1.15
1.20
1.10
1.05
Normalized
Normalized
25
Temperature (°C)
Temperature (°C)
1.00
0.95
0.90
1.10
1.00
0.90
0.80
0.85
0.80
120
1.00
0.85
25
100
1.05
0.90
0
75
Figure 11. Output Oscillation Frequency
(RT = 11.6 kW) vs. Temperature
1.15
−20
50
Temperature (°C)
Figure 10. Regulated RT Voltage vs. Temperature
0.80
−40
25
−40
−20
0
25
50
75
100
0.70
120
Temperature (°C)
−40
−20
0
25
50
75
100
Temperature (°C)
Figure 15. ISS1 vs. Temperature
Figure 14. Output Duty Cycle (RT = 2.7 kW)
vs. Temperature
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120
FAN7631
1.20
1.20
1.15
1.15
1.10
1.10
Normalized
Normalized
TYPICAL CHARACTERISTICS (These characteristic graphs are normalized at TA = 25°C) (continued)
1.05
1.00
0.95
1.05
1.00
0.95
0.90
0.90
0.85
0.85
0.80
−40
−20
0
25
50
100
75
0.80
−40
120
−20
0
Temperature (°C)
1.20
1.15
1.10
1.10
Normalized
Normalized
1.20
1.05
1.00
0.95
0.95
0.90
0.85
50
75
100
0.80
−40
120
−20
0
Figure 18. fOSC_SS (RT = 2.7 kW)
vs. Temperature
50
75
100
120
Figure 19. VOLP vs. Temperature
1.20
1.20
1.15
1.15
1.10
1.10
1.05
Normalized
Normalized
25
Temperature (°C)
Temperature (°C)
1.00
0.95
1.05
1.00
0.95
0.90
0.90
0.85
0.85
0.80
120
1.00
0.85
25
100
1.05
0.90
0
75
Figure 17. fOSC_SS (RT = 11.6 kW)
vs. Temperature
1.15
−20
50
Temperature (°C)
Figure 16. ISS2 vs. Temperature
0.80
−40
25
−40
−20
0
25
50
75
100
0.80
120
Temperature (°C)
−40
−20
0
25
50
75
100
Temperature (°C)
Figure 21. VOCP vs. Temperature
Figure 20. IOLP vs. Temperature
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120
FAN7631
1.20
1.20
1.15
1.15
1.10
1.10
Normalized
Normalized
TYPICAL CHARACTERISTICS (These characteristic graphs are normalized at TA = 25°C) (continued)
1.05
1.00
0.95
0.90
0.85
0.85
−20
0
25
50
75
Temperature (°C)
100
0.80
−40
120
Figure 22. VAOCP vs. Temperature
1.20
1.15
1.15
1.10
1.10
1.05
1.00
0.95
0.85
50
75
25
Temperature (°C)
100
0.80
−40
120
Figure 24. VLINE vs. Temperature
1.20
1.20
1.15
1.10
1.10
1.05
1.05
Normalized
1.15
1.00
0.95
120
−20
0
25
50
75
Temperature (°C)
100
120
Figure 25. ILINE vs. Temperature
1.00
0.95
0.90
0.90
0.85
0.85
0.80
0.80
−40
1.20
−20
0
25
50
75
Temperature (°C)
100
120
1.05
1.00
0.95
0.90
0.85
−20
0
25
50
Temperature (°C)
75
−20
0
25
50
75
100 120
Figure 27. Dead Time (DT = 150 ns)
vs. Temperature
1.10
0.80
−40
−40
Temperature (°C)
Figure 26. VFI vs. Temperature
1.15
Normalized
100
1.00
0.85
0
25
50
75
Temperature (°C)
0.95
0.90
−20
0
1.05
0.90
0.80
−40
−20
Figure 23. VOVP vs. Temperature
1.20
Normalized
Normalized
1.00
0.95
0.90
0.80
−40
Normalized
1.05
100
120
Figure 28. Dead Time (DT = 350 ns) vs. Temperature
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FAN7631
FUNCTIONAL DESCRIPTION
Internal Oscillator
around 10 nF in parallel with the RDT. As a protective
measure against abnormal conditions, such as DT pin
short−to−ground and lift open, shuntresistor and series
resistor RDT,Short and RDT,Open are internally connected to
the DT pin. Even when this pin is shorted to ground and
lifted open, the dead time is limited to 50 ns (short to ground)
and 1000 ns (lifted open). Since the internal resistors have
relatively large tolerance, it is recommended to set the dead
time between 150 ns and 600 ns to minimize the dead time
variation by the internal resistor tolerance.
Figure 29 shows the simplified circuit of internal
current−controlled oscillator and typical circuit
configuration for the RT pin. Internally, the voltage on the
RT pin is regulated at 2 V by the V/I converter. The
charging / discharging current for the oscillator capacitor,
CT, is obtained by mirroring the current flowing out of the
RT pin (ICTC). By comparing the capacitor voltage with VTH
and VTL and driving S/R flip−flop with the comparator
outputs, the clock signal is obtained. Thus, the switching
frequency increases as the RT pin current increases.
As can be seen in Figure 29, an opto−coupler transistor is
typically connected to the RT pin through Rmax to modulate
the switching frequency. During an overload condition, the
opto−coupler is fully turned off and ICTC is solely
determined by Rmin, which sets the minimum frequency.
Meanwhile, the maximum switching frequency is obtained
when the opto−coupler is fully turned on. Considering the
typical saturation voltage of opto−transistor (0.2 V), the
maximum frequency can be obtained by Rmax and Rmin as:
f max +
ǒ
11, 6 kW
R min
11, 6 kW
R min
)
HO Output
LO Output
Figure 30. Gate Driving Signals
50 kHz
Ǔ
10.4 kW
R max
(eq. 1)
VTH = VSS_END
VREF
ICTC
ICTC
VCT
2ICTC
Rmax
V/I Converter
Rmin
2V
2
RT
CT
S Q
VTH
VTL
time
600
50 kHz
Dead Time (ns)
f min +
Dead Time
R −Q
500
400
300
200
100
F/F
0
Clock
0
10
20
30
40
50
60
RDT, Dead Time Resistor (kW)
Freq.
Divider Gate
Drive
Figure 31. Dead Time vs. RDT
Soft−Start
Figure 29. Current−Controlled Oscillator
Since the voltage gain of the resonant converter is
inversely proportional to the switching frequency, the
soft−start is implemented by sweeping down the switching
frequency from a high initial frequency until the output
voltage is established. The current−steering circuit
connected to SS pin adaptively changes the sinking and
sourcing current of the SS pin to set soft−start time, OLP
shutdown delay, and restart time. As illustrated in Figure 32,
the sourcing current, ISS1 (3 mA), is enabled at the beginning
of startup, which rapidly raises VSS up to VSS_START
(1.6 V). Then the sourcing current is switched to ISS2
(30 mA) and gate drive signals are enabled. Due to the small
value of ISS2, the SS pin voltage slowly rises, allowing slow
decrease of the switching frequency.
To minimize the frequency variation while the output
capacitance of the opto−transistor is charged up, softstart is
Gate Driver and Dead Time Programming
The FAN7631 employs a gate drive circuit with high
driving capability (source: 0.5 A / sink: 1 A) to cover a wide
variety of applications. The two gate drive signals (LO and
HO) are complimentary; each signal has 50% duty cycle,
including the dead time, as shown in Figure 30.
The dead time can be programmed by the resistor, RDT, as
shown in Figure 31. Internally, the voltage on the DT pin is
regulated at 1.4 V by the V/I converter and IDT programs the
dead time using RDT. To improve the noise immunity of the
dead time circuit, a sample−and−hold circuit is internally
employed. However, severe noises in a high−power
application can affect the dead time circuit operation and it
is therefore recommended to use a bypass capacitor of
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11
FAN7631
delayed until the CON pin voltage (opto−coupler transistor
voltage) reaches the RT pin voltage. Thus, the initial
switching frequency is not affected by Rmax and is solely
determined as six times the minimum switching frequency
set by Rmin as in Equation 1. The maximum switching
frequency is also internally limited at 600 kHz.
When VSS reaches VSS_END (4.2 V), soft−start ends.
Then, the high threshold of VCT comparator, VTH, is
clamped at VSS_END while VSS keeps increasing until it
reaches VSSC (5 V). The soft−start time is given as:
t SS + C SS
2.6
3
Capacitive Sensing Method
The MOSFET drain current can be sensed using an
additional capacitor in parallel with the resonant capacitor,
as shown in Figure 34. While the low−side switch is turned
on, the current, ICB, through CB introduces VSENSE across
RSENSE. The ICB is a fraction of the transformer
primary−side current, Ip, determined by the current divider
with capacitors Cr and CB as:
i CB +
VSSC (5 V)
tSS
Cr ) CB
VSS_END (4.2 V)
Slow rising of VSS by ISS2
R D ¦¦
VSS_START
(1.6 V)
CB
Cr
ip
(eq. 3)
1
2pf SC B
(eq. 4)
Then, VSENSE can be obtained as:
V Sense +
VTL
Fast rising of VSS by ISS1
Oscillator timing capacitor voltage (VCT)
ip ^
Generally, 1/100~1/1000 is adequate for the ratio of
CB/Cr. RD is used as a damper for reducing noise generated
by the switching transition. To prevent the damping resistor
from affecting the current divider ratio, the resistor should
be much smaller than the impedance of CB at the switching
frequency, calculated as:
(eq. 2)
10 *5
CB
CB
Cr
(eq. 5)
R sensei p
Gate drive signal (LO)
Figure 32. Soft−Start Waveforms
Current Sensing
FAN7631 employs a negative voltage sensing method to
sense the drain current of the MOSFET. This allows sensing
the current without a leading edge spike caused by the
low−side MOSFET’s driving current. Therefore, the
resistive−sensing method requires only a small RC filter.
The capacitive−sensing method is also available.
Ns
CFilter
Resistive Sensing Method
The FAN7631 can sense the drain current as a negative
voltage, as shown in Figure 33. An RC filter with a time
constant of 1/30~1/10 of the operating period is typical.
FAN7631
VCS
Protection Circuit
The FAN7631 has several self−protective functions:
Overload Protection (OLP), Over−Current Protection
(OCP), level−change OCP, Abnormal Over−Current
Protection (AOCP), Over−Voltage Protection (OVP),
Thermal Shutdown (TSD), Fault Input (FI), and Line
Under−Voltage Lockout (LUVLO or also called brownout).
Level−change OCP, OLP, OCP, OVP, and LUVLO are
Auto−Restart Mode protections while AOCP, TSD, and
fault input are Latch Mode protections.
Once auto−restart protection is triggered, switching is
instantly terminated and the MOSFETs remain off. Then the
FAN7631 keeps attempting to restart after the restart delay
until the protection situation is removed. When a Latch
HO
Cr
CTR
Np
Ns
LO
CS
SG
PG
CB
Figure 34. Capacitive Sensing
VCS
Filter
VSENSE
RSENSE
Ids
CDL
Ns
RD
RFilter
Ns
RSENSE
Figure 33. Resistive Sensing
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12
FAN7631
Abnormal Over−Current Protection (AOCP)
Mode protection is triggered, the FAN7631 remains off until
LVCC drops to VLR (5 V) and then rises above LVCC,START
(12.5 V).
If the secondary−side rectifier diodes are shorted, a large
current with extremely high di/dt can flow through the
MOSFET before OCP is triggered. AOCP is triggered with
a short blanking time of 50 ns, tBAO, when the sensed voltage
drops below −1.10 V, terminating the switching operation.
Once the protection is triggered, VSS is discharged by an
internal switch. Since it is a Latch Mode protection, the
protection is reset when LVCC drops to VLR (5 V).
Overload Protection (OLP)
When the sensed voltage on the CS pin drops below VOLP
(−0.37 V) for more than OLP blanking time, tBOL (200 ns),
CSS starts to be discharged by sinking current IOLP. If the
sensed voltage on the CS pin does not drop below VOLP in
the next switching cycle, the current on the SS pin is
switched to charging current ISS1, restoring VSS as
illustrated in Figure 35. If the CS pin voltage drops below
VOLP for in next consecutive switching cycle until CSS
voltage, VSS, reaches VSS_START (1.6 V); OLP is triggered
and the gate drive signals remain off. Once the OLP is
triggered, FAN7631 repeats charging and discharging CSS
four times, then restarts. The OLP delay, tOLP, and self
auto−restart time, tAR, are given as:
t OLP + C SS
t AR + 8
3.4
C SS
2.6
3
VCS
VSS
VSS_END
(eq. 6)
10 *5
3
VOLP (−0.37 V)
VOCP (−0.56 V)
VAOCP (−1.1 V)
VSS_START
(eq. 7)
10 *5
Figure 37. Abnormal Over−Current Protection (AOCP)
Level−Change Over−Current Protection (OCP)
Even with soft−start, there can be large overshoot current
for the initial several switching cycles until the resonant
capacitor voltage reaches its steady−state value. To prevent
the startup failure by OCP, the OCP threshold is changed to
VAOCP level while the Latch Mode AOCP is disabled during
soft−start.
VOLP (−0.37 V)
VCS
tOLP
VOCP (−0.56 V)
VSS
VSS_END
VSS_START
Figure 35. Overload Protection (OLP)
VOCP (−0.56 V)
Over−Current Protection (OCP)
When the CS pin voltage drops below VOCP (−0.54 V) for
longer than the OCP blanking time, tBO (200 ns), OCP is
triggered, terminating switching operation. Then, FAN7631
repeats charging and discharging CSS four times before
restarting.
VCS
VSS
VAOCP (−1.1 V)
VSSC
VSS_START
Figure 38. Level Change OCP
Over−Voltage Protection (OVP)
When the LVCC reaches 23 V, OVP is triggered. This
protection is used when auxiliary winding of the transformer
is utilized to supply VCC to the FAN7631.
VOLP (−0.37 V)
VCS
VOCP (−0.56 V)
Thermal Shutdown (TSD)
The thermal shutdown function is integrated to detect
abnormal over−temperature, such as abnormal ambient
temperature rising or over−driving of gate drive circuit. If
the junction temperature exceeds TSD (130°C), thermal
shutdown is triggered in Latch Mode.
VSS
VSS_END
VSS_START
Figure 36. Over−Current Protection (OCP)
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13
FAN7631
Mode protection, the FI pin is used, which stops the
switching immediately once the voltage on FI pin is pulled
above VFI (4 V) using an opto−coupler. To configure an
external protection with Auto−Restart Mode, an
optocoupler can be used on the LS pin. When voltage on the
LS pin is pulled below VLINE (3 V), line UVLO is triggered.
When LS pin voltage is pulled HIGH, above 3 V, FAN7631
starts up softly.
Line−UVLO
FAN7631 includes a precise line−UVLO (or brownout)
function with programmable hysteresis voltage, as can be
seen in Figure 39. When the line voltage is recovered, it
starts up with soft−start, as shown in Figure 39. A hysteresis
voltage between the start and stop voltage is programmable
by ILINE and external resistor R1. In normal operation, the
comparator’s output is HIGH and ILINE is disabled ILINE is
activated when the comparator’s output is LOW,
introducing hysteresis.
If necessary, CFilter can be used to reduce noise
interference. Generally, hundreds of pico−farad to tens of
nano−farad is adequate depending on the level of noise.
LVCC
External
Protection
VFI
FI
6
DC−link
Pulled Down −
Stop Switching with Latch
Rbias
R1
LS
CFilter
2
ILINE
R2
Line
Sensing
Resistor
Line Good
External
Protection
VLINE
DC−link
R1
LS
Pulled Down −
Stop Switching with A/R
LINE OK
8
VLINE
ILINE
R2
Figure 39. Line−UVLO
Figure 41. External Protection Circuits
(Top: Latch Mode, Bottom: A/R Mode)
VCS
VLS
Skip Cycle Operation
Hysteresis
The FAN7631 provides the pulse−skip function to prevent
the switching frequency from increasing too much at noload
condition. Figure 42 shows the internal block diagram for
the control (CON) pin and its external configuration. The
CON pin is typically connected to the collector terminal of
the opto−coupler and the FAN7631 stops switching when
the CON pin voltage drops below 0.4 V. FAN7631 resumes
switching when the CON pin voltage rises above 0.6 V. The
frequency that causes pulse skipping is given as:
3V
VLINE
VSS
VSS_END
VSS_START
f SKIP +
Figure 40. Line UVLO Waveforms
The DC link input−voltages for start and stop are
calculated as:
V DL, STOP + V LINE
Rmax
R1
5.8 kW
R min
)
Rmin
(eq. 8)
Ǔ
4.6 kW
R max
Current Controlled
Oscillator
R1 ) R2
R2
V DL, START + V DL, STOP ) I LINE
ǒ
100 kHz
50% Duty Cycle
CON
0.6 V/0.4 V
DT
H
L
0.4 V 0.6 V
Simple Remote−On/Off
The power stage can be shut down with Latch Mode or
Auto−Restart Mode, as shown in Figure 41. For the Latch
Figure 42. Pulse−Skipping Circuit
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14
(eq. 9)
Gate Driver
FAN7631
PCB Layout Guideline
Figure 43 shows the PCB layout guideline to minimize the
usage of jumpers. Good PCB layout improves power system
efficiency and reliability and minimizes EMI. The Power
Ground (PG) and Signal Ground (SG) should meet at a
single point. Jumpers should be avoided, especially for the
ground trace.
Lm
LIk
Cr
VIN
CDC−link
LVCC
Power Ground
Signal Ground
Signal Ground
Figure 43. PCB Layout Guideline
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15
FAN7631
TYPICAL APPLICATION CIRCUIT
(Half−Bridge LLC Resonant Converter)
Application
Device
Input Voltage Range
Rated Output Power
Output Voltage
(Rated Current)
LCD TV
FAN7631
400 V (20 ms Hold−Up Time)
192 W
24 V−8 A
Features
• High efficiency ( >94% at 400 VDC input).
• Reduced EMI noise through zero−voltage−switching (ZVS).
• Enhanced system reliability with various protection functions.
.
.
.
.
.
.
Figure 44. Typical Application Circuit
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16
FAN7631
TYPICAL APPLICATION CIRCUIT (continued)
• Core: EER3542 (Ae = 107 mm2)
• Bobbin: EER3542 (Horizontal)
Usually, the LLC resonant converter requires large
leakage inductance value. To obtain a large leakage
inductance, sectional winding method is used.
EER3542
1
16
Np
2.5mm
NS2
15mm
13
12
8mm
Np
Ns2
NS1
8
Ns1
9
Figure 45. Winding Specifications
Table 1. WINDING SPECIFICATIONS
Pin (S " F)
Wire
Turns
Winding Method
Np
8→1
0.12 f → 30 (Litz Wire)
45
Section Winding
NS1
12 → 9
0.1 f → 100 (Litz Wire)
5
Section Winding
NS2
16 → 13
0.1 f → 100 (Litz Wire)
5
Section Winding
Pin
Specifications
Remark
Primary−Side Inductance (LP)
1−8
630 mH ±5%
100 kHz, 1 V
Primary−Side Effective Leakage (LR)
1−8
145 mH ±5%
Short One of the Secondary Windings
ORDERING INFORMATION
Part Number
Operating Temperature Range
Package
Shipping†
FAN7631SJX
−40°C ~ 130°C
16−Lead, Small−Outline Package (SOP)
2000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
www.onsemi.com
17
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SOP16
CASE 565BF
ISSUE O
DOCUMENT NUMBER:
DESCRIPTION:
98AON13763G
SOP16
DATE 31 DEC 2016
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 1
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