FCH040N65S3
MOSFET – Power,
N-Channel, SUPERFET) III,
Easy Drive
650 V, 65 A, 40 mW
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Description
SUPERFET III MOSFET is ON Semiconductor’s brand−new high
voltage super−junction (SJ) MOSFET family that is utilizing charge
balance technology for outstanding low on−resistance and lower gate
charge performance. This advanced technology is tailored to minimize
conduction loss, provides superior switching performance, and
withstand extreme dv/dt rate.
Consequently, SUPERFET III MOSFET Easy drive series helps
manage EMI issues and allows for easier design implementation.
Features
•
•
•
•
•
•
700 V @ TJ = 150°C
Typ. RDS(on) = 35.4 mW
Ultra Low Gate Charge (Typ. Qg = 136 nC)
Low Effective Output Capacitance (Typ. Coss(eff.) = 1154 pF)
100% Avalanche Tested
These Devices are Pb−Free and are RoHS Compliant
VDSS
RDS(ON) MAX
ID MAX
650 V
40 mW @ 10 V
65 A
D
G
S
POWER MOSFET
Applications
• Telecom / Server Power Supplies
• Industrial Power Supplies
• UPS / Solar
G
D S
TO−247 LONG LEADS
CASE 340CH
MARKING DIAGRAM
$Y&Z&3&K
FCH
040N65S3
$Y
&Z
&3
&K
FCH040N65S3
= ON Semiconductor Logo
= Assembly Plant Code
= Data Code (Year & Week)
= Lot
= Specific Device Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2017
August, 2019 − Rev. 5
1
Publication Order Number:
FCH040N65S3/D
FCH040N65S3
ABSOLUTE MAXIMUM RATINGS (TC = 25°C, Unless otherwise noted)
Symbol
Parameter
VDSS
Drain to Source Voltage
VGSS
Gate to Source Voltage
ID
Drain Current
FCH040N65S3−F155
Unit
650
V
− DC
±30
V
− AC (f > 1 Hz)
±30
− Continuous (TC = 25°C)
65
− Continuous (TC = 100°C)
41
IDM
Drain Current
162.5
A
EAS
Single Pulsed Avalanche Energy (Note 2)
358
mJ
IAS
Avalanche Current (Note 2)
8.1
A
EAR
Repetitive Avalanche Energy (Note 1)
4.17
mJ
dv/dt
MOSFET dv/dt
100
V/ns
Peak Diode Recovery dv/dt (Note 3)
20
PD
TJ, TSTG
TL
− Pulsed (Note 1)
A
Power Dissipation
(TC = 25°C)
417
W
− Derate Above 25°C
3.33
W/°C
−55 to +150
°C
300
°C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering, 1/8″ from Case for 5 seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Repetitive rating: pulse width limited by maximum junction temperature.
2. IAS = 8.1 A, RG = 25 W, starting TJ = 25°C.
3. ISD ≤ 32.5 A, di/dt ≤ 200 A/ms, VDD ≤ 400 V, starting TJ = 25°C.
THERMAL CHARACTERISTICS
Symbol
Parameter
FCH040N65S3−F155
Unit
_C/W
RqJC
Thermal Resistance, Junction to Case, Max.
0.3
RqJA
Thermal Resistance, Junction to Ambient, Max.
40
PACKAGE MARKING AND ORDERING INFORMATION
Part Number
Top Marking
Package
Packing Method
Reel Size
Tape Width
Quantity
FCH040N65S3−F155
FCH040N65S3
TO−247 G03
Tube
N/A
N/A
30 Units
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
VGS = 0 V, ID = 1 mA, TJ = 25_C
650
−
−
V
VGS = 0 V, ID = 1 mA, TJ = 150_C
700
−
−
V
OFF CHARACTERISTICS
BVDSS
Drain to Source Breakdown Voltage
DBVDSS / DTJ
Breakdown Voltage Temperature
Coefficient
ID = 1 mA, Referenced to 25_C
−
0.64
−
V/_C
IDSS
Zero Gate Voltage Drain Current
VDS = 650 V, VGS = 0 V
−
−
1
mA
VDS = 520 V, TC = 125_C
−
4.5
−
VGS = ±30 V, VDS = 0 V
−
−
±100
nA
IGSS
Gate to Body Leakage Current
ON CHARACTERISTICS
VGS(th)
Gate Threshold Voltage
VGS = VDS, ID = 1.7 mA
2.5
−
4.5
V
RDS(on)
Static Drain to Source On Resistance
VGS = 10 V, ID = 32.5 A
−
35.4
40
mW
Forward Transconductance
VDS = 20 V, ID = 32.5 A
−
46
−
S
gFS
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2
FCH040N65S3
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) (continued)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
−
4740
−
pF
−
120
−
pF
DYNAMIC CHARACTERISTICS
VDS = 400 V, VGS = 0 V, f = 1 MHz
Ciss
Input Capacitance
Coss
Output Capacitance
Coss(eff.)
Effective Output Capacitance
VDS = 0 V to 400 V, VGS = 0 V
−
1154
−
pF
Coss(er.)
Energy Related Output Capacitance
VDS = 0 V to 400 V, VGS = 0 V
−
171
−
pF
Total Gate Charge at 10 V
VDS = 400 V, ID = 32.5 A, VGS = 10 V
(Note 4)
−
136
−
nC
−
33
−
nC
−
59
−
nC
f = 1 MHz
−
0.7
−
W
VDD = 400 V, ID = 32.5 A,
VGS = 10 V, Rg = 3.3 W
(Note 4)
−
35
−
ns
−
51
−
ns
Qg(tot)
Qgs
Gate to Source Gate Charge
Qgd
Gate to Drain “Miller” Charge
ESR
Equivalent Series Resistance
SWITCHING CHARACTERISTICS
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
Turn-Off Delay Time
−
95
−
ns
Turn-Off Fall Time
−
30
−
ns
Maximum Continuous Drain to Source Diode Forward Current
−
−
65
A
ISM
Maximum Pulsed Drain to Source Diode Forward Current
−
−
162.5
A
VSD
Drain to Source Diode Forward Voltage
VGS = 0 V, ISD = 32.5 A
−
−
1.2
V
trr
Reverse Recovery Time
−
534
−
ns
Qrr
Reverse Recovery Charge
VGS = 0 V, ISD = 32.5 A,
dIF/dt = 100 A/ms
−
13.6
−
mC
tf
SOURCE-DRAIN DIODE CHARACTERISTICS
IS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Essentially independent of operating temperature typical characteristics.
TYPICAL PERFORMANCE CHARACTERISTICS
300
200
100
ID, Drain Current (A)
ID, Drain Current (A)
VGS = 10.0 V
8.0 V
100
7.0 V
6.5 V
6.0 V
5.5 V
10
1
0.2
250 ms Pulse Test
TC = 25°C
1
10
VDS, Drain−Source Voltage (V)
150°C
25°C
10
1
20
Figure 1. On−Region Characteristics
−55°C
VDS = 20 V
250 ms Pulse Test
3
4
5
6
7
8
VGS, Gate−Source Voltage (V)
Figure 2. Transfer Characteristics
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3
9
FCH040N65S3
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
1000
IS, Reverse Drain Current (A)
RDS(ON), Drain−Source
On−Resistance (W)
0.06
0.05
0.04
VGS = 10 V
VGS = 20 V
0.03
0.02
0.01
TC = 25°C
0
60
120
ID, Drain Current (A)
100
10
1
0.01
0.001
0.0
180
5
0.5
1.0
1.5
VSD, Body Diode Forward Voltage (V)
10
VGS, Gate−Source Voltage (V)
Ciss
4
10
Capacitances (pF)
VGS = 0 V
250 ms Pulse Test
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current and
Temperature
10
3
10
Coss
2
10
1
VGS = 0 V
f = 1 MHz
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
10
0
10
−1
−1
10
Crss
2
1
10
10
VDS, Drain−Source Voltage (V)
8
VDS = 130 V
6
2
0
3
10
1.0
0.9
−50
0
50
100
Qg, Total Gate Charge (nC)
150
3.0
VGS = 0 V
ID = 10 mA
1.1
0.8
ID = 32.5 A
Figure 6. Gate Charge Characteristics
RDS(on), Drain−Source
On−Resistance (Normalized)
1.2
VDS = 400 V
4
Figure 5. Capacitance Characteristics
BVDSS, Drain−Source
Breakdown Voltage (Normalized)
25°C
0.1
Figure 3. On−Resistance Variation vs.
Drain Current and Gate Voltage
10
150°C
2.5
2.0
1.5
1.0
0.5
0.0
50
100
150
0
TJ, Junction Temperature (5C)
VGS = 10 V
ID = 32.5 A
−50
0
50
100
150
TJ, Junction Temperature (5C)
Figure 8. On−Resistance Variation
vs. Temperature
Figure 7. Breakdown Voltage Variation
vs. Temperature
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4
FCH040N65S3
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
80
30 ms
100 ms
1 ms
DC
10
ID, Drain Current (A)
ID, Drain Current (A)
200
100
10 ms
Operation in this Area
is Limited by RDS(on)
1
0.1
0.01
TC = 25°C
TJ = 150°C
Single Pulse
1
10
100
VDS, Drain−Source Voltage (V)
60
40
20
0
25
1000
Figure 9. Maximum Safe Operating Area
50
75
100
125
TC, Case Temperature (5C)
Figure 10. Maximum Drain Current
vs. Case Temperature
30
EOSS, (mJ)
25
20
15
10
5
0
0
130
260
390
520
VDS, Drain to Source Voltage (V)
650
r(t), Normalized Effective Transient
Thermal Resistance
Figure 11. EOSS vs. Drain to Source Voltage
2
1
0.1
DUTY CYCLE − DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
0.01
0.001
−5
10
−4
t2
ZqJC(t) = r(t) x RqJC
RqJC = 0.3°C/W
Peak TJ = PDM x ZqJC(t) + TC
Duty Cycle, D = t1 / t2
SINGLE PULSE
10
−3
10
150
−2
−1
10
10
t, Rectangular Pulse Duration (sec)
Figure 12. Transient Thermal Response Curve
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5
0
10
1
10
FCH040N65S3
VGS
RL
Qg
VDS
VGS
Qgs
Qgd
DUT
IG = Const.
Charge
Figure 13. Gate Charge Test Circuit & Waveform
RL
VDS
VDS
90%
90%
90%
VDD
VGS
RG
VGS
DUT
VGS
10%
td(on)
10%
tr
td(off)
ton
tf
toff
Figure 14. Resistive Switching Test Circuit & Waveforms
L
E AS + 1 @ LI AS
2
VDS
BVDSS
ID
IAS
RG
VDD
DUT
VGS
2
ID(t)
VDD
VDS(t)
tp
tp
Figure 15. Unclamped Inductive Switching Test Circuit & Waveforms
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6
Time
FCH040N65S3
+
DUT
VDS
−
ISD
L
Driver
RG
Same Type
as DUT
VGS
− dv/dt controlled by RG
− ISD controlled by pulse period
D+
VGS
(Driver)
VDD
Gate Pulse Width
Gate Pulse Period
10 V
IFM, Body Diode Forward Current
ISD
(DUT)
di/dt
IRM
Body Diode Reverse Current
Body Diode Recovery dv/dt
VDS
(DUT)
VDD
VSD
Body Diode
Forward Voltage Drop
Figure 16. Peak Diode Recovery dv/dt Test Circuit & Waveforms
SUPERFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or
other countries.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−247−3LD
CASE 340CH
ISSUE A
DATE 09 OCT 2019
GENERIC
MARKING DIAGRAM*
XXXXXXXXX
AYWWG
XXXX
A
Y
WW
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13853G
TO−247−3LD
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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