MOSFET – N-Channel,
SUPERFET) II
800 V, 58 A, 60 mW
FCH060N80
Description
SUPERFET II MOSFET is ON Semiconductor’s brand−new high
voltage super−junction (SJ) MOSFET family that is utilizing charge
balance technology for outstanding low on−resistance and lower gate
charge performance. This technology is tailored to minimize
conduction loss, provide superior switching performance, dv/dt rate
and higher avalanche energy. Consequently, SUPERFET II MOSFET
is very suitable for the switching power applications such as PFC,
server/telecom power, FPD TV power, ATX power and industrial
power applications.
Features
•
•
•
•
•
•
•
Typ. RDS(on) = 54 mW
850 V @ TJ = 150°C
Ultra Low Gate Charge (Typ. Qg = 270 nC)
Low EOSS (Typ. 23 mJ @ 400 V)
Low Effective Output Capacitance (Typ. Coss(eff.) = 981 pF)
100% Avalanche Tested
This Device is RoHS Compliant
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VDSS
RDS(ON) MAX
ID MAX
800 V
60 mW @ 10 V
58 A
D
G
S
POWER MOSFET
Applications
• AC−DC Power Supply
• LED Lighting
G
D
S
TO−247−3LD
CASE 340CH
MARKING DIAGRAM
$Y&Z&3&K
FCH060N80
$Y
&Z
&3
&K
FCH060N80
= ON Semiconductor Logo
= Assembly Plant Code
= Numeric Date Code
= Lot Code
= Specific Device Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
November, 2020 − Rev. 4
1
Publication Order Number:
FCH060N80/D
FCH060N80
ABSOLUTE MAXIMUM RATINGS (TC = 25°C, Unless otherwise noted)
Symbol
Parameter
VDSS
Drain to Source Voltage
VGSS
Gate to Source Voltage
ID
Drain Current
Value
Unit
800
V
DC
±20
V
AC (f > 1 Hz)
±30
Continuous (TC = 25°C)
58
Continuous (TC = 100°C)
36.8
IDM
Drain Current
174
A
EAS
Single Pulsed Avalanche Energy (Note 2)
2317
mJ
IAS
Avalanche Current (Note 1)
11.6
A
EAR
Repetitive Avalanche Energy (Note 1)
50
mJ
dv/dt
MOSFET dv/dt
100
V/ns
Peak Diode Recovery dv/dt (Note 3)
20
PD
Pulsed (Note 1)
A
Power Dissipation
(TC = 25°C)
Derate Above 25°C
TJ, TSTG
TL
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering Purpose
1/8″ from Case for 5 seconds
500
W
4
W/°C
−55 to +150
°C
300
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Repetitive rating: pulse width limited by maximum junction temperature.
2. IAS = 11.6 A, VDD = 50 V, RG = 25 W, starting TJ = 25°C.
3. ISD ≤ 58 A, di/dt ≤ 200 A/ms, VDD ≤ BVDSS, starting TJ = 25°C.
THERMAL CHARACTERISTICS
Symbol
Parameter
Value
Unit
RqJC
Thermal Resistance, Junction to Case, Max.
0.25
_C/W
RqJA
Thermal Resistance, Junction to Ambient, Max.
40
PACKAGE MARKING AND ORDERING INFORMATION
Part Number
Top Mark
Package
Packing
Method
Reel Size
Tape Width
Quantity
FCH060N80−F155
FCH060N80
TO−247−3LD
Tube
N/A
N/A
30 Units
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2
FCH060N80
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
OFF CHARACTERISTICS
Drain to Source Breakdown Voltage
VGS = 0 V, ID = 1 mA, TJ = 25_C
DBVDSS / DTJ
Breakdown Voltage Temperature
Coefficient
ID = 1 mA, Referenced to 25_C
IDSS
Zero Gate Voltage Drain Current
VDS = 800 V, VGS = 0 V
25
VDS = 640 V, TC = 125_C
250
VGS = ±20 V, VDS = 0 V
±100
nA
4.5
V
60
mW
BVDSS
IGSS
Gate to Body Leakage Current
800
V
0.8
V/_C
mA
ON CHARACTERISTICS
VGS(th)
Gate Threshold Voltage
VGS = VDS, ID = 5.8 mA
RDS(on)
Static Drain to Source On Resistance
VGS = 10 V, ID = 29 A
54
Forward Transconductance
VDS = 20 V, ID = 29 A
68
gFS
2.5
S
DYNAMIC CHARACTERISTICS
VDS = 100 V, VGS = 0 V, f = 1 MHz
Ciss
Input Capacitance
11040
14685
pF
Coss
Output Capacitance
298
395
pF
Crss
Reverse Transfer Capacitance
10
pF
Coss
Output Capacitance
VDS = 480 V, VGS = 0 V, f = 1MHz
147
pF
Effective Output Capacitance
VDS = 0 V to 480 V, VGS = 0 V
981
pF
Total Gate Charge at 10 V
VDS = 640 V, ID = 58 A, VGS = 10 V
(Note 4)
270
f = 1 MHz
Coss(eff.)
Qg(tot)
Qgs
Gate to Source Gate Charge
Qgd
Gate to Drain “Miller” Charge
ESR
Equivalent Series Resistance
350
nC
54
nC
100
nC
0.78
W
SWITCHING CHARACTERISTICS
td(on)
Turn-On Delay Time
tr
Turn-On Rise Time
td(off)
VDD = 400 V, ID = 58 A, VGS = 10 V
Rg = 4.7 W
(Note 4)
55
120
ns
73
156
ns
Turn-Off Delay Time
213
436
ns
Turn-Off Fall Time
72
154
ns
Maximum Continuous Drain to Source Diode Forward Current
58
A
ISM
Maximum Pulsed Drain to Source Diode Forward Current
174
A
VSD
Drain to Source Diode Forward Voltage
VGS = 0 V, ISD = 58A
1.2
V
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
VGS = 0 V, ISD = 58 A,
dIF/dt = 100 A/ms
tf
SOURCE-DRAIN DIODE CHARACTERISTICS
IS
850
ns
35
mC
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Essentially independent of operating temperature typical characteristics.
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3
FCH060N80
TYPICAL PERFORMANCE CHARACTERISTICS
200
VDS = 20 V
250 ms Pulse Test
100
ID, Drain Current (A)
100
ID, Drain Current (A)
200
VGS = 10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
5.5 V
5.0 V
10
150°C
10
25°C
−55°C
1
0.1
250 ms Pulse Test
TC = 25°C
1
10
1
20
VDS, Drain−Source Voltage (V)
2
3
Figure 1. On−Region
Characteristics
VGS = 10 V
VGS = 20 V
0.06
0
40
80
120
160
1.2
1.5
10
150°C
1
25°C
0.1
0.01
0.001
0.0
200
0.3
0.6
0.9
VSD, Body Diode Forward Voltage (V)
Figure 4. Body Diode Forward Voltage
Variation vs. Source Current and
Temperature
Figure 3. On−Resistance Variation
vs. Drain Current and Gate Voltage
10
100000
Ciss
10000
VGS, Gate−Source Voltage (V)
Capacitances (pF)
7
250 ms Pulse Test
ID, Drain Current (A)
1000
Coss
100
VGS = 0 V
f = 1 MHz
10 C = C + C (C = shorted)
iss
gs
gd
ds
Coss = Cds + Cgd
Crss = Cgd
1
0.1
6
200
100 VGS = 0 V
TC = 25°C
0.08
0.04
5
Figure 2. Transfer
Characteristics
IS, Reverse Drain Current (A)
RDS(ON), Drain−Source
On−Resistance (W)
0.10
4
VGS, Gate−Source Voltage (V)
1
10
Crss
100
ID = 58 A
VDS = 160 V
VDS = 400 V
8
VDS = 640 V
6
4
2
0
800
0
60
120
180
240
VDS, Drain−Source Voltage (V)
Qg, Total Gate Charge (nC)
Figure 5. Capacitance
Characteristics
Figure 6. Gate Charge
Characteristics
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4
300
FCH060N80
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
BVDSS, Drain−Source
Breakdown Voltage (Normalized)
1.2
3.0
RDS(on), Drain−Source
On−Resistance (Normalized)
VGS = 0 V
ID = 1mA
1.1
1.0
0.9
0.8
−100
−50
0
50
100
150
2.4
1.8
1.2
0.6
0.0
−100
200
TJ, Junction Temperature (5C)
50
100
150
200
60
10 ms
100
50
ID, Drain Current (A)
100 ms
1 ms
10
DC
1
Operation in This Area
is Limited by RDS(on)
TC = 25 °C
TJ = 150 °C
Single Pulse
0.1
0.01
0.1
1
10
40
30
20
10
100
0
25
1000
Figure 9. Maximum Safe
Operating Area
48
36
24
12
160
320
480
640
75
100
125
150
Figure 10. Maximum Drain
Current vs. Case Temperature
60
0
50
TC, Case Temperature (5C)
VDS, Drain−Source Voltage (V)
EOSS, (mJ)
0
Figure 8. On−Resistance
Variation vs. Temperature
300
ID, Drain Current (A)
−50
TJ, Junction Temperature (5C)
Figure 7. Breakdown Voltage
Variation vs. Temperature
0
VGS = 10 V
ID = 29 mA
800
VDS, Drain to Source Voltage (V)
Figure 11. EOSS vs. Drain to
Source Voltage
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5
FCH060N80
Z qJC(t), Thermal Response (5C/W)
TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
0.3
0.5
0.1
0.2
0.1
P DM
0.05
0.01
t1
0.02
0.01
Single Pulse
t2
ZqJC(t) = 0.25 °C/W Max.
Duty Factor, D = t1/t2
1E−3
−5
10
TJM − TC = PDM * ZqJC(t)
−4
10
−3
−2
10
10
−1
10
t1, Rectangular Pulse Duration (sec)
Figure 12. Transient Thermal Response Curve
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6
0
10
FCH060N80
VGS
RL
Qg
10 V
VDS
VGS
Qgs
Qgd
DUT
1mA
Charge
Figure 13. Gate Charge Test Circuit & Waveform
VDS
RL
VDS
90%
90%
90%
VDD
VGS
RG
VGS
DUT
10 V
10%
td(on)
10%
tr
td(off)
ton
tf
toff
Figure 14. Resistive Switching Test Circuit & Waveforms
L
E AS + 1 @ LI 2
AS
2
VDS
BVDSS
ID
IAS
RG
VDD
DUT
10 V
ID(t)
VDD
VDS(t)
tp
tp
Figure 15. Unclamped Inductive Switching Test Circuit & Waveforms
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7
Time
FCH060N80
+
DUT
VDS
−
ISD
L
Driver
RG
Same Type
as DUT
VGS
− dv/dt controlled by RG
− ISD controlled by pulse period
D+
VGS
(Driver)
VDD
Gate Pulse Width
Gate Pulse Period
10 V
IFM, Body Diode Forward Current
ISD
(DUT)
di/dt
IRM
Body Diode Reverse Current
Body Diode Recovery dv/dt
VDS
(DUT)
VSD
VDD
Body Diode
Forward Voltage Drop
Figure 16. Peak Diode Recovery dv/dt Test Circuit & Waveforms
SUPERFET is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other
countries.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−247−3LD
CASE 340CH
ISSUE A
DATE 09 OCT 2019
GENERIC
MARKING DIAGRAM*
XXXXXXXXX
AYWWG
XXXX
A
Y
WW
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13853G
TO−247−3LD
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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