MOSFET – N-Channel,
SUPERFET) II
800 V, 46 A, 85 mW
FCH085N80
Description
SuperFET II MOSFET is ON Semiconductor’s brand−new high
voltage super−junction (SJ) MOSFET family that is utilizing charge
balance technology for outstanding low on−resistance and lower gate
charge performance. This technology is tailored to minimize
conduction loss, provide superior switching performance, dv/dt rate
and higher avalanche energy. Consequently, SuperFET II MOSFET is
very suitable for the switching power applications such as PFC,
server/telecom power, FPD TV power, ATX power and industrial
power applications.
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VDS
RDS(ON) MAX
ID MAX
800 V
85 mW @ 10 V
46 A
D
Features
•
•
•
•
•
•
•
Typ. RDS(on) = 67 mW
850 V @ TJ = 150°C
Ultra Low Gate Charge (Typ. Qg = 196 nC)
Low EOSS (Typ. 18 mJ @ 400 V)
Low Effective Output Capacitance (Typ. Coss(eff.) = 568 pF)
100% Avalanche Tested
These Devices are Pb−Free and are RoHS Compliant
G
S
N-CHANNEL MOSFET
Applications
• AC−DC Power Supply
• LED Lighting
TO−247−3LD
CASE 340CH
MARKING DIAGRAM
FCH085N80
AYWWG
FCH085N80
A
Y
WW
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2016
November, 2019 − Rev. 3
1
Publication Order Number:
FCH085N80/D
FCH085N80
ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Parameter
VDSS
Drain to Source Voltage
VGSS
Gate to Source Voltage
ID
Drain Current:
IDM
Drain Current:
EAS
Single Pulsed Avalanche Energy (Note 2)
IAS
Value
Unit
800
V
− DC
±20
V
− AC (f > 1 Hz)
±30
− Continuous (TC = 25°C)
46
− Continuous (TC = 100°C)
29
138
A
1701
mJ
Avalanche Current (Note 2)
9.2
A
EAR
Repetitive Avalanche Energy (Note 1)
4.4
mJ
dv/dt
MOSFET dv/dt
100
V/ns
Peak Diode Recovery dv/dt (Note 3)
20
PD
TJ, TSTG
TL
− Pulsed (Note 1)
A
Power Dissipation
(TC = 25°C)
446
W
Derate Above 25°C
3.5
W/°C
−55 to + 150
°C
300
°C
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering, 1/8″ from Case for 5 seconds
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Repetitive rating: pulse−width limited by maximum junction temperature.
2. IAS = 9.2 A, VDD = 50 V, RG = 25 W, starting TJ = 25 °C.
3. ISD ≤ 46 A, di/dt ≤ 200 A/ms, VDD ≤ BVDSS, starting TJ = 25 °C.
PACKAGE MARKING AND ORDERING INFORMATION
Part Number
Top Marking
Package
Packing Method
Reel Size
Tape Width
Quantity
FCH085N80−F155
FCH085N80
TO−247 G03
Tube
N/A
N/A
30 Units
THERMAL CHARACTERISTICS
Symbol
Parameter
FCH085N80−F155
Unit
°C/W
RqJC
Thermal Resistance, Junction to Case, Max.
0.28
RqJA
Thermal Resistance, Junction to Ambient, Max.
40.0
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2
FCH085N80
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
OFF CHARACTERISTICS
Drain to Source Breakdown Voltage
VGS = 0 V, ID = 1 mA, TJ = 25°C
800
−
−
V
DBVDSS
/DTJ
Breakdown Voltage Temperature
Coefficient
ID = 1 mA, Referenced to 25°C
−
0.8
−
V/°C
IDSS
Zero Gate Voltage Drain Current
VDS = 800 V, VGS = 0 V
−
−
25
mA
VDS = 640 V, VGS = 0 V, TC = 125 °C
−
−
250
VGS = ±20 V, VDS = 0 V
−
−
±100
BVDSS
IGSS
Gate to Body Leakage Current
nA
ON CHARACTERISTICS
VGS(th)
Gate Threshold Voltage
VGS = VDS, ID = 4.6 mA
2.5
−
4.5
V
RDS(on)
Static Drain to Source On Resistance
VGS = 10 V, ID = 23 A
−
67
85
mW
Forward Transconductance
VDS = 20 V, ID = 23 A
−
55
−
S
VDS = 100 V, VGS = 0 V, f = 1 MHz
−
8140
10825
pF
−
255
340
pF
gFS
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
−
10
−
pF
Coss
Output Capacitance
VDS = 480 V, VGS = 0 V, f = 1 MHz
−
1000
−
pF
Effective Output Capacitance
VDS = 0 V to 480 V, VGS = 0 V
−
728
−
pF
Total Gate Charge at 10 V
VDS = 640 V, ID = 46 A, VGS = 10 V
(Note 4)
−
196
255
nC
−
40
−
nC
−
72
−
nC
f = 1 MHz
−
0.8
−
W
VDD = 400 V, ID = 46 A,
VGS = 10 V, Rg = 4.7 W
(Note 4)
−
45
100
ns
−
55
120
ns
Coss(eff.)
Qg(tot)
Qgs
Gate to Source Gate Charge
Qgd
Gate to Drain “Miller” Charge
ESR
Equivalent Series Resistance
SWITCHING CHARACTERISTICS
td(on)
Turn-On Delay Time
tr
Turn−On Rise Time
td(off)
Turn-Off Delay Time
−
160
330
ns
Turn−Off Fall Time
−
35
80
ns
tf
DRAIN-SOURCE DIODE CHARACTERISTICS
Maximum Continuous Source to Drain Diode Forward Current
−
−
46
A
ISM
Maximum Pulsed Drain to Source Diode Forward Current
−
−
138
A
VSD
Drain to Source Diode Forward Voltage
VGS = 0 V, ISD = 46 A
−
−
1.2
V
trr
Reverse Recovery Time
−
800
−
ns
Qrr
Reverse Recovery Charge
VGS = 0 V, ISD = 46 A,
diF/dt = 100 A/ms
−
32
−
mC
IS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Essentially independent of operating temperature typical characteristics.
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3
FCH085N80
TYPICAL CHARACTERISTICS
Figure 2. Transfer Characteristics
Figure 1. On−Region Characteristics
Figure 4. Body Diode Forward Voltage Variation
vs. Source Current and Temperature
Figure 3. On−Resistance Variation vs. Drain
Current and Gate Voltage
Figure 6. Gate Charge Characteristics
Figure 5. Capacitance Characteristics
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4
FCH085N80
TYPICAL CHARACTERISTICS
Figure 7. Breakdown Voltage Variation vs.
Temperature
Figure 8. On−Resistance Variation vs.
Temperature
Figure 10. Maximum Drain Current vs. Case
Temperature
Figure 9. Maximum Safe Operating Area
Figure 11. Eoss vs. Drain to Source Voltage
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5
FCH085N80
TYPICAL CHARACTERISTICS
Figure 12. Transient Thermal Response Curve
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6
FCH085N80
VGS
RL
Qg
VDS
VGS
Qgs
Qgd
DUT
IG = Const.
Charge
Figure 13. Gate Charge Test Circuit & Waveform
RL
VDS
VDS
90%
90%
90%
VDD
VGS
RG
VGS
DUT
VGS
10%
td(on)
10%
tr
tf
td(off)
ton
toff
Figure 14. Resistive Switching Test Circuit & Waveforms
L
E AS + 1 @ LI AS
2
VDS
BVDSS
ID
IAS
RG
VDD
DUT
VGS
2
ID(t)
VDD
VDS(t)
tp
tp
Figure 15. Unclamped Inductive Switching Test Circuit & Waveforms
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7
Time
FCH085N80
+
DUT
VSD
−
ISD
L
Driver
RG
Same Type
as DUT
VGS
− dv/dt controlled by RG
− ISD controlled by pulse period
D+
VGS
(Driver)
VDD
Gate Pulse Width
Gate Pulse Period
10 V
IFM, Body Diode Forward Current
ISD
(DUT)
di/dt
IRM
Body Diode Reverse Current
Body Diode Recovery dv/dt
VDS
(DUT)
VDD
VSD
Body Diode
Forward Voltage Drop
Figure 16. Peak Diode Recovery dv/dt Test Circuit & Waveforms
SUPERFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or
other countries.
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8
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−247−3LD
CASE 340CH
ISSUE A
DATE 09 OCT 2019
GENERIC
MARKING DIAGRAM*
XXXXXXXXX
AYWWG
XXXX
A
Y
WW
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13853G
TO−247−3LD
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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