MOSFET – N-Channel,
SUPREMOS
600 V, 22 A, 165 mW
FCH22N60N
Description
The SUPREMOS® MOSFET is ON Semiconductor’s next
generation of high voltage super−junction (SJ) technology employing
a deep trench filling process that differentiates it from
the conventional SJ MOSFETs. This advanced technology and precise
process control provides lowest Rsp on−resistance, superior switching
performance and ruggedness. SUPREMOS MOSFET is suitable
for high frequency switching power converter applications such as
PFC, server/telecom power, FPD TV power, ATX power,
and industrial power applications.
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VDS
RDS(ON) MAX
ID MAX
600 V
165 m @ 10 V
22 A
D
Features
•
•
•
•
•
•
650 V @ TJ = 150°C
RDS(on) = 140 m (Typ.) @ VGS = 10 V, ID = 11 A
Ultra Low Gate Charge (Typ. Qg = 45 nC)
Low Effective Output Capacitance (Typ. Coss(eff.) = 196.4 pF)
100% Avalanche Tested
This Device is Pb−Free and is RoHS Compliant
G
S
N-CHANNEL MOSFET
Applications
• PDP TV
• Solar Inverter
• AC−DC Power Supply
G
D
S
TO−247−3LD
CASE 340CK
MARKING DIAGRAM
$Y&Z&3&K
FCH
22N60N
$Y
&Z
&3
&K
FCH22N60N
= ON Semiconductor Logo
= Assembly Plant Code
= Numeric Date Code
= Lot Code
= Specific Device Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2009
October, 2020 − Rev. 3
1
Publication Order Number:
FCH22N60N/D
FCH22N60N
ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
FCH22N60N
Unit
VDSS
Drain to Source Voltage
600
V
VGSS
Gate to Source Voltage
±30
V
− Continuous (TC = 25°C)
22
A
− Continuous (TC = 100°C)
13.8
ID
Parameter
Drain Current
IDM
Drain Current
EAS
IAR
66
A
Single Pulsed Avalanche Energy (Note 2)
672
mJ
Avalanche Current (Note 1)
7.3
A
EAR
Repetitive Avalanche Energy (Note 1)
2.75
mJ
dv/dt
MOSFET dv/dt
100
V/ns
Peak Diode Recovery dv/dt (Note 3)
20
PD
− Pulsed (Note 1)
Power Dissipation
(TC = 25°C)
− Derate above 25°C
TJ, TSTG
TL
Operating and Storage Temperature Range
205
W
1.64
W/°C
−55 to + 150
°C
300
°C
Maximum Lead Temperature for Soldering, 1/8″ from Case for 5 Second
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Repetitive Rating: Pulse width limited by maximum junction temperature.
2. IAS = 7.3 A, RG = 25 , starting TJ = 25 °C
3. ISD ≤ 22 A, di/dt ≤ 200 A/s, VDD ≤ 380 V, starting TJ = 25 °C
THERMAL CHARACTERISTICS
Symbol
Parameter
RJC
Thermal Resistance, Junction to Case, Max.
RJA
Thermal Resistance, Junction to Ambient, Max.
FCH22N60N
Unit
0.61
°C/W
40
PACKAGE MARKING AND ORDERING INFORMATION
Part Number
Top Mark
Package
Package Method
Reel Size
Tape Width
Quantity
FCH22N60N
FCH22N60N
TO−247−3LD
Tube
N/A
N/A
30 Units
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2
FCH22N60N
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
ID = 1 mA, VGS = 0 V, TJ = 25°C
600
−
−
V
ID = 1 mA, VGS = 0 V, TJ = 150°C
650
−
−
OFF CHARACTERISTICS
BVDSS
Drain to Source Breakdown Voltage
BVDSS
/ TJ
Breakdown Voltage Temperature
Coefficient
ID = 1 mA, Referenced to 25°C
−
0.68
−
V/°C
IDSS
Zero Gate Voltage Drain Current
VDS = 480 V, VGS = 0 V
−
−
10
A
VDS = 480 V, TJ = 125°C
−
−
100
VGS = ±50 V, VDS = 0 V
−
−
±100
nA
2.0
3
4.0
V
IGSS
Gate to Body Leakage Current
ON CHARACTERISTICS
VGS(th)
Gate Threshold Voltage
VGS = VDS, ID = 250 A
RDS(on)
Static Drain to Source On Resistance
VGS = 10 V, ID = 11 A
−
0.140
0.165
Forward Transconductance
VDS = 20 V, ID = 11 A
−
22
−
S
VDS = 100 V, VGS = 0 V,
f = 1 MHz
−
1950
−
pF
gFS
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Coss
Output Capacitance
Coss(eff.)
Qg(tot)
−
75.9
−
pF
−
3
−
pF
VDS = 380 V, VGS = 0 V, f = 1 MHz
−
43.2
−
pF
Effective Output Capacitance
VDS = 0 V to 480 V, VGS = 0 V
−
196.4
−
pF
Total Gate Charge at 10 V
VDS = 380 V, ID = 11 A,
VGS = 10 V
(Note 4)
−
45
−
nC
−
8.7
−
nC
−
14.5
−
nC
f = 1 MHz
−
1
−
VDD = 380 V, ID = 11 A,
RG = 4.7
(Note 4)
−
16.9
−
ns
−
16.7
−
ns
Qgs
Gate to Source Gate Charge
Qgd
Gate to Drain “Miller” Charge
ESR
Equivalent Series Resistance(G−S)
SWITCHING CHARACTERISTICS
td(on)
Turn-On Delay Time
tr
Turn−On Rise Time
td(off)
Turn-Off Delay Time
−
49
−
ns
Turn−Off Fall Time
−
4
−
ns
Maximum Continuous Drain to Source Diode Forward Current
−
−
22
A
ISM
Maximum Pulsed Drain to Source Diode Forward Current
−
−
66
A
VSD
Drain to Source Diode Forward Voltage
VGS = 0 V, ISD = 11 A
−
−
1.2
V
trr
Reverse Recovery Time
−
350
−
ns
Qrr
Reverse Recovery Charge
VGS = 0 V, ISD = 11 A,
dIF/dt = 100 A/s
−
6
−
C
tf
DRAIN-SOURCE DIODE CHARACTERISTICS
IS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Essentially Independent of Operating Temperature Typical Characteristics.
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3
FCH22N60N
TYPICAL CHARACTERISTICS
100
*Notes:
1. 250 s Pulse Test
2. TC = 25°C
VGS = 15.0 V
10.0 V
8.0 V
7.0 V
6.0 V
5.0 V
4.0 V
10
1
0.1
ID, Drain Current [A]
ID, Drain Current [A]
100
0.3
1
150°C
1
10
25°C
*Notes:
1. VDS = 20 V
2. 250 s Pulse Test
2
3
VDS, Drain−Source Voltage [V]
100
IS, Reverse Drain Current [A]
RDS(ON) [],
Drain−Source On−Resistance
0.4
0.3
VGS = 10 V
VGS = 20 V
0.1
10
20
30
40
50
150°C
1
0.0
60
Figure 3. On−Resistance Variation vs. Drain Current
and Gate Voltage
Ciss
1000
Crss
100
10
1
0.1
*Notes:
1. VGS = 0 V
2. f = 1 MHz
1
10
1.0
1.5
10
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
Coss
0.5
Figure 4. Body Diode Forward Voltage Variation
vs. Source Current and Temperature
VGS, Gate−Source Voltage [V]
Capacitance [pF]
10000
25°C
VSD, Body Diode Forward Voltage [V]
ID, Drain Current [A]
1E5
8
*Notes:
1. VGS = 0 V
2. 250 s Pulse Test
10
*Note: TC = 25°C
0
7
4
5
6
VGS, Gate−Source Voltage [V]
Figure 2. Transfer Characteristics
Figure 1. On−Region Characteristics
0.2
−55°C
10
100
6
4
2
0
600
VDS, Drain−Source Voltage [V]
VDS = 120 V
VDS = 300 V
VDS = 480 V
8
*Note: ID = 11 A
0
10
20
30
40
50
QG, Total Gate Charge [nC]
Figure 6. Gate Charge Characteristics
Figure 5. Capacitance Characteristics
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4
FCH22N60N
TYPICAL CHARACTERISTICS (continued)
3.0
RDS(ON), (Normalized)
Drain−Source On−Resistance
BVDSS, (Normalized)
Drain−Source Breakdown Voltage
1.2
1.1
1.0
0.9
0.8
−100
*Notes:
1. VGS = 0 V
2. ID = 1 mA
−50
0
50
100
150
2.5
2.0
1.5
1.0
*Notes:
1. VGS = 10 V
2. ID = 11 A
0.5
0.0
−100
200
−50
TJ, Junction Temperature [°C]
0.1
0.01
1
10
ID, Drain Current [A]
10 ms
DC
100
15
10
5
0
1000
50
25
75
100
Figure 10. Maximum Drain Current
vs. Case Temperature
Figure 9. Maximum Safe Operating Area
1
0.5
0.2
PDM
0.1
t1
0.05
0.02
0.01
t2
*Notes:
1. ZJC(t) = 0.61°C/W Max.
2. Duty Factor, D = t1/t2
3. TJM − TC = PDM * ZJC(t)
Single Pulse
0.01
10−5
10−4
125
TC, Case Temperature [°C]
VDS, Drain−Source Voltage [V]
0.1
200
20
*Notes:
1. TC = 25°C
2. TJ = 150°C
3. Single Pulse
ZJC(t), Thermal Response [°C/W]
ID, Drain Current [A]
1 ms
Operation in This Area
is Limited by RDS(on)
150
25
100 s
1
100
Figure 8. On−Resistance Variation
vs. Temperature
10 s
10
50
TJ, Junction Temperature [°C]
Figure 7. Breakdown Voltage Variation
vs. Temperature
100
0
10−3
10−2
10−1
t1, Rectangular Pulse Duration [sec]
Figure 11. Transient Thermal Response Curve
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5
1
10
150
FCH22N60N
VGS
RL
Qg
VDS
VGS
Qgs
Qgd
DUT
IG = const.
Charge
Figure 12. Gate Charge Test Circuit & Waveform
RL
VDS
VDS
90%
VDD
VGS
RG
VGS
DUT
VGS
10%
td(on)
td(off) t
f
tr
ton
toff
Figure 13. Resistive Switching Test Circuit & Waveforms
L
E AS + 1 LI AS
2
VDS
BVDSS
ID
IAS
RG
VDD
DUT
VGS
2
ID(t)
VDD
VDS(t)
tp
tp
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
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6
Time
FCH22N60N
+
DUT
VDS
−
ISD
L
Driver
RG
Same Type
as DUT
VGS
− dv/dt controlled by RG
− ISD controlled by pulse period
D+
VGS
(Driver)
VDD
Gate Pulse Width
Gate Pulse Period
10 V
IFM, Body Diode Forward Current
ISD
(DUT)
di/dt
IRM
Body Diode Reverse Current
Body Diode Recovery dv/dt
VDS
(DUT)
VDD
VSD
Body Diode
Forward Voltage Drop
Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
SUPREMOS is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or
other countries.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−247−3LD SHORT LEAD
CASE 340CK
ISSUE A
A
DATE 31 JAN 2019
A
E
P1
P
A2
D2
Q
E2
S
B
D
1
2
D1
E1
2
3
L1
A1
L
b4
c
(3X) b
0.25 M
(2X) b2
B A M
DIM
(2X) e
GENERIC
MARKING DIAGRAM*
AYWWZZ
XXXXXXX
XXXXXXX
XXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW = Work Week
ZZ
= Assembly Lot Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13851G
TO−247−3LD SHORT LEAD
A
A1
A2
b
b2
b4
c
D
D1
D2
E
E1
E2
e
L
L1
P
P1
Q
S
MILLIMETERS
MIN NOM MAX
4.58 4.70 4.82
2.20 2.40 2.60
1.40 1.50 1.60
1.17 1.26 1.35
1.53 1.65 1.77
2.42 2.54 2.66
0.51 0.61 0.71
20.32 20.57 20.82
13.08
~
~
0.51 0.93 1.35
15.37 15.62 15.87
12.81
~
~
4.96 5.08 5.20
~
5.56
~
15.75 16.00 16.25
3.69 3.81 3.93
3.51 3.58 3.65
6.60 6.80 7.00
5.34 5.46 5.58
5.34 5.46 5.58
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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