MOSFET – N-Channel,
SUPERFET)
600 V, 35 A, 98 mW
FCH35N60
Description
SUPERFET MOSFET is ON Semiconductor’s first generation
of high voltage super−junction (SJ) MOSFET family that is utilizing
charge balance technology for outstanding low on−resistance
and lower gate charge performance. This technology is tailored
to minimize conduction loss, provide superior switching performance,
dv/dt rate and higher avalanche energy. Consequently, SUPERFET
MOSFET is very suitable for the switching power applications
such as PFC, server/telecom power, FPD TV power, ATX power
and industrial power applications.
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VDS
RDS(ON) MAX
ID MAX
600 V
98 m @ 10 V
35 A
D
Features
•
•
•
•
•
•
650 V @ TJ = 150°C
Typ. RDS(on) = 79 m
Ultra Low Gate Charge (Typ. Qg = 139 nC)
Low Effective Output Capacitance (Typ. Coss(eff.) = 340 pF)
100% Avalanche Tested
This is a Pb−Free Device
G
S
N-CHANNEL MOSFET
Applications
• Solar Inverter
• AC−DC Power Supply
G
D
S
TO−247−3LD
CASE 340CK
MARKING DIAGRAM
$Y&Z&3&K
FCH
35N60
$Y
&Z
&3
&K
FCH35N60
= ON Semiconductor Logo
= Assembly Plant Code
= Numeric Date Code
= Lot Code
= Specific Device Code
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
© Semiconductor Components Industries, LLC, 2009
April, 2021 − Rev. 3
1
Publication Order Number:
FCH35N60/D
FCH35N60
ABSOLUTE MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Symbol
Value
Unit
VDSS
Drain to Source Voltage
600
V
VGSS
Gate to Source Voltage
±30
V
− Continuous (TC = 25°C)
35
A
− Continuous (TC = 100°C)
22.2
− Pulsed (Note 1)
105
A
1455
mJ
35
A
31.25
mJ
20
V/ns
312.5
W
2.5
W/°C
−55 to + 150
°C
300
°C
ID
Parameter
Drain Current
IDM
Drain Current
EAS
Single Pulsed Avalanche Energy (Note 2)
IAR
Avalanche Current (Note 1)
EAR
Repetitive Avalanche Energy (Note 1)
dv/dt
Peak Diode Recovery dv/dt (Note 3)
PD
Power Dissipation
(TC = 25°C)
− Derate above 25°C
TJ, TSTG
TL
Operating and Storage Temperature Range
Maximum Lead Temperature for Soldering, 1/8″ from Case for 5 Second
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Repetitive Rating: Pulse width limited by maximum junction temperature.
2. IAS = 17.5 A, VDD = 50 V, RG = 25 , starting TJ = 25°C
3. ISD ≤ 35 A, di/dt ≤ 200 A/s, VDD ≤ BVDSS, starting TJ = 25°C
PACKAGE MARKING AND ORDERING INFORMATION
Part Number
Top Mark
Package
Package Method
Reel Size
Tape Width
Quantity
FCH35N60
FCH35N60
TO−247−3LD
Tube
−
−
30 Units
THERMAL CHARACTERISTICS
Symbol
Parameter
Value
Unit
°C/W
RJC
Thermal Resistance, Junction to Case, Max.
0.4
RJA
Thermal Resistance, Junction to Ambient, Max.
42
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2
FCH35N60
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
ID = 250 A, VGS = 0 V, TJ = 25°C
600
−
−
V
ID = 250 A, VGS = 0 V, TJ = 150°C
−
650
−
Breakdown Voltage Temperature
Coefficient
ID = 250 A, Referenced to 25°C
−
0.6
−
V/°C
BVDS
Drain−Source Avalanche Breakdown
Voltage
VGS = 0 V, ID = 16 A
−
700
−
V
IDSS
Zero Gate Voltage Drain Current
VDS = 600 V, VGS = 0 V
−
−
1
A
VDS = 480 V, TC = 125°C
−
−
10
VGS = ±30 V, VDS = 0 V
−
−
±100
nA
OFF CHARACTERISTICS
BVDSS
BVDSS
/ TJ
IGSS
Drain to Source Breakdown Voltage
Gate to Body Leakage Current
ON CHARACTERISTICS
VGS(th)
Gate Threshold Voltage
VGS = VDS, ID = 250 A
3.0
−
5.0
V
RDS(on)
Static Drain to Source On Resistance
VGS = 10 V, ID = 17.5 A
−
0.079
0.098
Forward Transconductance
VDS = 40 V, ID = 17.5 A
−
28.8
−
S
VDS = 25 V, VGS = 0 V,
f = 1 MHz
−
4990
6640
pF
−
2380
3170
pF
−
140
−
pF
gFS
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Coss
Output Capacitance
VDS = 480 V, VGS = 0 V, f = 1 MHz
−
113
−
pF
Effective Output Capacitance
VDS = 0 V to 480 V, VGS = 0 V
−
340
−
pF
Qg
Total Gate Charge at 10 V
−
139
181
nC
Qgs
Gate to Source Gate Charge
VDS = 480 V, ID = 35 A,
VGS = 10 V
(Note 4)
−
31
−
nC
Qgd
Gate to Drain “Miller” Charge
−
69
−
nC
ESR
Equivalent Series Resistance (G−S)
Drain Open, f = 1 MHz
−
1.4
−
VDD = 300 V, ID = 35 A,
RG = 4.7
(Note 4)
−
34
78
ns
−
120
250
ns
Cosseff.
SWITCHING CHARACTERISTICS
td(on)
Turn-On Delay Time
tr
Turn−On Rise Time
td(off)
Turn-Off Delay Time
−
105
220
ns
Turn−Off Fall Time
−
73
155
ns
tf
DRAIN-SOURCE DIODE CHARACTERISTICS
Maximum Continuous Drain to Source Diode Forward Current
−
−
35
A
ISM
Maximum Pulsed Drain to Source Diode Forward Current
−
−
105
A
VSD
Drain to Source Diode Forward Voltage
VGS = 0 V, ISD = 35 A
−
−
1.4
V
trr
Reverse Recovery Time
−
614
−
ns
Qrr
Reverse Recovery Charge
VGS = 0 V, ISD = 35 A,
dIF/dt = 100 A/s
−
16.3
−
C
IS
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Essentially independent of operating temperature.
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3
FCH35N60
TYPICAL CHARACTERISTICS
200
VGS = 15.0 V
100
10.0 V
8.0 V
7.0 V
6.5 V
6.0 V
5.5 V
10
100
ID, Drain Current [A]
ID, Drain Current [A]
200
1
0.3
150°C
25°C
*Notes:
1. 250 s Pulse Test
2. TC = 25°C
1
0.1
10
*Notes:
1. VDS = 20 V
2. 250 s Pulse Test
1
20
4
5
8
9
500
IS, Reverse Drain Current [A]
0.24
RDS(ON) [],
Drain−Source On−Resistance
7
Figure 2. Transfer Characteristics
Figure 1. On−Region Characteristics
0.20
0.16
0.12
VGS = 10 V
VGS = 20 V
0.08
100
*Note: TC = 25°C
0
25
50
75
100
1
125
150°C
10
0.2
10000
VGS, Gate−Source Voltage [V]
10
Ciss
1000
Coss
Ciss = Cgs + Cgd (Cds = shorted)
Coss = Cds + Cgd
Crss = Cgd
1
10
0.8
1.2
1.6
Figure 4. Body Diode Forward Voltage Variation
vs. Source Current and Temperature
50000
10
0.1
0.4
VSD, Body Diode Forward Voltage [V]
Figure 3. On−Resistance Variation vs. Drain Current
and Gate Voltage
*Notes:
100 1. VGS = 0 V
2. f = 1 MHz
25°C
*Notes:
1. VGS = 0 V
2. 250 s Pulse Test
ID, Drain Current [A]
Capacitances [pF]
6
VGS, Gate−Source Voltage [V]
VDS, Drain−Source Voltage [V]
0.04
−55°C
10
Crss
100
8
6
4
2
0
600
VDS, Drain−Source Voltage [V]
VDS = 100 V
VDS = 250 V
VDS = 400 V
*Note: ID = 35 A
0
40
80
120
160
QG, Total Gate Charge [nC]
Figure 5. Capacitance Characteristics
Figure 6. Gate Charge Characteristics
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4
FCH35N60
TYPICAL CHARACTERISTICS
3.0
RDS(ON), (Normalized)
Drain−Source On−Resistance
BVDSS, (Normalized)
Drain−Source Breakdown Voltage
1.15
1.10
1.05
1.00
0.95
*Notes:
1. VGS = 0 V
2. ID = 250 A
0.90
0.85
−100
−50
0
50
100
150
2.5
2.0
1.5
1.0
0.0
−100
200
*Notes:
1. VGS = 10 V
2. ID = 17.5 A
0.5
−50
TJ, Junction Temperature [°C]
200
40
ID, Drain Current [A]
1 ms
Operation in This Area
is Limited by RDS(on)
1
10 ms
DC
1
10
100
30
20
10
*Notes:
1. TC = 25°C
2. TJ = 150°C
3. Single Pulse
0.1
0
1000
50
25
75
100
Figure 10. Maximum Drain Current
vs. Case Temperature
Figure 9. Maximum Safe Operating Area
0.6
0.5
0.1
0.2
0.1
0.05
0.02
0.01 0.01
Single Pulse
0.001
10−5
10−4
125
TC, Case Temperature [°C]
VDS, Drain−Source Voltage [V]
ZJC(t), Thermal Response [°C/W]
ID, Drain Current [A]
150
100 s
10
0.01
100
Figure 8. On−Resistance Variation
vs. Temperature
10 s
100
50
TJ, Junction Temperature [°C]
Figure 7. Breakdown Voltage Variation
vs. Temperature
300
0
PDM
t1
t2
*Notes:
1. ZJC(t) = 0.4°C/W Max.
2. Duty Factor, D = t1/t2
3. TJM − TC = PDM * ZJC(t)
10−3
10−2
10−1
1
t1, Rectangular Pulse Duration [sec]
Figure 11. Transient Thermal Response Curve
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5
10
150
FCH35N60
VGS
RL
Qg
VDS
VGS
Qgs
Qgd
DUT
1 mA
Charge
Figure 12. Gate Charge Test Circuit & Waveform
RL
VDS
VDS
90%
VDD
VGS
RG
VGS
DUT
VGS
10%
td(on)
td(off) t
f
tr
ton
toff
Figure 13. Resistive Switching Test Circuit & Waveforms
L
E AS + 1 LI AS
2
VDS
BVDSS
ID
IAS
RG
VDD
DUT
VGS
2
ID(t)
VDD
VDS(t)
tp
tp
Figure 14. Unclamped Inductive Switching Test Circuit & Waveforms
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6
Time
FCH35N60
+
DUT
VDS
−
ISD
L
Driver
RG
Same Type
as DUT
VGS
− dv/dt controlled by RG
− ISD controlled by pulse period
D+
VGS
(Driver)
VDD
Gate Pulse Width
Gate Pulse Period
10 V
IFM, Body Diode Forward Current
ISD
(DUT)
di/dt
IRM
Body Diode Reverse Current
Body Diode Recovery dv/dt
VDS
(DUT)
VDD
VSD
Body Diode
Forward Voltage Drop
Figure 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
SUPERFET is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or
other countries.
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7
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
TO−247−3LD SHORT LEAD
CASE 340CK
ISSUE A
A
DATE 31 JAN 2019
A
E
P1
P
A2
D2
Q
E2
S
B
D
1
2
D1
E1
2
3
L1
A1
L
b4
c
(3X) b
0.25 M
(2X) b2
B A M
DIM
(2X) e
GENERIC
MARKING DIAGRAM*
AYWWZZ
XXXXXXX
XXXXXXX
XXXX = Specific Device Code
A
= Assembly Location
Y
= Year
WW = Work Week
ZZ
= Assembly Lot Code
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “G”, may
or may not be present. Some products may
not follow the Generic Marking.
DOCUMENT NUMBER:
DESCRIPTION:
98AON13851G
TO−247−3LD SHORT LEAD
A
A1
A2
b
b2
b4
c
D
D1
D2
E
E1
E2
e
L
L1
P
P1
Q
S
MILLIMETERS
MIN NOM MAX
4.58 4.70 4.82
2.20 2.40 2.60
1.40 1.50 1.60
1.17 1.26 1.35
1.53 1.65 1.77
2.42 2.54 2.66
0.51 0.61 0.71
20.32 20.57 20.82
13.08
~
~
0.51 0.93 1.35
15.37 15.62 15.87
12.81
~
~
4.96 5.08 5.20
~
5.56
~
15.75 16.00 16.25
3.69 3.81 3.93
3.51 3.58 3.65
6.60 6.80 7.00
5.34 5.46 5.58
5.34 5.46 5.58
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
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