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liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws,
regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and hold onsemi and its officers, employees,
subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative
Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
Features
Applications
r DS(ON) = 6.1mΩ (Typ.), V GS = 10V, ID = 80A
Qg(tot) = 51nC (Typ.), V GS = 10V
Low Miller Charge
Low QRR Body Diode
UIS Capability (Single Pulse and Repetitive
Pulse)
Qualified to AEC Q101
RoHS Compliant
Motor / Body Load Control
ABS Systems
Pow ertrain Management
Injection Systems
DC-DC converters and Off -line UPS
Distributed Pow er Architectures and VRMs
Primary Sw itch for 12V and 24V systems
Formerly developmental type 82567
Ordering Information
Device
Output Voltage
Marking
Package
Shipping
FDB070AN06A0-F085
TBD
FDB070AN06A0
TO-263AB
Tape and Reel
© 2017 Semiconductor Components Industries, LLC
August-2017, Rev. 2
Publication Order Number:
FDB070AN06A0-F085/D
FDB070AN06A0-F085 — N-Channel PowerTrench® MOSFET
FDB070AN06A0-F085
N-Channel PowerTrench® MOSFET
60V, 80A, 7mΩ
TC = 25℃ unless otherwise noted
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Ratings
Unit
V DSS
Drain to Source Voltage
60
V
V GS
Gate to Source Voltage
±20
V
Continuous (T C < 97℃, V GS = 10V)
80
A
Continuous (T A = 25℃, V GS = 10V, RJA = 43℃/W)
15
A
Drain Current
ID
Pulsed
E AS
Figure 4
A
Single Pulse Avalanche Energy (1)
190
mJ
Power dissipation
175
W
Derate above 25℃
1.17
W/℃
-55 to 175
℃
0.86
℃/W
62
℃/W
43
℃/W
PD
T J, T STG
Operating and Storage Temperature
Thermal Characteristics
RJC
Thermal Resistance Junction to Case TO-220,TO-263
(2)
RJA
Thermal Resistance Junction to Ambient TO-220,TO-263
RJA
Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area
Notes:
1.
Starting TJ = 25 ℃, L = 93 H, IAS = 64A.
2.
Pulse width = 100s.
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry .
All ON Semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems
certification.
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2
FDB070AN06A0-F085 — N-Channel PowerTrench® MOSFET
PD
Absolute Maximum Ratings
Symbol
TC = 25℃ unless otherw ise noted
Parameter
Test Conditions
Min.
Typ.
Max.
Units
Off Characteristics
B VDSS
Drain to Source Breakdown Voltage ID = 250 A, V GS = 0 V
60
V
1
IDSS
Zero Gate Voltage Drain Current
V DS = 50 V
V GS = 0 V
IGSS
Gate to Source Leakage Current
V GS = ±20 V
Gate to Source Threshold Voltage
V GS = V DS, ID = 250A
T C = 150 ℃
250
A
±100
nA
4
V
On Characteristics
V GS(TH)
ID = 80A, V GS = 10V
rDS(ON)
Drain to Source On Resistance
2
0.0061
0.007
0.0127
0.015
ID = 80A, V GS = 10V,
T J = 175℃
Ω
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
CRSS
Reverse Transfer Capacitance
V DS = 25V, V GS = 0 V,
F = 1 MHz
Total Gate Charge at 10V
V GS = 0V to 10V
Qg(TH)
Threshold Gate Charge
V GS = 0V to 2V
Gate to Source Gate Charge
Qgs2
Gate Charge Threshold to Plateau
Qgd
Gate to Drain “Miller” Charge
pF
510
pF
230
Qg(TOT)
Qgs
3000
V DD = 30 V
ID = 80 A
Ig = 1.0 mA
pF
51
66
nC
5.4
7
nC
17
nC
11.6
nC
16
nC
Sw itching Characteristics (V GS = 10 V)
tON
T d(ON)
tr
T d(OFF)
tf
tOFF
Turn-On Time
256
Turn-On Delay Time
ns
12
ns
Rise Time
V DD = 30 V, I D = 80 A
159
ns
Turn-Off Delay Time
V GS = 10 V, RGS = 5.6 Ω
27
ns
35
ns
Fall Time
Turn-Off Time
93
ns
ISD = 80 A
1.25
V
ISD = 40 A
1.0
V
Reverse Recovery Time
ISD = 75 A, dI SD/dt = 100 A/s
67
ns
Reverse Recovered Charge
ISD = 75 A, dI SD/dt = 100 A/s
80
nC
Drain-Source Diode Characteristics
V SD
trr
QRR
Source to Drain Diode Voltage
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3
FDB070AN06A0-F085 — N-Channel PowerTrench® MOSFET
PD
Electrical Characteristics
Figure 1.
TC = 25℃ unless otherw ise noted
Norm alized Pow er Dissipation vs
Am bient Tem perature
Figure 3.
Figure 2.
Maxim um Continuous Drain Current vs
Case Tem perature
Norm alized Maxim um Transient Therm al Im pedance
Figure 4.
Peak Current Capability
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4
FDB070AN06A0-F085 — N-Channel PowerTrench® MOSFET
PD
Typical Characteristics
Figure 5.
TC = 25℃ unless otherw ise noted
Forw ard Bias Safe Operating Area
NOTE: Refer to ON Semiconductor Application Notes AN7514 and
AN7515
Figure 6.
Figure 7.
Figure 9.
Transfer Characteristics
Figure 8.
Drain to Source On Resistance vs Drain
Current
Unclam ped Inductive Sw itching
Capability
Saturation Characteristics
Figure 10. Norm alized Drain to Source On
Resistance vs Junction Tem perature
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5
FDB070AN06A0-F085 — N-Channel PowerTrench® MOSFET
PD
Typical Characteristics
TC = 25℃ unless otherw ise noted
Figure 11.
Norm alized Gate Threshold Voltage vs
Junction Tem perature
Figure 12. Norm alized Drain to Source Breakdow n
Voltage vs Junction Tem perature
Figure 13.
Capacitance vs Drain to Source Voltage
Figure 14.
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6
Gate Charge Waveform s for Constant
Gate Current
FDB070AN06A0-F085 — N-Channel PowerTrench® MOSFET
PD
Typical Characteristics
Figure 15.
Unclam ped Energy Test Circuit
Figure 17.
Figure 19.
Gate Charge Test Circuit
Sw itching Tim e Test Circuit
Figure 16.
Unclam ped Energy Waveform s
Figure 18.
Figure 20.
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7
Gate Charge Waveform s
Sw itching Tim e Waveform s
FDB070AN06A0-F085 — N-Channel PowerTrench® MOSFET
PD
Test Circuits and Waveforms
The maximum rated junction temperature, TJM , and
the ther mal resistance of the heat dissipating path
deter mines the maximum allow able device pow er
dissipation, PDM , in an application. Therefore the
application’s
ambient
temperature,
TA( ℃ ), and
ther mal resistance RθJA( ℃/W) must be review ed to
ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship
and serves as the basis for establishing the rating of
the part.
In us ing surface mount devices such as the TO-263
package, the environment in w hich it is applied w ill
have a significant influence on the part’s current and
maximum pow er dissipation ratings.
Precise
deter mination of PDM is complex and influenced by
many factors:
1.
2.
3.
4.
5.
6.
Figure 21.
Mounting pad area onto w hich the device is
attached and w hether there is copper on one
side or both sides of the board.
The number of copper layers and the thickness
of the board.
The use of external heat sinks.
The use of thermal vias.
Air flow and board orientation.
For non steady state applications, the pulse
w idth, the duty cycle and the transient ther mal
response of the part, the board and the
environment they are in.
ON Semiconductor prov ides ther mal infor mation to
assist the designer’s
preliminary
application
evaluation. Figure 21 defines the RJA for the device
as a function of the top copper (component side)
area. This is for a horizontally positioned FR-4 board
w ith 1oz copper after 1000 seconds of steady state
pow er with no air flow . This graph provides the
necessary information for calculation of the steady
state junction temperature or pow er dissipation. Pulse
applications can be evaluated using the ON
Semiconductor device Spice ther mal model or
manually utilizing the nor malized maximum transient
thermal impedance curve.
Ther mal res istances corresponding to other copper
areas can be obtained from Figure 21 or by
calculation us ing Equation 2 or 3. Equation 2 is used
for copper area defined in inches square and equation
3 is for area in centimeters square. The area, in
square inches or square centimeters is the top copper
area including the gate and source pads.
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8
Therm al Resistance vs Mounting Pad
Area
FDB070AN06A0-F085 — N-Channel PowerTrench® MOSFET
PD
Thermal Resistance vs. Mounting Pad Area
FDB070AN06A0-F085 — N-Channel PowerTrench® MOSFET
PD
PSPICE Electrical Model
.SUBCKT FDB070AN06A0 2 1 3 ; rev March 2003
Ca 12 8 1.5e-9
Cb 15 14 1.5e-9
Cin 6 8 2.9e-9
Dbody 7 5 Dbody MOD
Dbreak 5 11 DbreakMOD
Dplcap 10 5 DplcapMOD
Ebreak 11 7 17 18 62
Eds 14 8 5 8 1
Egs 13 8 6 8 1
Esg 6 10 6 8 1
Ev thres 6 21 19 8 1
Ev temp 20 6 18 22 1
It 8 17 1
Lgate 1 9 4.8e-9
Ldrain 2 5 1.0e-9
Lsource 3 7 3e-9
RLgate 1 9 48
RLdrain 2 5 10
RLsource 3 7 3
Mmed 16 6 8 8 MmedMOD
Mstro 16 6 8 8 MstroMOD
Mweak 16 21 8 8 MweakMOD
Rbreak 17 18 RbreakMOD 1
Rdrain 50 16 RdrainMOD 1.3e-3
Rgate 9 20 2.7
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 3.1e-3
Rv thres 22 8 Rv thresMOD 1
Rv temp 18 19 Rv tempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD
Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),10) )}
.MODEL Dbody MOD D (IS=7.6E-12 N=1.04 RS=2.2e-3 TRS1=2.7e-3 TRS2=2e-7
+ CJO=1.6e-9 M=0.55 TT=5e-12 XTI=3.9)
.MODEL DbreakMOD D (RS=8e-1 TRS1=5e-4 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=1.05e-9 IS=1e-30 N=10 M=0.45)
.MODEL MmedMOD NMOS (VTO=3.7 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.7)
.MODEL MstroMOD NMOS (VTO=4.7 KP=100 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL MweakMOD NMOS (VTO=3.01 KP=0.03 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=27 RS=0.1)
.MODEL
.MODEL
.MODEL
.MODEL
.MODEL
.MODEL
RbreakMOD RES (TC1=7.1e-4 TC2=-5.5e-7)
RdrainMOD RES (TC1=1.7e-2 TC2=4e-5)
RSLCMOD RES (TC1=3e-3 TC2=1e-5)
RsourceMOD RES (TC1=1e-3 TC2=1e-6)
Rv thresMOD RES (TC1=-5.2e-3 TC2=-1.5e-5)
Rv tempMOD RES (TC1=-3e-3 TC2=1.3e-6)
.MODEL
.MODEL
.MODEL
.MODEL
.ENDS
S1AMOD
S1BMOD
S2AMOD
S2BMOD
VSWITCH
VSWITCH
VSWITCH
VSWITCH
(RON=1e-5
(RON=1e-5
(RON=1e-5
(RON=1e-5
ROFF=0.1
ROFF=0.1
ROFF=0.1
ROFF=0.1
VON=-4 VOFF=-2)
VON=-2 VOFF=-4)
VON=-1.5 VOFF=0.5)
VON=0.5 VOFF=-1.5)
Note: For f urther discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conf erence Records, 1991, written by William J. Hepp and C. Frank
Wheatley .
www.onsemi.com
9
rev March 2003
template FDB070AN06A0 n2,n1,n3
electrical n2,n1,n3
{
v ar i iscl
dp..model dbody mod = (isl=7.6e-12,nl=1.04,rs=2.2e-3,trs1=2.7e-3,trs2=2e-7,cjo=1.6e-9,m=0.55,tt=5e-12,xti=3.9)
dp..model dbreakmod = (rs=8e-1,trs1=5e-4,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=1.05e-9,isl=10e-30,nl=10,m=0.45)
m..model mmedmod = (ty pe=_n,v to=3.7,kp=10,is=1e-30, tox=1)
m..model mstrongmod = (ty pe=_n,v to=4.7,kp=100,is=1e-30, tox=1)
m..model mweakmod = (ty pe=_n,v to=3.01,kp=0.03,is=1e-30, tox=1,rs=0.1)
sw_v csp..model s1amod = (ron=1e-5,rof f =0.1,v on=-4,v off=-2)
sw_v csp..model s1bmod = (ron=1e-5,rof f =0.1,v on=-2,v off=-4)
sw_v csp..model s2amod = (ron=1e-5,rof f =0.1,v on=-1.5,v off=0.5)
sw_v csp..model s2bmod = (ron=1e-5,rof f =0.1,v on=0.5,v off=-1.5)
c.ca n12 n8 = 1.5e-9
c.cb n15 n14 = 1.5e-9
c.cin n6 n8 = 2.9e-9
dp.dbody n7 n5 = model=dbody mod
dp.dbreak n5 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
spe.ebreak n11 n7 n17 n18 = 62
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.ev thres n6 n21 n19 n8 = 1
spe.ev temp n20 n6 n18 n22 = 1
i.it n8 n17 = 1
l.lgate n1 n9 = 4.8e-9
l.ldrain n2 n5 = 1.0e-9
l.lsource n3 n7 = 3e-9
res.rlgate n1 n9 = 48
res.rldrain n2 n5 = 10
res.rlsource n3 n7 = 3
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u,
w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod,
l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
res.rbreak n17 n18 = 1, tc1=7.1e-4,tc2=-5.5e-7
res.rdrain n50 n16 = 1.3e-3, tc1=1.7e-2,tc2=4e-5
res.rgate n9 n20 = 2.7
res.rslc1 n5 n51 = 1e-6, tc1=3e-3,tc2=1e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.1e-3, tc1=1e-3,tc2=1e-6
res.rv thres n22 n8 = 1, tc1=-5.2e-3,tc2=-1.5e-5
res.rv temp n18 n19 = 1, tc1=-3e-3,tc2=1.3e-6
sw_v csp.s1a n6 n12 n13 n8 = model=s1amod
sw_v csp.s1b n13 n12 n13 n8 = model=s1bmod
sw_v csp.s2a n6 n15 n14 n13 = model=s2amod
sw_v csp.s2b n13 n15 n14 n13 = model=s2bmod
v .v bat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v (n51,n50) = ((v (n5,n51)/(1e-9+abs(v (n5,n51))))*((abs(v (n5,n51)*1e6/250))** 10))
}
}
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10
FDB070AN06A0-F085 — N-Channel PowerTrench® MOSFET
PD
SABER Electrical Model
FDB070AN06A0-F085 — N-Channel PowerTrench® MOSFET
PD
PSPICE Thermal Model
REV 23 March 2003
FDB070AN06A0T
CTHERM1
CTHERM2
CTHERM3
CTHERM4
CTHERM5
CTHERM6
TH 6 3.5e-3
6 5 1.7e-2
5 4 1.8e-2
4 3 1.9e-2
3 2 4.7e-2
2 TL 7e-2
RTHERM1
RTHERM2
RTHERM3
RTHERM4
RTHERM5
RTHERM6
TH 6 2e-2
6 5 7e-2
5 4 1e-1
4 3 1.5e-1
3 2 1.6e-1
2 TL 1.85e-1
SABER Thermal Model
SABER thermal model FDB070AN06A0T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 =3.5e-3
ctherm.ctherm2 6 5 =1.7e-2
ctherm.ctherm3 5 4 =1.8e-2
ctherm.ctherm4 4 3 =1.9e-2
ctherm.ctherm5 3 2 =4.7e-2
ctherm.ctherm6 2 tl =7e-2
rtherm.rtherm1
rtherm.rtherm2
rtherm.rtherm3
rtherm.rtherm4
rtherm.rtherm5
rtherm.rtherm6
}
th 6 =2e-2
6 5 =7e-2
5 4 =1e-1
4 3 =1.5e-1
3 2 =1.6e-1
2 tl =1.85e-1
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11
FDB070AN06A0-F085 — N-Channel PowerTrench® MOSFET
PD
Physical Dimensions
Figure 22.
TO-263 2L (D2PAK), 4.445 x 10.16 x 15.24m m , TAPE REEL
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12
FDB070AN06A0-F085 — N-Channel PowerTrench® MOSFET
PD
ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the
United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A
listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make
changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any
particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor
products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by
ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and
actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.
ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for
use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or simi lar classification in a foreign jurisdiction or
any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs,
damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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