FDB2532_F085

MOSFET – N-Channel, POWERTRENCH) 150 V, 79 A, 16 mW FDB2532-F085 Features • • • • • • • www.onsemi.com RDS(ON) = 14 mW (Typ.), VGS = 10 V, ID = 33 A Qg (tot) = 82 nC (Typ.), VGS = 10 V Low Miller Charge Low QRR Body Diode UIS Capability (Single Pulse and Repetitive Pulse) AEC−Q101 Qualified and PPAP Capable These Devices are Pb−Free and are RoHS Compliant D G S Applications • • • • • • • • DC/DC converters and Off−Line UPS Distributed Power Architectures and VRMs Primary Switch for 24 V and 48 V Systems High Voltage Synchronous Rectifier Direct Injection / Diesel Injection Systems 42 V Automotive Load Control Electronic Valve Train Systems Synchronous Rectification D2PAK−3 CASE 418AJ DRAIN (FLANGE) GATE SOURCE MARKING DIAGRAM $Y&Z&3&K FDB2532 $Y &Z &3 &K FDB2532 = ON Semiconductor Logo = Assembly Plant Code = Data Code (Year & Week) = Lot = Specific Device Code ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2010 May, 2020 − Rev. 2 1 Publication Order Number: FDB2532−F085/D FDB2532−F085 MOSFET MAXIMUM RATINGS (TC = 25°C, Unless otherwise noted) Symbol Value Unit VDSS Drain to Source Voltage 150 V VGS Gate to Source Voltage ±20 V − Continuous (TC = 25°C, VGS = 10 V) 79 A − Continuous (TC = 100°C, VGS = 10 V) 56 − Continuous (Tamb = 25°C, VGS = 10 V, RqJA = 43°C/W) 8 A Figure 4 A 400 mJ ID ID Parameter Drain Current Drain Current − Pulsed EAS Single Pulse Avalanche Energy (Note 1) PD Power Dissipation TJ, TSTG (TC = 25°C) 310 W − Derate Above 25°C 2.07 W/°C −55 to +175 °C Operating and Storage Temperature Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Starting TJ = 25°C, L = 0.5 mH, IAS = 40 A THERMAL CHARACTERISTICS Symbol Parameter RqJC Thermal Resistance Junction to Case RqJA Thermal Resistance Junction to Ambient, 1in2 Copper Pad Area Value Unit 0.48 _C/W 43 _C/W PACKAGE MARKING AND ORDERING INFORMATION Device Marking FDB2532 Device FDB2532−F085 Package TO−263 (D2−PAK−3) Reel Size Tape Width Quantity 330 mm 24 mm 800 Units www.onsemi.com 2 FDB2532−F085 ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted) Parameter Symbol Test Conditions Min. Typ. Max. Unit OFF CHARACTERISTICS Drain to Source Breakdown Voltage ID = 250 mA, VGS = 0 V IDSS Zero Gate Voltage Drain Current VDS = 120 V, VGS = 0 V IGSS Gate to Source Leakage Current BVDSS 150 V 1 mA VDS = 120 V, VGS = 0 V, TC = 150_C 250 VGS = ±20 V ±100 nA 4.0 V W ON CHARACTERISTICS VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250 mA 2.0 RDS(ON) Drain to Source On Resistance ID = 33 A, VGS = 10 V 0.014 0.016 ID = 16 A, VGS = 6 V 0.016 0.024 ID = 33 A, VGS = 10 V, TC = 175 °C 0.040 0.048 VDS = 25 V, VGS = 0 V, f = 1 MHz 5870 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance 615 pF Crss Reverse Transfer Capacitance 135 pF Qg(tot) Total Gate Charge at 10 V VGS = 0 V to 10 V, VDD = 75 V, ID = 33 A, Ig = 1.0 mA 82 107 nC Qg(th) Threshold Gate Charge VGS = 0 V to 2 V, VDD = 75 V, ID = 33 A, Ig = 1.0 mA 11 14 nC Qgs Gate to Source Gate Charge VDD = 75 V, ID = 33 A, Ig = 1.0 mA 23 nC Qgs2 Gate Charge Threshold to Plateau 13 nC Qgd Gate to Drain “Miller” Charge 19 nC RESISTIVE SWITCHING CHARACTERISTICS (VGS = 10 V) tON td(ON) tr td(OFF) tf tOFF Turn-On Time Turn-On Delay Time VDD = 75 V, ID = 33 A, VGS = 10 V, RGS = 3.6 W 69 ns 16 ns Rise Time 30 ns Turn-Off Delay Time 39 ns Fall Time 17 ns Turn-Off Time 84 ns ISD = 33 A 1.25 V ISD = 16 A 1 V DRAIN−SOURCE DIODE CHARACTERISTICS VSD trr QRR Source to Drain Diode Voltage Reverse Recovery Time ISD = 33 A, dlSD/dt = 100 A/ms 105 ns Reverse Recovery Charge ISD = 33 A, dlSD/dt = 100 A/ms 327 nC Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 1. Pulse Width = 100 s www.onsemi.com 3 FDB2532−F085 TYPICAL CHARACTERISTICS TC = 25°C unless otherwise noted 125 VGS = 10V 1.0 ID, DRAIN CURRENT (A) 100 0.8 0.6 0.4 75 50 25 0.2 0 0 25 50 75 100 125 150 0 175 25 50 TC , CASE TEMPERATURE (oC) ZQJC, NORMALIZED THERMAL IMPEDANCE 75 100 125 150 TC, CASE TEMPERATURE (oC) Figure 1. Normalized Power Dissipation vs. Ambient Temperature Figure 2. Maximum Continuous Drain Current vs Case Temperature 2.0 DUTY CYCLE − DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 1.0 PDM 0.1 t1 t2 NOTES: DUTY FACTOR : D = t1/t2 PEAK TJ = PDM x ZQJC x RQJC + TC SINGLE PULSE 0.01 10−5 10−4 10−3 10−2 100 10−1 101 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 2000 IDM, PEAK CURRENT (A) POWER DISSIPATION MULTIPLIER 1.2 TC = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 1000 I = I25 175 − TC 150 VGS = 10V 100 50 10−5 10−4 10−3 10−2 t, PULSE WIDTH (s) Figure 4. Peak Current Capability www.onsemi.com 4 10−1 100 101 175 FDB2532−F085 TYPICAL CHARACTERISTICS (Continued) TC = 25°C unless otherwise noted NOTE: 1000 Refer to ON Semiconductor Application Notes AN−7515 and AN−7517 200 10 ms STARTING TJ = 25oC IAS, AVALANCHE CURRENT (A) ID, DRAIN CURRENT (A) 100 100 ms 100 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 10 1ms 10ms DC 1 SINGLE PULSE TJ = MAX RATED TC = 25oC 0.1 1 10 100 STARTING TJ = 150oC 10 If R = 0 tAV = (L)(IAS)/(1.3*RATED BV DSS − VDD) If R p  tAV = (L/R)ln[(I AS*R)/(1.3*RATED BVDSS − VDD) +1] 1 300 0.001 0.01 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 5. Forward Bias Safe Operating Area Figure 6. Unclamped Inductive Switching Capability 180 120 TJ = 175oC 90 60 TJ = 25oC TJ = −55 oC VGS = 6V 120 30 90 TC = 25oC 60 VGS = 5V 30 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 0 0 0.0 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.0 2.0 3.0 4.0 5.0 6.0 6.5 VDS, DRAIN TO SOURCE VOLTAGE (V) VGS , GATE TO SOURCE VOLTAGE (V) Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics 18 3.0 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX NORMALIZED DRAIN TO SOURCE ON RESISTANCE DRAIN TO SOURCE ON RESISTANCE (m W) VGS = 7V VGS = 10V 150 ID, DRAIN CURRENT (A) ID , DRAIN CURRENT (A) 180 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX VDD = 15V 150 1 0.1 tAV, TIME IN AVALANCHE (ms) 17 VGS = 6V 16 15 VGS = 10V 14 13 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 2.5 2.0 1.5 1.0 VGS = 10V, ID =33A 0.5 0 20 40 60 ID, DRAIN CURRENT (A) −80 80 −40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (oC) Figure 9. Drain to Source On Resistance vs Drain Current Figure 10. Normalized Drain to Source On Resistance vs Junction Temperature www.onsemi.com 5 FDB2532−F085 TYPICAL CHARACTERISTICS (Continued) TC = 25°C unless otherwise noted 1.2 1.4 ID = 250 mA NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE VGS = VDS, ID = 250 mA NORMALIZED GATE THRESHOLD VOLTAGE 1.2 1.0 0.8 0.6 1.1 1.0 0.9 0.4 −80 −40 0 40 80 120 160 200 −80 T J, JUNCTION TEMPERATURE (oC) Figure 11. Normalized Gate Threshold Voltage vs. Junction Temperature VGS , GATE TO SOURCE VOLTAGE (V) 10 C, CAPACITANCE (pF) CISS  C GS + CGD COSS @ CDS + CGD 1000 CRSS  C GD 100 VGS = 0V, f = 1MHz 200 VDD = 75V 8 6 4 WAVEFORMS IN DESCENDING ORDER: ID = 33A ID = 16A 2 0 50 1 0 40 80 120 160 TJ , JUNCTION TEMPERATURE (o C) Figure 12. Normalized Drain to Source Breakdown Voltage vs Junction Temperature 10000 0.1 −40 10 150 0 VDS , DRAIN TO SOURCE VOLTAGE (V) 20 40 60 80 Qg, GATE CHARGE (nC) Figure 13. Capacitance vs. Drain to Source Voltage Figure 14. Gate Charge Waveforms for Constant Gate Currents www.onsemi.com 6 100 FDB2532−F085 TEST CIRCUITS WAVEFORMS VDS L VARY tp TO OBTAIN REQUIRED PEAK IAS RG + DUT VGS 0V tp − VDD IAS 0.01 W Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms VDS L VGS + DUT − VDD Ig(REF) Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms VDS RL + VGS − VDD DUT RGS VGS Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms www.onsemi.com 7 FDB2532−F085 Thermal Resistance vs. Mounting Pad Area The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM, in an application. Therefore the application’s ambient temperature, TA (°C), and thermal resistance RqJA (°C/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part. P DM + (T JM * T A) R QJA ON Semiconductor provides thermal information to assist the designer’s preliminary application evaluation. Figure 21 defines the RqJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR−4 board with 1oz copper after 1 000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the ON Semiconductor device Spice thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Thermal resistances corresponding to other copper areas can be obtained from Figure 21 or by calculation using Equation 2 or 3. Equation 2 is used for copper area defined in inches square and equation 3 is for area in centimeter square. The area, in square inches or square centimeters is the top copper area including the gate and source pads. (eq. 1) In using surface mount devices such as the TO−263 (D2−PAK−3) package, the environment in which it is applied will have a significant influence on the part’s current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors: 1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. R QJA + 26.51 ) 19.84 (0.262 ) Area) (eq. 2) 128 (1.69 ) Area) (eq. 3) Area in Inches Squared. R QJA + 26.51 ) Area in Centimeters Squared. 80 RQJA= 26.51+ 19.84/(0.262+Area) EQ.2 RQJA = 26.51+ 128/(1.69+Area) EQ.3 RQJA (o C/W) 60 40 20 0.1 1 10 (0.645) (6.45) AREA, TOP COPPER AREA in2 (cm 2 ) (64.5) Figure 21. Thermal Resistance vs. Mounting Pad Area www.onsemi.com 8 FDB2532−F085 PSPICE Electrical Model .SUBCKT FDB2532 2 1 3 ; rev April 2002 CA 12 8 1.4e−9 CB 15 14 1.6e−9 CIN 6 8 5.61e−9 Dbody 7 5 DbodyMOD Dbreak 5 11 DbreakMOD Dplcap 10 5 DplcapMOD Ebreak 11 7 17 18 159 Eds 14 8 5 8 1 Egs 13 8 6 8 1 Esg 6 10 6 8 1 Evthres 6 21 19 8 1 Evtemp 20 6 18 22 1 It 8 17 1 Lgate 1 9 9.56e−9 Ldrain 2 5 1.0e−9 Lsource 3 7 7.71e−9 RLgate 1 9 95.6 RLdrain 2 5 10 RLsource 3 7 77.1 Mmed 16 6 8 8 MmedMOD Mstro 16 6 8 8 MstroMOD Mweak 16 21 8 8 MweakMOD Rbreak 17 18 RbreakMOD 1 Rdrain 50 16 RdrainMOD 9.6e−3 Rgate 9 20 1.01 RSLC1 5 51 RSLCMOD 1.0e−6 RSLC2 5 50 1.0e3 Rsource 8 7 RsourceMOD 3.0e−3 Rvthres 22 8 RvthresMOD 1 Rvtemp 18 19 RvtempMOD 1 S1a 6 12 13 8 S1AMOD S1b 13 12 13 8 S1BMOD S2a 6 15 14 13 S2AMOD S2b 13 15 14 13 S2BMOD Vbat 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e−6*190),3))} .MODEL DbodyMOD D (IS=6.0E−11 N=1.09 RS=2.3e−3 TRS1=3.0e−3 TRS2=1.0e−6 + CJO=3.9e−9 M=0.65 TT=4.8e−8 XTI=4.2) .MODEL DbreakMOD D (RS=0.17 TRS1=3.0e−3 TRS2=−8.9e−6) .MODEL DplcapMOD D (CJO=1.0e−9 IS=1.0e−30 N=10 M=0.6) .MODEL MmedMOD NMOS (VTO=3.55 KP=10 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=1.01) .MODEL MstroMOD NMOS (VTO=4.2 KP=145 IS=1e−30 N=10 TOX=1 L=1u W=1u) .MODEL MweakMOD NMOS (VTO=2.9 KP=0.05 IS=1e−30 N=10 TOX=1 L=1u W=1u RG=10.1 RS=0.1) .MODEL RbreakMOD RES (TC1=1.1e−3 TC2=−9.0e−7) .MODEL RdrainMOD RES (TC1=9.0e−3 TC2=3.5e−5) .MODEL RSLCMOD RES (TC1=3.4e−3 TC2=1.5e−6) www.onsemi.com 9 FDB2532−F085 .MODEL RsourceMOD RES (TC1=4.0e−3 TC2=1.0e−6) .MODEL RvthresMOD RES (TC1=−4.1e−3 TC2=−1.4e−5) .MODEL RvtempMOD RES (TC1=−4.0e−3 TC2=3.5e−6) .MODEL S1AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−6.0 VOFF=−4.0) .MODEL S1BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−4.0 VOFF=−6.0) .MODEL S2AMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=−1.4 VOFF=1.0) .MODEL S2BMOD VSWITCH (RON=1e−5 ROFF=0.1 VON=1.0 VOFF=−1.4) NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub−Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. Figure 22. PSPICE Electrical Model www.onsemi.com 10 FDB2532−F085 SABER Electrical Model REV April 2002 ttemplate FDB2532 n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (isl=6.0e−11,nl=1.09,rs=2.3e−3,trs1=3.0e−3,trs2=1.0e−6,cjo=3.9e−9,m=0.65,tt=4.8e−8,xti=4.2) dp..model dbreakmod = (rs=0.17,trs1=3.0e−3,trs2=−8.9e−6) dp..model dplcapmod = (cjo=1.0e−9,isl=10.0e−30,nl=10,m=0.6) m..model mmedmod = (type=_n,vto=3.55,kp=10,is=1e−30, tox=1) m..model mstrongmod = (type=_n,vto=4.2,kp=145,is=1e−30, tox=1) m..model mweakmod = (type=_n,vto=2.9,kp=0.05,is=1e−30, tox=1,rs=0.1) sw_vcsp..model s1amod = (ron=1e−5,roff=0.1,von=−6.0,voff=−4.0) sw_vcsp..model s1bmod = (ron=1e−5,roff=0.1,von=−4.0,voff=−6.0) sw_vcsp..model s2amod = (ron=1e−5,roff=0.1,von=−1.4,voff=1.0) sw_vcsp..model s2bmod = (ron=1e−5,roff=0.1,von=1.0,voff=−1.4) c.ca n12 n8 = 1.4e−9 c.cb n15 n14 = 1.6e−9 c.cin n6 n8 = 5.61e−9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.dplcap n10 n5 = model=dplcapmod spe.ebreak n11 n7 n17 n18 = 159 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evthres n6 n21 n19 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 i.it n8 n17 = 1 l.lgate n1 n9 = 9.56e−9 l.ldrain n2 n5 = 1.0e−9 l.lsource n3 n7 = 7.71e−9 res.rlgate n1 n9 = 95.6 res.rldrain n2 n5 = 10 res.rlsource n3 n7 = 77.1 m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1=1.1e−3,tc2=−9.0e−7 res.rdrain n50 n16 = 9.6e−3, tc1=9.0e−3,tc2=3.5e−5 res.rgate n9 n20 = 1.01 res.rslc1 n5 n51 = 1.0e−6, tc1=3.4e−3,tc2=1.5e−6 res.rslc2 n5 n50 = 1.0e3 res.rsource n8 n7 = 3.0e−3, tc1=4.0e−3,tc2=1.0e−6 res.rvthres n22 n8 = 1, tc1=−4.1e−3,tc2=−1.4e−5 res.rvtemp n18 n19 = 1, tc1=−4.0e−3,tc2=3.5e−6 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod www.onsemi.com 11 FDB2532−F085 v.vbat n22 n19 = dc=1 equations { i (n51−>n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e−9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/190))** 3)) } } Figure 23. SABER Electrical Model www.onsemi.com 12 FDB2532−F085 SPICE Thermal Model REV 26 February 2002 th JUNCTION FDB2532 CTHERM1 TH 6 7.5e−3 CTHERM2 6 5 8.0e−3 CTHERM3 5 4 9.0e−3 CTHERM4 4 3 2.4e−2 CTHERM5 3 2 3.4e−2 CTHERM6 2 TL 6.5e−2 CTHERM1 RTHERM1 6 RTHERM1 TH 6 3.1e−4 RTHERM2 6 5 2.5e−3 RTHERM3 5 4 2.0e−2 RTHERM4 4 3 8.0e−2 RTHERM5 3 2 1.2e−1 RTHERM6 2 TL 1.3e−1 CTHERM2 RTHERM2 5 SABER Thermal Model SABER thermal model FDB2532 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 6 =7.5e−3 ctherm.ctherm2 6 5 =8.0e−3 ctherm.ctherm3 5 4 =9.0e−3 ctherm.ctherm4 4 3 =2.4e−2 ctherm.ctherm5 3 2 =3.4e−2 ctherm.ctherm6 2 tl =6.5e−2 CTHERM3 RTHERM3 4 CTHERM4 RTHERM4 3 rrtherm.rtherm1 th 6 =3.1e−4 rtherm.rtherm2 6 5 =2.5e−3 rtherm.rtherm3 5 4 =2.0e−2 rtherm.rtherm4 4 3 =8.0e−2 rtherm.rtherm5 3 2 =1.2e−1 rtherm.rtherm6 2 tl =1.3e−1 } CTHERM5 RTHERM5 2 CTHERM6 RTHERM6 tl CASE Figure 24. Thermal Model POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 13 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS D2PAK−3 (TO−263, 3−LEAD) CASE 418AJ ISSUE F SCALE 1:1 GENERIC MARKING DIAGRAMS* XX XXXXXXXXX AWLYWWG IC DOCUMENT NUMBER: DESCRIPTION: XXXXXXXXG AYWW Standard 98AON56370E AYWW XXXXXXXXG AKA Rectifier XXXXXX XXYMW SSG DATE 11 MAR 2021 XXXXXX = Specific Device Code A = Assembly Location WL = Wafer Lot Y = Year WW = Work Week W = Week Code (SSG) M = Month Code (SSG) G = Pb−Free Package AKA = Polarity Indicator *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. D2PAK−3 (TO−263, 3−LEAD) PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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