FDC633N_F095

March 1998 FDC633N N-Channel Enhancement Mode Field Effect Transistor General Description Features This N-Channel enhancement mode power field effect transistors is produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications in notebook computers, portable phones, PCMICA cards, and other battery powered circuits where fast switching,low in-line power loss and resistance to transients are needed in a very small outline surface mount package. SOT-23 SuperSOTTM-6 SuperSOTTM-8 5.2 A, 30 V. RDS(ON) = 0.042 Ω @ VGS = 4.5 V RDS(ON) = 0.054 Ω @ VGS = 2.5 V. SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. SOIC-16 SOT-223 SO-8 S D D .63 1 6 2 5 3 4 3 G SuperSOT TM pin 1 -6 D D Absolute Maximum Ratings T A = 25°C unless otherwise noted Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage - Continuous ID Drain Current - Continuous PD Maximum Power Dissipation Units 30 V ±8 V (Note 1a) 5.2 A (Note 1a) 1.6 (Note 1b) 0.8 - Pulsed TJ,TSTG FDC633N 16 Operating and Storage Temperature Range W -55 to 150 °C THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 78 °C/W RθJC Thermal Resistance, Junction-to-Case (Note 1) 30 °C/W © 1998 Fairchild Semiconductor Corporation FDC633N Rev.C ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA ∆BVDSS/∆TJ Breakdown Voltage Temp. Coefficient ID = 250 µA, Referenced to 25 oC 30 IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V V mV/oC 42 o 1 µA 10 µA IGSSF Gate - Body Leakage, Forward VGS = 8 V, VDS = 0 V 100 nA IGSSR Gate - Body Leakage, Reverse VGS = -8 V, VDS = 0 V -100 nA 1 V TJ = 55 C ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage 0.4 VDS = VGS, ID = 250 µA ∆VGS(th)/∆TJ Gate Threshold VoltageTemp.Coefficient ID = 250 µA, Referenced to 25 C RDS(ON) Static Drain-Source On-Resistance VGS = 4.5 V, ID = 5.2 A o 0.67 mV/oC -2.4 o TJ = 125 C VGS = 2.5 V, ID = 4.5 A 0.033 0.042 0.051 0.07 0.043 0.054 11 Ω ID(on) On-State Drain Current VGS = 4.5 V, VDS = 5 V gFS Forward Transconductance VDS = 10 V, ID = 5.2 A 15 A S DYNAMIC CHARACTERISTICS Ciss Input Capacitance VDS = 10 V, VGS = 0 V, 538 pF Coss Output Capacitance f = 1.0 MHz 226 pF Crss Reverse Transfer Capacitance 51 pF SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time VDD = 5 V, ID = 1 A, 5 12 ns tr Turn - On Rise Time VGS = 4.5 V, RGEN = 6 Ω 17 27 ns tD(off) Turn - Off Delay Time 25 40 ns tf Turn - Off Fall Time Qg Total Gate Charge VDS = 10 V, ID = 5.2 A, Qgs Gate-Source Charge VGS = 4.5 V Qgd Gate-Drain Charge 5.3 11 ns 11 16 nC 2 nC 2.4 nC DRAIN-SOURCE DIODE CHARACTERISTICS IS Continuous Source Diode Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 1.3 A (Note 2) o TJ = 125 C 1.3 A 0.7 1.2 V 0.57 1 Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a. 78oC/W when mounted on a 1 in2 pad of 2oz Cu on FR-4 board. b. 156oC/W when mounted on a minimum pad of 2oz Cu on FR-4 board. 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. FDC633N Rev.C Typical Electrical Characteristics 2.5 R DS(ON), NORMALIZED I D , DRAIN-SOURCE CURRENT (A) VGS = 4.5V 3.0 15 2.0 10 5 1.5 0 DRAIN-SOURCE ON-RESISTANCE 2 20 1.8 1.4 0.5 1 1.5 2 2.5 2.5 3.0 1.2 3.5 4.5 1 0.8 0 V GS = 2.0V 1.6 3 0 5 10 I D , DRAIN CURRENT (A) VDS , DRAIN-SOURCE VOLTAGE (V) 0.15 R DS(ON) , ON-RESISTANCE (OHM) I D = 5.2A V GS = 4.5V 1.4 1.2 1 0.8 I D = 2.5A 0.12 0.09 TA = 125°C 0.06 0.03 TA = 25°C 0 0.6 -50 1 -25 0 25 50 75 100 TJ , JUNCTION TEMPERATURE (°C) 125 GS Figure 3. On-Resistance Variation with Temperature. 15 TJ = -55°C VDS = 5V 25°C 12 125°C 9 6 3 0.5 1 V GS 1.5 2 , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 4 5 2.5 VGS = 0V TJ = 125°C 1 25°C 0.1 -55°C 0.01 0.001 0.0001 0 3 , GATE TO SOURCE VOLTAGE (V) Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 15 0 2 V 150 I S , REVERSE DRAIN CURRENT (A) R DS(ON) , NORMALIZED 1.6 DRAIN-SOURCE ON-RESISTANCE 20 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. Figure 1. On-Region Characteristics. I D, DRAIN CURRENT (A) 15 0 0.2 0.4 0.6 0.8 1 1.2 VSD , BODY DIODE FORWARD VOLTAGE (V) Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDC633N Rev.C Typical Electrical Characteristics (continued) 1300 I D = 5.2A VDS = 5V 10V 4 600 15V CAPACITANCE (pF) V GS , GATE-SOURCE VOLTAGE (V) 5 3 2 300 Coss 100 1 50 0 0 3 6 9 12 Crss f = 1 MHz VGS = 0 V 20 0.1 15 Q g , GATE CHARGE (nC) 0.3 1 3 10 30 VDS , DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics. 40 5 100 MIT ) LI (ON S RD 10 5 us 1m s 10m s 10 0m s 2 1 0.5 1s VGS = 4.5V SINGLE PULSE RθJA = See Note 1b T A A = 25°C 0.1 0.05 0.01 0.1 0.2 0.5 SINGLE PULSE RθJA =See note 1b TA = 25°C 4 POWER (W) 20 3 2 DC 1 0 0.01 1 2 5 10 30 0.1 50 1 10 100 300 SINGLE PULSE TIME (SEC) V DS , DRAIN-SOURCE VOLTAGE (V) Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. TRANSIENT THERMAL RESISTANCE 1 r(t), NORMALIZED EFFECTIVE I D , DRAIN CURRENT (A) Ciss 0.5 D = 0.5 0.2 0.1 0.05 R JA (t) = r(t) * R θJA θ R = See Note 1b θJA 0.2 0.1 P(pk) 0.05 t1 0.02 0.02 0.01 t2 TJ - TA = P * R θJA (t) 0.01 Duty Cycle, D = t 1/ t 2 Single Pulse 0.005 0.00001 0.0001 0.001 0.01 0.1 1 10 100 300 t 1, TIME (sec) Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in note 1b. Transient thermal response will change depending on the circuit board design. FDC633N Rev.C TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST  FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench  QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER  SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET  VCX™ STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4