FDD2612

FDD2612 200V N-Channel PowerTrench MOSFET General Description Features This N-Channel MOSFET has been designed specifically to improve the overall efficiency of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low RDS(ON) and fast switching speed. • 4.9 A, 200 V. RDS(ON) = 720 mΩ @ VGS = 10 V • High performance trench technology for extremely low RDS(ON) • High power and current handling capability Applications • Fast switching speed • DC/DC converter • Low gate charge (8nC typical) D D G G S TO-252 S Absolute Maximum Ratings Symbol TA=25oC unless otherwise noted Ratings Units VDSS Drain-Source Voltage Parameter 200 V VGSS Gate-Source Voltage ± 20 V ID Drain Current 4.9 A – Continuous (Note 1a) – Pulsed PD 10 Power Dissipation TJ, TSTG W (Note 1) 42 (Note 1a) 3.8 (Note 1b) 1.6 −55 to +175 °C Operating and Storage Junction Temperature Range Thermal Characteristics RθJC Thermal Resistance, Junction-to-Case (Note 1) 3.5 °C/W RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 40 °C/W RθJA Thermal Resistance, Junction-to-Ambient (Note 1b) 96 °C/W Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity FDD2612 FDD2612 13’’ 16mm 2500 units 2001 Fairchild Semiconductor Corporation FDD2612 Rev B1 (W) FDD2612 August 2001 Symbol TA = 25°C unless otherwise noted Parameter Test Conditions Min Typ Max Units Drain-Source Avalanche Ratings (Note 2) WDSS Drain-Source Avalanche Energy IAR Drain-Source Avalanche Current Single Pulse,VDD = 100 V,ID = 1.5A 90 mJ 1.5 A Off Characteristics ID = 250 µA 200 V BVDSS ∆BVDSS ∆TJ IDSS Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current VDS = 160 V, VGS = 0 V IGSSF Gate–Body Leakage, Forward VGS = 20 V, VDS = 0 V 100 nA IGSSR Gate–Body Leakage, Reverse VGS = –20 V , VDS = 0 V –100 nA 4.5 V On Characteristics VGS(th) ∆VGS(th) ∆TJ VGS = 0 V, ID = 250 µA, Referenced to 25°C mV/°C µA 1 (Note 2) ID = 250 µA VDS = VGS, ID = 250 µA, Referenced to 25°C ID(on) Gate Threshold Voltage Gate Threshold Voltage Temperature Coefficient Static Drain–Source On Resistance On–State Drain Current ID = 1.5 A VGS = 10 V, VGS = 10 V, ID = 1.5 A,TJ = 125°C VGS = 10 V, VDS = 10 V gFS Forward Transconductance VDS = 10 V, RDS(on) 246 2 4 – 8.6 600 1125 mV/°C 720 1422 mΩ 5 A ID = 1.5 A 4.4 S V GS = 0 V, 234 pF 18 pF 8 pF Dynamic Characteristics VDS = 100 V, f = 1.0 MHz Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Switching Characteristics td(on) Turn–On Delay Time tr Turn–On Rise Time td(off) tf Qg Total Gate Charge Qgs Gate–Source Charge Qgd Gate–Drain Charge (Note 2) VDD = 100 V, VGS = 10 V, ID = 1 A, RGEN = 6 Ω 6 12 ns 6 12 ns Turn–Off Delay Time 17 30 ns Turn–Off Fall Time 8 16 ns 8 11 nC VDS = 100 V, VGS = 10 V ID = 1.5 A, 1.6 nC 2.2 nC Drain–Source Diode Characteristics and Maximum Ratings IS VSD Maximum Continuous Drain–Source Diode Forward Current Drain–Source Diode Forward VGS = 0 V, IS = 3.2 A Voltage (Note 2) 0.8 3.2 A 1.2 V Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) RθJA = 40°C/W when mounted on a 2 1in pad of 2 oz copper b) RθJA = 96°C/W when mounted on a minimum pad. Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% 3. Maximum current is calculated as: PD RDS(ON) where PD is maximum power dissipation at TC = 25°C and RDS(on) is at TJ(max) and VGS = 10V. Package current limitation is 21A FDD2612 Rev B1(W) FDD2612 Electrical Characteristics FDD2612 Typical Characteristics 5 1.3 RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE VGS =10V ID, DRAIN CURRENT (A) 6.0V 6.5V 4 3 5.5V 2 1 0 0 2 4 6 8 10 VGS = 5.5V 1.2 6.0V 1.1 6.5V 1 0.9 12 0 1 VDS, DRAIN-SOURCE VOLTAGE (V) 2 3 4 5 ID, DRAIN CURRENT (A) Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 2.6 1.4 ID = 0.8A RDS(ON), ON-RESISTANCE (OHM) ID = 1.5A VGS = 10V 2.2 1.8 1.4 1 0.6 1.2 TA = 125oC 1 0.8 0.6 TA = 25oC 0.2 0.4 -50 -25 0 25 50 75 100 125 150 175 4 5 6 o TJ, JUNCTION TEMPERATURE ( C) 7 8 9 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. On-Resistance Variation with Temperature. Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 10 8 IS, REVERSE DRAIN CURRENT (A) VDS = 25V ID, DRAIN CURRENT (A) RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 7.5V 10V 6 4 TA = 125oC 2 25oC -55oC VGS = 0V 1 TA = 125oC 0.1 25oC 0.01 -55oC 0.001 0.0001 0 3 4 5 6 VGS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 7 0 0.2 0.4 0.6 0.8 1 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDD2612 Rev B1(W) FDD2612 Typical Characteristics 350 ID = 1.5A VDS = 50V 100V f = 1MHz VGS = 0 V 300 12 CISS CAPACITANCE (pF) VGS, GATE-SOURCE VOLTAGE (V) 15 150V 9 6 250 200 150 100 3 COSS 50 CRSS 0 0 0 2 4 6 8 0 10 40 Figure 7. Gate Charge Characteristics. 160 200 100 P(pk), PEAK TRANSIENT POWER (W) 100µs 10 1ms 10ms 100ms RDS(ON) LIMIT 1 1s 10s DC 0.1 VGS = 10V SINGLE PULSE RθJA = 96oC/W 0.01 TA = 25oC 0.001 0.1 1 10 100 1000 SINGLE PULSE RθJA =96°C/W TA = 25°C 80 60 40 20 0 0.01 0.1 1 VDS, DRAIN-SOURCE VOLTAGE (V) 10 100 1000 t1, TIME (sec) Figure 9. Maximum Safe Operating Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 120 Figure 8. Capacitance Characteristics. 100 ID, DRAIN CURRENT (A) 80 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 10. Single Pulse Maximum Power Dissipation. 1 D = 0.5 RθJA(t) = r(t) + RθJA RθJA = 96 °C/W 0.2 0.1 0.1 0.05 P(pk) t1 0.02 0.01 t2 0.01 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 SINGLE PULSE 0.001 0.0001 0.001 0.01 0.1 1 10 100 1000 Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1b. Transient thermal response will change depending on the circuit board design. FDD2612 Rev B1(W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ DenseTrench™ DOME™ EcoSPARK™ E2CMOSTM EnSignaTM FACT™ FACT Quiet Series™ FAST  FASTr™ FRFET™ GlobalOptoisolator™ GTO™ HiSeC™ ISOPLANAR™ LittleFET™ MicroFET™ MicroPak™ MICROWIRE™ OPTOLOGIC™ OPTOPLANAR™ PACMAN™ POP™ Power247™ PowerTrench  QFET™ QS™ QT Optoelectronics™ Quiet Series™ SILENT SWITCHER  SMART START™ STAR*POWER™ Stealth™ SuperSOT™-3 SuperSOT™-6 SuperSOT™-8 SyncFET™ TinyLogic™ TruTranslation™ UHC™ UltraFET  VCX™ STAR*POWER is used under license DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H4