FDD9510L-F085

FDD9510L-F085

  • 厂商:

    ONSEMI(安森美)

  • 封装:

    TO-252(DPAK)

  • 描述:

    特性:典型 RDS(on) = 11 mΩ,VGS = -10V,ID = -50A。典型 Qg(tot) = 28 nC,VGS = -10V,ID = -50A。UIS 能力。符合 AEC Q10...

  • 数据手册
  • 价格&库存
FDD9510L-F085 数据手册
MOSFET - P-Channel Logic Level PowerTrench) -40 V, 13.5 mW, -50 A FDD9510L-F085 Features • • • • • Typ RDS(on) = 11 mW at VGS = −10 V; ID = −50 A Typ Qg(tot) = 28 nC at VGS = −10 V; ID = −50 A UIS Capability Qualified to AEC Q101 These Devices are Pb−Free and are RoHS Compliant www.onsemi.com D G Applications • • • • • • • S DPAK TO−252 CASE 369AS Automotive Engine Control Powertrain Management Solenoid and Motor Drivers Electrical Power Steering Integrated Starter/Alternator Distributed Power Architectures and VRM Primary Switch for 12 V Systems D G ABSOLUTE MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain to Source Voltage VDSS −40 V Gate to Source Voltage VGS ±16 V Drain Current − Continuous (VGS = −10 V) (TC = 25°C) (Note 1) ID −50 A Pulsed Drain Current (TC = 25°C) ID See Figure 4 A Single Pulse Avalanche Energy (Note 2) EAS 35.3 mJ Power Dissipation PD 75 W Derate above 25°C PD 0.5 W/°C TJ, TSTG −55 to +175 °C Operating and Storage Temperature Range Thermal Resistance (Junction to Case) RqJC 2 °C/W Maximum Thermal Resistance (Junction to Ambient) (Note 3) RqJA 52 °C/W S ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Current is limited by wirebond configuration 2. Starting Tj = 25°C, L = 40 mH, IAS = −42 A, VDD = −40 V during inductor charging and VDD = 0 V during time in avalanche 3. RqJA is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RqJC is guaranteed by design while RqJA is determined by the user’s board design. The maximum rating presented here is based on mounting on a 1 in2 pad of 2 oz copper. © Semiconductor Components Industries, LLC, 2018 February, 2020 − Rev. 1 1 Publication Order Number: FDD9510L−F085/D FDD9510L−F085 PACKAGE MARKING AND ORDERING INFORMATION Device Device Marking Package Reel Size Tape Width Quantity FDD9510L−F085 FDD9510L D−PAK (TO−252) 13″ 16 mm 2500 Units ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Conditions Min Typ Max Unit −40 − − V TJ = 25_C − − −1 mA TJ = 175_C (Note 4) − − −1 mA VGS = ±16 V − − ±100 nA OFF CHARACTERISTICS BVDSS IDSS IGSS Drain to Source Breakdown Voltage VGS = 0 V, ID = −250 mA Drain to Source Leakage Current VDS = −40 V, VGS = 0 V Gate to Source Leakage Current ON CHARACTERISTICS VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 mA −1 −1.9 −3 V RDS(on) Drain to Source On−Resistance VGS = −4.5 V, ID = −50 A, TJ = 25_C − 16 22 mW VGS = −10 V, ID = −50 A TJ = 25_C − 11 13.5 mW TJ = 175_C (Note 4) − 18 22.7 mW − 2020 − pF DYNAMIC CHARACTERISTICS VDS = −20 V, VGS = 0 V, f = 1 MHz Ciss Input Capacitance Coss Output Capacitance − 785 − pF Crss Reverse Transfer Capacitance − 36 − pF Rg Gate Resistance VGS = −0.5 V, f = 1 MHz − 23 − W Qg(tot) Total Gate Charge VGS = 0 V to −10 V − 28 37 nC Qg(−4.5) Total Gate Charge VDD = −20 V, ID = −50 A VGS = 0 V to −4.5 V − 13 − nC VGS = 0 V to −1 V − 2 − nC − 7 − nC − 4 − nC − − 44 ns − 8 − ns Qg(th) Threshold Gate Charge Qgs Gate to Source Gate Charge Qgd Gate to Drain “Miller” Charge VDD = −20 V, ID = −50 A SWITCHING CHARACTERISTICS ton Turn-On Time VDD = −20 V, ID = −50 A, VGS = −10 V, RGEN = 6 W td(on) Turn-On Delay Time tr Turn-On Rise Time − 21 − ns td(off) Turn-Off Delay Time − 113 − ns Turn-Off Fall Time − 35 − ns Turn-Off Time − − 220 ns VGS = 0 V, ISD = −50 A − −0.97 −1.25 V VGS = 0 V, ISD = −25 A − −0.9 −1.2 V IF = −50 A, dISD/dt = 100 A/ms − 42 63 ns − 31 56 nC tf toff DRAIN−SOURCE DIODE CHARACTERISTICS VSD Source to Drain Diode Voltage Trr Reverse Recovery Time Qrr Reverse Recovery Charge Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. The maximum value is specified by design at TJ = 175°C. Product is not tested to this condition in production www.onsemi.com 2 FDD9510L−F085 NORMALIZED THERMAL IMPEDANCE (ZqJC) 1.2 70 1.0 60 −ID, DRAIN CURRENT (A) POWER DISSIPATION MULTIPLIER TYPICAL CHARACTERISTICS 0.8 0.6 0.4 0.2 0 25 0 75 50 100 125 150 50 40 30 20 VGS = −10 V 10 0 175 Current Limited by Package 25 50 75 125 100 150 175 TC, CASE TEMPERATURE (°C) TC, CASE TEMPERATURE (°C) Figure 1. Normalized Power Dissipation vs. Case Temperature Figure 2. Maximum Continuous Drain Current vs. Case Temperature 2 1 Duty Cycle = 0.5 0.2 PDM 0.1 0.1 0.05 t1 0.02 0.01 t2 DUTY CYCLE, D = t1/t2 Peak TJ = PDM X ZqJA X RqJA + TC 0.01 Single Pulse 0.00001 0.0001 0.001 0.01 1 0.1 10 t, RECTANGULAR PULSE DURATION (s) Figure 3. Normalized Maximum Transient Thermal Impedance 1000 TC = 25°C For temperatures above 25°C derate peak current as follows: −IDM, PEAK CURRENT (A) VGS = −10 V ƪǸ I + I 25 ƫ 175 * T C 150 100 Single Pulse 10 0.00001 0.0001 0.001 0.01 t, RECTANGULAR PULSE DURATION (s) Figure 4. Peak Current Capability www.onsemi.com 3 0.1 1 10 FDD9510L−F085 TYPICAL CHARACTERISTICS 100 Operation in this Area may be Limited by RDS(on) 0.1 1 ms 10 ms 100 ms Single Pulse TJ = Max Rated TC = 25°C 1 10 TJ = 25°C 30 TJ = 175°C 2 TJ = −55°C 3 5 4 0.01 0.1 10 1 100 VGS = 0 V 10 1 0.1 TJ = 175°C 0.01 0.001 7 6 300 100 TJ = −55°C TJ = 25°C 0 0.2 0.4 0.6 0.8 1.0 1.2 −VGS, GATE−TO−SOURCE VOLTAGE (V) −VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 7. Transfer Characteristics Figure 8. Forward Diode Characteristics 150 7.0 V VGS = 10 V 5.0 V 100 4.5 V 4.0 V 50 3.5 V Pulse Width = 250 ms TJ = 25°C 0 0.001 Figure 6. Unclamped Inductive Switching Capability 60 0 NOTE: Refer to ON Semiconductor Application Notes AN7514 and AN7515 Figure 5. Forward Bias Safe Operating Area VDD = −5 V 150 Starting TJ = 150°C tAV, TIME IN AVALANCHE (mS) Pulse Duration = 250 ms Duty Cycle = 0.5% Max 1 10 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) 90 0 If R = 0, tAV=(L)(IAS)/(1.3*Rated BVDSS− VDD) If R ≠ 0, tAV=(L/R)In[(IAS*R)/(1.3*Rated BVDSS− VDD)+1] Starting TJ = 25°C 1 100 −IS, REVERSE DRAIN CURRENT (A) 1 120 −ID, DRAIN CURRENT (A) 100 ms Operation in this Area may be Limited by Package 10 0.1 −ID, DRAIN CURRENT (A) −IAS, AVALANCHE CURRENT (A) 100 −ID, DRAIN CURRENT (A) −ID, DRAIN CURRENT (A) 1000 1 2 3 4 5.0 V 100 4.5 V 4.0 V 50 0 5 7.0 V VGS = 10 V 3.5 V Pulse Width = 250 ms TJ = 175°C 0 1 2 3 4 −VDS, DRAIN−SOURCE VOLTAGE (V) −VDS, DRAIN−SOURCE VOLTAGE (V) Figure 9. Saturation Characteristics Figure 10. Saturation Characteristics www.onsemi.com 4 5 FDD9510L−F085 TYPICAL CHARACTERISTICS 1.8 RDS(on), NORMALIZED DRAIN− SOURCE ON−RESISTANCE 70 60 50 ID = −50 A 40 30 TJ = 175°C 20 TJ = 25°C 10 0 NORMALIZED GATE THRESHOLD VOLTAGE Pulse Duration = 250 ms Duty Cycle = 0.5% Max 3 6 5 4 7 8 9 1.2 1.0 VGS = −10 V ID = −50 A 0.8 −40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (°C) Figure 11. RDS(on) vs. Gate Voltage Figure 12. Normalized RDS(on) vs. Junction Temperature 200 1.10 VGS = VDS ID = −250 mA 1.0 0.8 0.6 0.4 −80 −40 0 40 80 120 160 200 ID = −1 mA 1.05 1.00 0.95 0.90 −80 −40 0 40 80 120 160 200 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 13. Normalized Gate Threshold Voltage vs. Temperature Figure 14. Normalized Drain to Source Breakdown Voltage vs. Junction Temperature −VGS, GATE TO SOURCE VOLTAGE (V) 10,000 Ciss CAPACITANCE (pF) 1.4 −VGS, GATE−TO−SOURCE VOLTAGE (V) 1.2 1000 Coss 100 Crss 10 VGS = 0 V f = 1 MHz 1 1.6 0.6 −80 10 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE RDS(on), ON−RESISTANCE (mW) 80 0.1 1 40 10 10 ID = −50 A 8 VDD = −20 V 6 VDD = −16 V VDD = −24 V 4 2 0 0 6 12 18 24 −VDS, DRAIN−TO−SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 15. Capacitance vs. Drain to Source Voltage Figure 16. Gate Charge vs. Gate to Source Voltage POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC. www.onsemi.com 5 30 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS DPAK3 (TO−252 3 LD) CASE 369AS ISSUE O DOCUMENT NUMBER: DESCRIPTION: 98AON13810G DPAK3 (TO−252 3 LD) DATE 30 SEP 2016 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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