DATA SHEET
www.onsemi.com
MOSFET – Dual N-Channel,
POWERTRENCH®
S2
G2
D1
20V, 1.2A, 175mW
Pin 1
FDG1024NZ
SC−88/SC−70 6 Lead, 1.25 x 2
CASE 419AD
Description
This dual N−Channel logic level enhancement mode field effect
transistors are produced using onsemi’s proprietary, high cell density,
DMOS technology. This very high density process is especially
tailored to minimize on−state resistance. This device has been
designed especially for low voltage applications as a replacement for
bipolar digital transistors and small signal MOSFETs. Since bias
resistors are not required, this dual digital FET can replace several
different digital transistors, with different bias resistor values.
Features
•
•
•
•
•
•
•
•
•
D2
G1
S1
Max rDS(on) = 175 mW at VGS = 4.5 V, ID = 1.2 A
Max rDS(on) = 215 mW at VGS = 2.5 V, ID = 1.0 A
Max rDS(on) = 270 mW at VGS = 1.8 V, ID = 0.9 A
Max rDS(on) = 389 mW at VGS = 1.5 V, ID = 0.8 A
HBM ESD Protection Level > 2 kV (Note 3)
Very Low Level Gate Drive Requirements Allowing Operation
in 1.5 V Circuits (VGS(th) < 1 V)
Very Small Package Outline SC−88/SC−70 6 Lead
RoHS Compliant
These Device is Halogen Free
MARKING DIAGRAM
&E&E&E
&Y
&.4N&G
&E
&Y
&.4N
&G
= Designates Space
= Binary Calendar Year
= Specific Device Code
= 1−Digit Weekly Date Code
ELECTRICAL CONNECTION
S1 1 or 4*
6 or 3
D1
G1
2 or 5
5 or 2
G2
D2 3 or 6
4 or 1*
S2
MOSFET MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Parameter
Symbol
Ratings
Unit
VDS
Drain to Source Voltage
20
V
N−Channel MOSFET
VGS
Gate to Source Voltage
±8
V
Drain Current
1.2
A
* The pinouts are symmetrical; pin 1 and 4 are
interchangeable.
Units inside the carrier can be of either orientation
and will not affect the functionality of the device.
ID
Continuous TA = 25°C
(Note 1a)
Pulsed
PD
TJ, TSTG
Power
Dissipation
6
TA = 25°C (Note 1a)
0.36
TA = 25°C (Note 1b)
0.30
Operating and Storage Junction
Temperature Range
W
−55 to +150
°C
ORDERING INFORMATION
See detailed ordering and shipping information on
page 3 of this data sheet.
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
© Semiconductor Components Industries, LLC, 2010
February, 2022 − Rev. 2
1
Publication Order Number:
FDG1024NZ/D
FDG1024NZ
THERMAL CHARACTERISTICS
Symbol
Ratings
Unit
RqJA
Thermal Resistance, Junction to Ambient (Note 1a)
Parameter
350
_C/W
RqJA
Thermal Resistance, Junction to Ambient (Note 1b)
415
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
OFF CHARACTERISTICS
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
20
−
−
V
DBV DSS
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25°C
−
14
−
mV/°C
IDSS
Zero Gate Voltage Drain Current
VDS = 16 V, VGS = 0 V
−
−
1
μA
IGSS
Gate to Source Leakage Current
VGS = ±8 V, VDS = 0 V
−
−
±10
μA
0.4
0.8
1.0
V
DT J
ON CHARACTERISTICS
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
DV GS(th)
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25°C
−
−3
−
mV/°C
Static Drain to Source On Resistance
VGS = 4.5 V, ID = 1.2 A
−
160
175
mΩ
VGS = 2.5 V, ID = 1.0 A
−
185
215
VGS = 1.8 V, ID = 0.9 A
−
232
270
VGS = 1.5 V, ID = 0.8 A
−
321
389
VGS = 4.5 V, ID = 1.2 A, TJ = 125°C
−
220
259
VDD = 5 V, ID = 1.2 A
−
4
−
S
VDS = 10 V, VGS = 0 V,
f = 1 MHz
−
115
150
pF
−
25
35
pF
DT J
rDS(ON)
gFS
Forward Transconductance
DYNAMIC CHARACTERISTICS
CiSS
Input Capacitance
COSS
Output Capacitance
Crss
Reverse Transfer Capacitance
−
20
25
pF
Gate Resistance
−
4.6
−
Ω
−
3.7
10
ns
−
1.7
10
ns
−
11
19
ns
−
1.5
10
ns
−
1.8
2.6
nC
Rg
SWITCHING CHARACTERISTICS
td(on)
tr
td(off)
tf
Qg
Turn−On Delay Time
Rise Time
VDD = 10 V, ID = 1.2 A,
VGS = 4.5 V, RGEN = 6 Ω
Turn−Off Delay Time
Fall Time
Total Gate Charge
VGS = 4.5 V, VDD = 10 V, ID = 1.2 A
Qgs
Gate to Source Charge
−
0.3
−
nC
Qgd
Gate to Drain “Miller” Charge
−
0.4
−
nC
DRAIN−SOURCE DIODE CHARACTERISTICS
IS
Maximum Continuous Drain−Source Diode Forward Current
−
−
0.3
A
Source to Drain Diode Forward
Voltage
VGS = 0 V, IS = 0.3 A (Note 2)
−
0.7
1.2
V
trr
Reverse Recovery Time
IF = 1.2 A, di/dt = 100 A/ms
−
10
20
ns
Qrr
Reverse Recovery Charge
−
1.9
10
nC
VSD
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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2
FDG1024NZ
NOTES:
1. RqJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. RqJC is guaranteed
by design while RθJA is determined by the user’s board design.
b. 415°C/W when mounted on
a minimum pad of 2 oz copper
a. 350°C/W when mounted
on a 1 in2 pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%.
3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied.
PACKAGE MARKING AND ORDERING INFORMATION
ORDERING INFORMATION
Device Marking
Device
Package
Reel Size
Tape Width
Shipping†
.4N
FDG1024NZ
SC−88/SC−70 6 Lead
(Halogen Free)
7"
8 mm
3000 / Tape and Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
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3
FDG1024NZ
TYPICAL CHARACTERISTICS
(TJ = 25°C unless otherwise noted)
6
Normalized Drain to Source
On−Resistance
VGS = 3.5 V
5
ID, Drain Current (A)
2.5
VGS = 4.5 V
VGS = 2.5 V
4
Pulse Duration = 80 ms
Duty Cycle = 0.5% Max
3
VGS = 1.8 V
2
1
VGS = 1.5 V
0
0
0.4
0.8
1.2
1.6
VGS = 1.5 V
VGS = 2.5 V
2.0
VGS = 3.5 V
1.5
1.0
0.5
2.0
VGS = 4.5 V
Pulse Duration = 80 ms
Duty Cycle = 0.5% Max
0
1
VDS, Drain to Source Voltage (V)
600
ID = 1.2 A
VGS = 4.5 V
1.4
rDS(on), Drain to Source
On−Resistance (mW)
Normalized Drain to Source
On−Resistance
3
1.2
1.0
0.8
0.6
0
−75 −50 −25
25 50 75 100
TJ, Junction Temperature (5C)
300
200
10
IS, Reverse Drain Current (A)
3
2
TJ = 125°C
TJ = −55°C
0
1
2
3
VGS, Gate to Source Voltage (V)
TJ = 25°C
100
1.5
2.0
2.5
3.0
4.0
3.5
4.5
Figure 4. On−Resistance vs. Gate to
Source Voltage
TJ = 25°C
1
TJ = 125°C
VGS, Gate to Source Voltage (V)
VDS = 5 V
4
ID = 1.2 A
400
0
1.0
125 150
Pulse Duration = 80 ms
Duty Cycle = 0.5% Max
5
6
5
Pulse Duration = 80 ms
Duty Cycle = 0.5% Max
500
Figure 3. Normalized On−Resistance vs.
Junction Temperature
6
4
Figure 2. Normalized On−Resistance vs.
Drain Current and Gate Voltage
1.6
ID, Drain Current (A)
2
ID, Drain Current (A)
Figure 1. On−Region Characteristics
0
VGS = 1.8 V
1
TJ = 125°C
TJ = 25°C
0.1
TJ = −55°C
0.01
0.2
4
VGS = 0 V
0.4
0.6
0.8
1.0
1.2
VSD, Body Diode Forward Voltage (V)
Figure 5. Transfer Characteristics
Figure 6. Source to Drain Diode
Forward Voltage vs. Source Current
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4
1.4
FDG1024NZ
TYPICAL CHARACTERISTICS (continued)
(TJ = 25°C unless otherwise noted)
300
ID = 1.2 A
4
Ciss
VDD = 5 V
Capacitance (pF)
VGS, Gate to Source Voltage (V)
5
3
VDD = 10 V
2
VDD = 15 V
1
100
Coss
10
0
0
0.5
1.0
1.5
2.0
5
2.5
0.1
1
Figure 7. Gate Charge Characteristics
Ig, Gate Leakage Current (mA)
ID, Drain Current (A)
105
0.1 ms
1
1 ms
10 ms
Single Pulse
TJ = Max Rated
100 ms
1s
RqJA = 415°C/W
TA = 25°C
0.01
0.01
0.1
DC
1
10
10
14
TJ = 125°C
TJ = 25°C
10−1
0
2
4
6
8
10
VGS, Gate to Source Voltage (V)
Figure 9. Forward Bias Safe Operating Area
P(PK), Peak Transient Power (W)
12
103
10−3
100
VGS = 0 V
VDS, Drain to Source Voltage (V)
100
20
Figure 8. Capacitance vs.
Drain to Source Voltage
This Area is
Limited by rDS(on)
0.1
10
VDS, Drain to Source Voltage (V)
Qg, Gate Charge (nC)
10
Crss
f = 1 MHz
VGS = 0 V
Figure 10. Gate Leakage Current vs.
Gate to Source Voltage
VGS = 4.5 V
Single Pulse
RqJA = 415°C/W
TA = 25°C
10
1
0.1
10−4
10−3
10−2
10−1
1
10
t, Pulse Width (s)
Figure 11. Single Pulse Maximum Power Dissipation
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5
100
1000
FDG1024NZ
TYPICAL CHARACTERISTICS (continued)
(TJ = 25°C unless otherwise noted)
2
Normalized Thermal
Impedance, ZqJA
1
0.1
Duty Cycle−Descending Order
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
0.01
0.001
10−4
t2
Notes:
Duty Factor: D = t1/t2
Peak TJ = PDM x ZqJA x RqJA + TA
Single Pulse
RqJA = 415°C
10−3
10−2
10−1
1
10
100
1000
t, Rectangular Pulse Duration (s)
Figure 12. Transient Thermal Response Curve
POWERTRENCH is a registered trademark of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United
States and/or other countries.
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6
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88 (SC−70 6 Lead), 1.25x2
CASE 419AD
ISSUE A
DATE 07 JUL 2010
1
D
e
e
E1 E
SYMBOL
MIN
A
0.80
MAX
1.10
A1
0.00
0.10
A2
0.80
1.00
b
0.15
0.30
0.18
c
0.10
D
1.80
2.00
2.20
E
1.80
2.10
2.40
E1
1.15
1.25
1.35
0.65 BSC
e
L
0.26
L1
0.36
0.46
0.42 REF
0.15 BSC
L2
TOP VIEW
NOM
θ
0º
8º
θ1
4º
10º
q1
A2 A
q
b
q1
L
L1
A1
SIDE VIEW
c
L2
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-203.
DOCUMENT NUMBER:
DESCRIPTION:
98AON34266E
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
SC−88 (SC−70 6 LEAD), 1.25X2
PAGE 1 OF 1
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are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reserves
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special, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others.
© Semiconductor Components Industries, LLC, 2019
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onsemi,
, and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates
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