Digital FET, Dual N-Channel
FDG6301N
General Description
These dual N−Channel logic level enhancement mode field effect
transistors are produced using ON Semiconductor’s proprietary, high
cell density, DMOS technology. This very high density process is
especially tailored to minimize on−state resistance. This device has
been designed especially for low voltage applications as a replacement
for bipolar digital transistors and small signal MOSFETs.
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G2
G2
D1
Features
D2
G1
S1
• 25 V, 0.22 A Continuous, 0.65 A Peak
RDS(ON) = 4 W @ VGS = 4.5 V
RDS(ON) = 5 W @ VGS = 2.7 V
Very Low Level Gate Drive Requirements Allowing Direct
Operation in 3 V Circuits (VGS(th) < 1.5 V)
Gate−Source Zener for ESD Ruggedness (>6 kV Human Body
Model)
Compact Industry Standard SC70−6 Surface Mount Package
These Devices are Pb−Free and are RoHS Compliant
♦
•
•
•
•
SC−88/SC70−6/SOT−363
CASE 419B−02
♦
ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted)
Symbol
FDG6301N
Units
VDSS
Drain−Source Voltage
Parameter
25
V
VGSS
Gate−Source Voltage
8
V
ID
Drain/Output Current
Continuous
0.22
A
Pulsed
0.65
PD
Maximum Power Dissipation (Note 1)
0.3
W
TJ, TSTG
Operating and Storage Temperature
Range
−55 to +150
°C
6.0
kV
ESD
Electrostatic Discharge Rating
MIL−STD−883D
Human Body Model (100 pF / 1500 W)
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
MARKING DIAGRAM
01M
01
M
= Specific Device Code
= Assembly Operation Month
PIN CONNECTIONS
1 or 4*
6 or 3
2 or 5
5 or 2
3 or 6
4 or 1*
*The pinouts are symmetrical; pin 1 and 4 are
interchangeable.
Units inside the carrier can be of either orientation
and will not affect the functionality of the device.
ORDERING INFORMATION
See detailed ordering and shipping information on page 5 of
this data sheet.
© Semiconductor Components Industries, LLC, 1999
June, 2020 − Rev. 6
1
Publication Order Number:
FDG6301N/D
FDG6301N
THERMAL CHARACTERISTICS
Symbol
RqJA
Parameter
Ratings
Unit
415
_C/W
Thermal Resistance, Junction−to−Ambient (Note 1)
1. RqJA is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder
mounting surface of the drain pins. RqJC is guaranteed by design while RqCA is determined by the user’s board design. RqJA = 415°C/W on
minimum pad mounting on FR−4 board in still air.
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
OFF CHARACTERISTICS
BVDSS
Drain−Source Breakdown Voltage
VGS = 0 V, ID = 250 mA
25
−
−
V
DBVDSS / DTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 mA, Referenced to 25_C
−
25
−
mV/_C
IDSS
Zero Gate Voltage Drain Current
VDS = 20 V, VGS = 0 V
−
−
1
mA
VDS = 20 V, VGS = 0 V, TJ = 55_C
−
−
10
mA
VGS = 8 V, VDS = 0 V
−
−
100
nA
0.65
0.85
1.5
V
IGSS
Gate−Body Leakage Current
ON CHARACTERISTICS (Note 2)
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 mA
DVGS(th) / DTJ
Gate Threshold Voltage
Temperature Coefficient
ID = 250 mA, Referenced to 25_C
−
−2.1
−
mV/_C
Static Drain−Source
On−Resistance
VGS = 4.5 V, ID = 0.22 A
−
2.6
4
W
VGS = 4.5 V, ID = 0.22 A, TJ = 125_C
−
5.3
7
VGS = 2.7 V, ID = 0.19 A
−
3.7
5
On−State Drain Current
VGS = 4.5 V, VDS = 5 V
0.22
−
−
A
Forward Transconductance
VDS = 5 V, ID = 0.22 A
−
0.2
−
S
VDS = 10 V, VGS = 0 V, f = 1.0 MHz
−
9.5
−
pF
RDS(on)
ID(on)
gFS
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
−
6
−
pF
Crss
Reverse Transfer Capacitance
−
1.3
−
pF
−
5
10
ns
−
4.5
10
ns
−
4
8
ns
SWITCHING CHARACTERISTICS (Note 2)
tD(on)
Turn-On Delay Time
tr
Turn-On Rise Time
tD(off)
Turn-Off Delay Time
tf
Turn-Off Fall Time
Qg
Total Gate Charge
Qgs
Gate−Source Charge
Qgd
Gate−Drain Charge
VDD = 5 V, ID = 0.5 A,
VGS = 4.5 V, RGEN = 50 W
VDS = 5 V, ID = 0.22 A,
VGS = 4.5 V
−
3.2
7
ns
−
0.29
0.4
nC
−
0.12
−
nC
−
0.03
−
nC
−
−
0.25
A
−
0.8
1.2
V
DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS
VSD
Maximum Continuous Source Current
Drain−Source Diode Forward
Voltage
VGS = 0 V, IS = 0.25 A (Note 2)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2.0%
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2
FDG6301N
0.5
VGS = 4.5 V
3.5 V
0.4
3.0 V
0.3
2.7 V
2.5 V
0.2
2.0 V
0.1
0
0
1
2
3
4
5
V DS , DRAIN−SOURCE VOLTAGE (V)
RDS(ON) , NORMALIZED
DRAIN−SOURCE ON−RESISTANCE
I D, DRAIN−SOURCE CURRENT (A)
TYPICAL PERFORMANCE CHARACTERISTICS
1.8
I D = 0.22 A
1.6
V GS = 4.5 V
1.4
1.2
1
0.8
0.6
−50
−25
0
25
50
75
100
125
150
VGS = 2.5 V
2.7 V
4
3.0 V
3.5
3.5 V
3
4.0 V
2
0
TJ = −55°C
25 °C
125°C
0.15
0.1
0.05
0
0.5
1
1.5
2
2.5
0.2
0.3
0.4
20
ID = 0.10 A
16
12
8
TA = 125°C
4
25°C
0
1
2
3
4
5
Figure 4. On−Resistance Variation with
Gate−to−Source Voltage
3
IS , REVERSE DRAIN CURRENT (A)
V DS = 5 V
0.1
5.0 V
I D , DRAIN CURRENT (A)
TJ , JUNCTION TEMPERATURE (°C)
0.2
4.5 V
2.5
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. On−Resistance Variation with
Temperature
I D, DRAIN CURRENT (A)
4.5
Figure 2. On−Resistance Variation with
Drain Current and Gate Voltage
RDS(ON), ON−RESISTANCE (W )
RDS(ON) , NORMALIZED
DRAIN−SOURCE ON−RESISTANCE
Figure 1. On−Region Characteristics
5
VGS , GATE TO SOURCE VOLTAGE (V)
0.4
VGS = 0 V
0.1
TJ = 125°C
0.01
25°C
-55°C
0.001
0.0001
0
0.2
0.4
0.6
0.8
1
1.2
VSD , BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature
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3
FDG6301N
6
30
VDS = 5 V
I D = 0.22 A
10 V
5
CAPACITANCE (pF)
VGS , GATE−SOURCE VOLTAGE (V)
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
4
3
2
1
0
0
0.2
0.1
0.4
0.3
C oss
5
3
C rss
f = 1 MHz
VGS = 0 V
Qg , GATE CHARGE (nC)
3
10
50
10 ms
100 ms
1s
10 s
VGS = 4.5 V
SINGLE PULSE
RqJA = 415°C/W
TA = 25°C
0.01
0.4
DC
0.8
2
5
30
20
10
10
25
0
0.0001
40
V DS , DRAIN−SOURCE VOLTAGE (V)
0.001
0.01
0.1
1
10
200
SINGLE PULSE TIME (sec)
Figure 10. Single Pulse Maximum Power
Dissipation
Figure 9. Maximum Safe Operating Area
r(t), NORMALIZED EFFECTIVE
TRANSIENT THERMAL RESISTANCE
25
SINGLE PULSE
RqJA = 415°C/W
TA = 25°C
40
POWER (W)
RDS(ON) LIMIT
0.1
0.03
1
Figure 8. Capacitance Characteristics
1
0.3
0.3
V DS , DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics
I D, DRAIN CURRENT (A)
C iss
8
2
0.1
0.6
0.5
15
1
0.5
D = 0.5
0.2
0.2
0.1
0.05
0.02
0.01
RqJA (t) = r(t) * RqJA
RqJA = 415°C/W
0.1
0.05
P(pk)
0.02
0.01
Single Pulse
t1
0.005
0.002
0.0001
0.001
t2
TJ − TA = P * RqJA (t)
Duty Cycle, D = t1 / t2
0.01
0.1
1
10
t 1, TIME (sec)
Thermal characterization performed using the conditions described in Note 1.
Transient thermal response will change depending on the circuit board design.
Figure 11. Transient Thermal Response Curve
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4
100
200
FDG6301N
ORDERING INFORMATION
Device Order Number
Device Marking
Package Type
Shipping†
FDG6301N
01
SC−88/SC70−6/SOT−363
(Pb−Free)
3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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5
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
1
SCALE 2:1
DATE 11 DEC 2012
2X
aaa H D
D
H
A
D
6
5
GAGE
PLANE
4
1
2
L
L2
E1
E
DETAIL A
3
aaa C
2X
bbb H D
2X 3 TIPS
e
B
6X
b
ddd
TOP VIEW
C A-B D
M
A2
DETAIL A
A
6X
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
THE PLASTIC BODY AND DATUM H.
5. DATUMS A AND B ARE DETERMINED AT DATUM H.
6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OF THE FOOT.
ccc C
A1
SIDE VIEW
C
SEATING
PLANE
END VIEW
c
RECOMMENDED
SOLDERING FOOTPRINT*
6X
DIM
A
A1
A2
b
C
D
E
E1
e
L
L2
aaa
bbb
ccc
ddd
MILLIMETERS
MIN
NOM MAX
−−−
−−−
1.10
0.00
−−−
0.10
0.70
0.90
1.00
0.15
0.20
0.25
0.08
0.15
0.22
1.80
2.00
2.20
2.00
2.10
2.20
1.15
1.25
1.35
0.65 BSC
0.26
0.36
0.46
0.15 BSC
0.15
0.30
0.10
0.10
GENERIC
MARKING DIAGRAM*
6
XXXMG
G
6X
0.30
INCHES
NOM MAX
−−− 0.043
−−− 0.004
0.035 0.039
0.008 0.010
0.006 0.009
0.078 0.086
0.082 0.086
0.049 0.053
0.026 BSC
0.010 0.014 0.018
0.006 BSC
0.006
0.012
0.004
0.004
MIN
−−−
0.000
0.027
0.006
0.003
0.070
0.078
0.045
0.66
1
2.50
0.65
PITCH
XXX = Specific Device Code
M
= Date Code*
G
= Pb−Free Package
(Note: Microdot may be in either location)
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
*Date Code orientation and/or position may
vary depending upon manufacturing location.
*This information is generic. Please refer to
device data sheet for actual part marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present.
STYLES ON PAGE 2
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 1 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
DATE 11 DEC 2012
STYLE 1:
PIN 1. EMITTER 2
2. BASE 2
3. COLLECTOR 1
4. EMITTER 1
5. BASE 1
6. COLLECTOR 2
STYLE 2:
CANCELLED
STYLE 3:
CANCELLED
STYLE 4:
PIN 1. CATHODE
2. CATHODE
3. COLLECTOR
4. EMITTER
5. BASE
6. ANODE
STYLE 5:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 6:
PIN 1. ANODE 2
2. N/C
3. CATHODE 1
4. ANODE 1
5. N/C
6. CATHODE 2
STYLE 7:
PIN 1. SOURCE 2
2. DRAIN 2
3. GATE 1
4. SOURCE 1
5. DRAIN 1
6. GATE 2
STYLE 8:
CANCELLED
STYLE 9:
PIN 1. EMITTER 2
2. EMITTER 1
3. COLLECTOR 1
4. BASE 1
5. BASE 2
6. COLLECTOR 2
STYLE 10:
PIN 1. SOURCE 2
2. SOURCE 1
3. GATE 1
4. DRAIN 1
5. DRAIN 2
6. GATE 2
STYLE 11:
PIN 1. CATHODE 2
2. CATHODE 2
3. ANODE 1
4. CATHODE 1
5. CATHODE 1
6. ANODE 2
STYLE 12:
PIN 1. ANODE 2
2. ANODE 2
3. CATHODE 1
4. ANODE 1
5. ANODE 1
6. CATHODE 2
STYLE 13:
PIN 1. ANODE
2. N/C
3. COLLECTOR
4. EMITTER
5. BASE
6. CATHODE
STYLE 14:
PIN 1. VREF
2. GND
3. GND
4. IOUT
5. VEN
6. VCC
STYLE 15:
PIN 1. ANODE 1
2. ANODE 2
3. ANODE 3
4. CATHODE 3
5. CATHODE 2
6. CATHODE 1
STYLE 16:
PIN 1. BASE 1
2. EMITTER 2
3. COLLECTOR 2
4. BASE 2
5. EMITTER 1
6. COLLECTOR 1
STYLE 17:
PIN 1. BASE 1
2. EMITTER 1
3. COLLECTOR 2
4. BASE 2
5. EMITTER 2
6. COLLECTOR 1
STYLE 18:
PIN 1. VIN1
2. VCC
3. VOUT2
4. VIN2
5. GND
6. VOUT1
STYLE 19:
PIN 1. I OUT
2. GND
3. GND
4. V CC
5. V EN
6. V REF
STYLE 20:
PIN 1. COLLECTOR
2. COLLECTOR
3. BASE
4. EMITTER
5. COLLECTOR
6. COLLECTOR
STYLE 21:
PIN 1. ANODE 1
2. N/C
3. ANODE 2
4. CATHODE 2
5. N/C
6. CATHODE 1
STYLE 22:
PIN 1. D1 (i)
2. GND
3. D2 (i)
4. D2 (c)
5. VBUS
6. D1 (c)
STYLE 23:
PIN 1. Vn
2. CH1
3. Vp
4. N/C
5. CH2
6. N/C
STYLE 24:
PIN 1. CATHODE
2. ANODE
3. CATHODE
4. CATHODE
5. CATHODE
6. CATHODE
STYLE 25:
PIN 1. BASE 1
2. CATHODE
3. COLLECTOR 2
4. BASE 2
5. EMITTER
6. COLLECTOR 1
STYLE 26:
PIN 1. SOURCE 1
2. GATE 1
3. DRAIN 2
4. SOURCE 2
5. GATE 2
6. DRAIN 1
STYLE 27:
PIN 1. BASE 2
2. BASE 1
3. COLLECTOR 1
4. EMITTER 1
5. EMITTER 2
6. COLLECTOR 2
STYLE 28:
PIN 1. DRAIN
2. DRAIN
3. GATE
4. SOURCE
5. DRAIN
6. DRAIN
STYLE 29:
PIN 1. ANODE
2. ANODE
3. COLLECTOR
4. EMITTER
5. BASE/ANODE
6. CATHODE
STYLE 30:
PIN 1. SOURCE 1
2. DRAIN 2
3. DRAIN 2
4. SOURCE 2
5. GATE 1
6. DRAIN 1
DOCUMENT NUMBER:
DESCRIPTION:
98ASB42985B
SC−88/SC70−6/SOT−363
Electronic versions are uncontrolled except when accessed directly from the Document Repository.
Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.
PAGE 2 OF 2
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the
rights of others.
© Semiconductor Components Industries, LLC, 2019
www.onsemi.com
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
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