FDG6302P

July 1999 FDG6302P Dual P-Channel, Digital FET General Description Features -25 V, -0.14 A continuous, -0.4 A peak. RDS(ON) = 10 Ω @ VGS= -4.5 V, RDS(ON) = 13 Ω @ VGS= -2.7 V. These dual P-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1.5 V). Gate-Source Zener for ESD ruggedness (>6kV Human Body Model). Compact industry standard SC70-6 surface mount package. SC70-6 SuperSOTTM-6 SOT-23 D1 G2 SO-8 SuperSOTTM-8 SOT-223 S2 .02 . S1 SC70-6 G1 D2 1 or 4 * 6 or 3 2 or 5 5 or 2 3 or 6 4 or 1 * *The pinouts are symmetrical; pin 1 and 4 are interchangeable. Units inside the carrier can be of either orientation and will not affect the functionality of the device. Absolute Maximum Ratings Symbol Parameter VDSS Drain-Source Voltage VGSS Gate-Source Voltage ID Drain/Output Current PD Maximum Power Dissipation TA = 25°C unless otherwise noted - Continuous - Pulsed FDG6302P Units -25 V -8 V -0.14 A -0.4 (Note 1) TJ,TSTG Operating and Storage Temperature Range ESD Electrostatic Discharge Rating MIL-STD-883D Human Body Model (100 pF / 1500 Ω) 0.3 W -55 to 150 °C 6.0 kV 415 °C/W THERMAL CHARACTERISTICS RθJA Thermal Resistance, Junction-to-Ambient (Note 1) FDG6302P Rev.F1 Electrical Characteristics (TA = 25 OC unless otherwise noted) Symbol Parameter Conditions Min -25 Typ Max Units OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA ∆BVDSS/∆TJ Breakdown Voltage Temp. Coefficient ID = -250 µA, Referenced to 25oC IDSS Zero Gate Voltage Drain Current VDS = -20 V, VGS = 0 V V TJ = 55°C IGSS Gate - Body Leakage Current mV / oC -19 VGS = -8 V, VDS = 0 V -1 µA -10 µA -100 nA ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = -250 µA ∆VGS(th)/∆TJ Gate Threshold Voltage Temp.Coefficient ID = -250 µA, Referenced to 25oC -0.65 RDS(ON) Static Drain-Source On-Resistance VGS = -4.5 V, ID = -0.14 A -0.9 -1.5 TJ =125°C VGS = -2.7 V, ID = -0.05 A V mV / oC 2 7.3 10 11 17 10.4 13 -0.14 Ω ID(ON) On-State Drain Current VGS = -4.5 V, VDS = -5 V A gFS Forward Transconductance VDS = -5 V, ID = -0.14 A 0.12 S VDS = -10 V, VGS = 0 V, f = 1.0 MHz 12 pF 7 pF 1.5 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 2) tD(on) Turn - On Delay Time tr Turn - On Rise Time tD(off) Turn - Off Delay Time tf Turn - Off Fall Time Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge VDD = -5 V, ID = -0.25 A, VGS = -4.5 V, RGEN = 6 Ω VDS = -5 V, ID = -0.14 A, VGS = -4.5 V 5 12 ns 8 16 ns 9 18 ns 5 10 ns 0.22 0.31 nC 0.12 nC 0.05 nC DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS Maximum Continuous Source Current VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = -0.25 A (Note 2) -0.8 -0.25 A -1.2 V Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. RθJA = 415OC/W on minimum pad mounting on FR-4 board in still air. 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. FDG6302P Rev.F1 Typical Electrical Characteristics 2.5 VGS = -4.5V -3.5V R DS(ON), NORMALIZED -3.0V 0.15 -2.7V -2.5V 0.1 -2.0V 0.05 0 0 1 2 3 DRAIN-SOURCE ON-RESISTANCE -I D , DRAIN-SOURCE CURRENT (A) 0.2 VGS = -2.0V 2 -2.7V -3.5V 0.1 0.15 0.2 25 R DS(ON) , ON-RESISTANCE (OHM) I D = -0.14A V GS = -4.5V 1.4 1.2 1 0.8 0.6 -50 -25 0 25 50 75 100 125 150 TJ , JUNCTION TEMPERATURE (°C) I D = -0.07A 20 15 TA = 125°C 10 TA = 25°C 5 0 1.5 2 Figure 3. On-Resistance Variation with Temperature. 0.3 TA = -55°C 0.12 25°C 125°C 0.1 0.08 0.06 0.04 0.02 0 1 2 3 -VGS , GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 3 3.5 4 4.5 5 Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 0.14 VDS = -5.0V 2.5 -VGS , GATE TO SOURCE VOLTAGE (V) -I S , REVERSE DRAIN CURRENT (A) R DS(ON) , NORMALIZED 0.05 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.6 DRAIN-SOURCE ON-RESISTANCE 0 -I D , DRAIN CURRENT (A) Figure 1. On-Region Characteristics. -ID , DRAIN CURRENT (A) -4.0V -4.5V 1 -V DS , DRAIN-SOURCE VOLTAGE (V) 0 -3.0V 1.5 0.5 4 -2.5V 4 VGS = 0V 0.1 TA = 125°C 25°C -55°C 0.01 0.001 0.0001 0.2 0.4 0.6 0.8 1 1.2 -VSD , BODY DIODE FORWARD VOLTAGE (V) Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDG6302P Rev.F Typical Electrical Characteristics 40 I D = -0.14A VDS = -5V 6 20 -10 CAPACITANCE (pF) -V GS , GATE-SOURCE VOLTAGE (V) 8 -15 4 2 0 Coss 5 3 1 0 0.1 0.2 0.3 0.4 Ciss 10 0.5 0.1 0.5 0.2 Figure 7. Gate Charge Characteristics. 1 2 5 10 20 Figure 8. Capacitance Characteristics. 1 50 RD S(O N) LI 10m s MIT 1s 0.1 10s DC VGS = -4.5V SINGLE PULSE RθJA = 415°C/W TA = 25°C 0.03 1 2 SINGLE PULSE R θJA=415°C/W TA= 25°C 40 10 0m s POWER (W) 0.3 30 20 10 3 5 10 20 0 0.0001 40 0.001 0.01 0.1 1 10 200 SINGLE PULSE TIME (SEC) - VDS , DRAIN-SOURCE VOLTAGE (V) Figure 9. Maximum Safe Operating Area. Figure 10. Single Pulse Maximum Power Dissipation. TRANSIENT THERMAL RESISTANCE 1 r(t), NORMALIZED EFFECTIVE -I D , DRAIN CURRENT (A) 0.5 -VDS , DRAIN TO SOURCE VOLTAGE (V) Q g , GATE CHARGE (nC) 0.005 Crss f = 1 MHz VGS = 0 V 0.5 D = 0.5 0.2 0.2 0.1 0.05 0.02 0.01 R θJA (t) = r(t) * R θJA R θJA =415 °C/W 0.1 P(pk) 0.05 t1 0.02 0.01 Single Pulse Duty Cycle, D = t 1/ t 2 0.005 0.002 0.0001 t2 TJ - TA = P * R θJA (t) 0.001 0.01 0.1 1 10 100 200 t 1, TIME (sec) Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in note 1. Transient thermalresponse will change depending on the circuit board design. FDG6302P Rev.F TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. HiSeC™ ISOPLANAR™ MICROWIRE™ POP™ PowerTrench  QFET™ QS™ Quiet Series™ SuperSOT™-3 SuperSOT™-6 ACEx™ Bottomless™ CoolFET™ CROSSVOLT™ E2CMOSTM FACT™ FACT Quiet Series™ FAST FASTr™ GTO™ SuperSOT™-8 SyncFET™ TinyLogic™ UHC™ VCX™ DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 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PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. E