FDG6304P

Digital FET, Dual P-Channel FDG6304P General Description These dual P−Channel logic level enhancement mode field effect transistors are produced using ON Semiconductor proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on−state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. www.onsemi.com S2 G2 D1 Features D2 G1 S1 • −25 V, −0.41 A Continuous, −1.5 A Peak RDS(ON) = 1.1 W @ VGS = −4.5 V RDS(ON) = 1.5 W @ VGS = −2.7 V Very Low Level Gate Drive Requirements Allowing Direct Operation in 3 V Circuits (VGS(th) < 1.5 V) Gate−Source Zener for ESD Ruggedness (>6 kV Human Body Model) Compact Industry Standard SC70−6 Surface Mount Package These Devices are Pb−Free and are RoHS Compliant ♦ • • • • SC−88/SC70−6/SOT−363 CASE 419B−02 ♦ ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted) Symbol FDG6304P Units VDSS Drain−Source Voltage Parameter −25 V VGSS Gate−Source Voltage −8 V ID Drain/Output Current Continuous −0.41 A Pulsed −1.5 PD Maximum Power Dissipation (Note 1) 0.3 W TJ, TSTG Operating and Storage Temperature Range −55 to +150 °C 6.0 kV ESD Electrostatic Discharge Rating MIL−STD−883D Human Body Model (100 pF / 1500 W) Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. MARKING DIAGRAM 04M 04 M = Specific Device Code = Assembly Operation Month PIN CONNECTIONS 1 or 4* 6 or 3 2 or 5 5 or 2 3 or 6 4 or 1* *The pinouts are symmetrical; pin 1 and 4 are interchangeable. Units inside the carrier can be of either orientation and will not affect the functionality of the device. ORDERING INFORMATION See detailed ordering and shipping information on page 5 of this data sheet. © Semiconductor Components Industries, LLC, 2000 July, 2021 − Rev. 7 1 Publication Order Number: FDG6304P/D FDG6304P THERMAL CHARACTERISTICS Symbol RqJA Parameter Ratings Unit 415 _C/W Thermal Resistance, Junction−to−Ambient (Note 1) 1. RqJA is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RqJC is guaranteed by design while RqCA is determined by the user’s board design. RqJA = 415°C/W on minimum pad mounting on FR−4 board in still air. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Symbol Parameter Conditions Min Typ Max Unit −25 − − V OFF CHARACTERISTICS BVDSS Drain−Source Breakdown Voltage VGS = 0 V, ID = −250 mA DBVDSS / DTJ Breakdown Voltage Temperature Coefficient ID = −250 mA, Referenced to 25_C − −22 − mV/_C IDSS Zero Gate Voltage Drain Current VDS = −20 V, VGS = 0 V − − −1 mA VDS = −20 V, VGS = 0 V, TJ = 55_C − − −10 mA VGS = −8 V, VDS = 0 V − − 100 nA −0.65 −0.82 −1.5 V IGSS Gate−Body Leakage Current ON CHARACTERISTICS (Note 2) VGS(th) Gate Threshold Voltage VDS = VGS, ID = −250 mA DVGS(th) / DTJ Gate Threshold Voltage Temperature Coefficient ID = −250 mA, Referenced to 25_C − 2 − mV/_C Static Drain−Source On−Resistance VGS = −4.5 V, ID = −0.41 A − 0.85 1.1 W VGS = −4.5 V, ID = −0.41 A, TJ = 125_C − 1.2 1.9 VGS = −2.7 V, ID = −0.25 A − 1.15 1.5 On−State Drain Current VGS = −4.5 V, VDS = −5 V −1.5 − − A Forward Transconductance VDS = −5 V, ID = −0.41 A − 0.9 − S VDS = 10 V, VGS = 0 V, f = 1.0 MHz − 62 − pF RDS(on) ID(on) gFS DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance − 34 − pF Crss Reverse Transfer Capacitance − 10 − pF − 7 15 ns − 8 16 ns SWITCHING CHARACTERISTICS (Note 2) VDD = −5 V, ID = −0.5 A, VGS = −4.5 V, RGEN = 6 W tD(on) Turn-On Delay Time tr Turn-On Rise Time tD(off) Turn-Off Delay Time − 55 80 ns tf Turn-Off Fall Time − 35 60 ns Qg Total Gate Charge − 1.1 1.5 nC Qgs Gate−Source Charge − 0.31 − nC Qgd Gate−Drain Charge − 0.29 − nC − − −0.25 A − −0.85 −1.2 V VDS = −5 V, ID = −0.41 A, VGS = −4.5 V DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS VSD Maximum Continuous Source Current Drain−Source Diode Forward Voltage VGS = 0 V, IS = −0.25 A (Note 2) Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2.0% www.onsemi.com 2 FDG6304P 1.2 VGS = −4.5 V −3.0 V −2.7 V 0.9 −2.5 V 0.6 −2.0 V 0.3 −1.5 V 0 0 1 2 3 4 −VDS , DRAIN−SOURCE VOLTAGE (V) RDS(ON) , NORMALIZED DRAIN−SOURCE ON−RESISTANCE −I D, DRAIN−SOURCE CURRENT (A) TYPICAL PERFORMANCE CHARACTERISTICS 1.6 ID = −0.41 A VGS = −4.5 V 1.4 1.2 1 0.8 0.6 −50 −25 0 25 50 75 100 −2.5 V 1.5 125 150 V DS = −5 V TJ = −55°C 0.8 0.5 0 0.2 25 °C 125°C 0.4 0.2 1 1.5 2 0.6 0.4 −3.5 V −4.5 V 0.8 1 1.2 −I D , DRAIN CURRENT (A) 5 ID = −0.2 A 4 3 2 TJ = 125°C 1 25°C 0 1 2 3 4 5 Figure 4. On−Resistance Variation with Gate−to−Source Voltage 0.6 0 0.5 −3.0 V −V GS, GATE TO SOURCE VOLTAGE (V) 2.5 3 −VGS , GATE TO SOURCE VOLTAGE (V) −I S , REVERSE DRAIN CURRENT (A) 1 −2.7 V 1 TJ , JUNCTION TEMPERATURE (°C) Figure 3. On−Resistance Variation with Temperature −ID, DRAIN CURRENT (A) V GS = −2.0 V 2 Figure 2. On−Resistance Variation with Drain Current and Gate Voltage RDS(ON), ON−RESISTANCE (W ) RDS(ON) , NORMALIZED DRAIN−SOURCE ON−RESISTANCE Figure 1. On−Region Characteristics 2.5 Figure 5. Transfer Characteristics 1 VGS = −5 V TJ = 125°C 0.1 25 °C −55°C 0.01 0.001 0.0001 0.2 0.4 0.6 0.8 1 1.2 −VSD , BODY DIODE FORWARD VOLTAGE (V) Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature www.onsemi.com 3 FDG6304P 5 I D = −0.41 A 200 VDS = −5 V CAPACITANCE (pF) −VGS , GATE−SOURCE VOLTAGE (V) TYPICAL PERFORMANCE CHARACTERISTICS (continued) −10 V 4 −15 V 3 2 1 0 0.4 0.8 1.2 C rss f = 1 MHz VGS = 0 V Qg , GATE CHARGE (nC) 0.3 2 1 5 1 ms 1 POWER (W) 10 ms 10 s VGS = −4.5 V SINGLE PULSE RqJA = 415°C/W TA = 25°C 0.01 0.1 0.2 SINGLE PULSE RqJA = 415°C/W TA = 25°C 40 100 ms 1s 0.1 DC 30 20 10 0.5 1 2 5 10 25 0 0.0001 40 0.001 −V DS , DRAIN−SOURCE VOLTAGE (V) 0.01 0.1 1 10 200 SINGLE PULSE TIME (sec) Figure 10. Single Pulse Maximum Power Dissipation Figure 9. Maximum Safe Operating Area r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 25 Figure 8. Capacitance Characteristics 50 0.5 RDS(ON) LIMIT 10 −V DS , DRAIN TO SOURCE VOLTAGE (V) 3 0.05 C oss 10 3 0.1 1.6 C iss 30 5 0 Figure 7. Gate Charge Characteristics −I D, DRAIN CURRENT (A) 80 1 0.5 D = 0.5 0.2 0.2 0.1 0.05 0.02 0.01 RqJA (t) = r(t) * RqJA RqJA = 415°C/W 0.1 0.05 P(pk) 0.02 0.01 Single Pulse t1 0.005 0.002 0.0001 t2 TJ − TA = P * RqJA (t) Duty Cycle, D = t1 / t2 0.001 0.01 0.1 1 10 t 1, TIME (sec) Thermal characterization performed using the conditions described in Note 1. Transient thermal response will change depending on the circuit board design. Figure 11. Transient Thermal Response Curve www.onsemi.com 4 100 200 FDG6304P ORDERING INFORMATION Device Order Number Device Marking Package Type Shipping† FDG6304P 04 SC−88/SC70−6/SOT−363 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. www.onsemi.com 5 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE Y 1 SCALE 2:1 DATE 11 DEC 2012 2X aaa H D D H A D 6 5 GAGE PLANE 4 1 2 L L2 E1 E DETAIL A 3 aaa C 2X bbb H D 2X 3 TIPS e B 6X b ddd TOP VIEW C A-B D M A2 DETAIL A A 6X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH, PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRUSIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END. 4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY AND DATUM H. 5. DATUMS A AND B ARE DETERMINED AT DATUM H. 6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP. 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDITION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OF THE FOOT. ccc C A1 SIDE VIEW C SEATING PLANE END VIEW c RECOMMENDED SOLDERING FOOTPRINT* 6X DIM A A1 A2 b C D E E1 e L L2 aaa bbb ccc ddd MILLIMETERS MIN NOM MAX −−− −−− 1.10 0.00 −−− 0.10 0.70 0.90 1.00 0.15 0.20 0.25 0.08 0.15 0.22 1.80 2.00 2.20 2.00 2.10 2.20 1.15 1.25 1.35 0.65 BSC 0.26 0.36 0.46 0.15 BSC 0.15 0.30 0.10 0.10 GENERIC MARKING DIAGRAM* 6 XXXMG G 6X 0.30 INCHES NOM MAX −−− 0.043 −−− 0.004 0.035 0.039 0.008 0.010 0.006 0.009 0.078 0.086 0.082 0.086 0.049 0.053 0.026 BSC 0.010 0.014 0.018 0.006 BSC 0.006 0.012 0.004 0.004 MIN −−− 0.000 0.027 0.006 0.003 0.070 0.078 0.045 0.66 1 2.50 0.65 PITCH XXX = Specific Device Code M = Date Code* G = Pb−Free Package (Note: Microdot may be in either location) DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. *Date Code orientation and/or position may vary depending upon manufacturing location. *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. STYLES ON PAGE 2 DOCUMENT NUMBER: DESCRIPTION: 98ASB42985B SC−88/SC70−6/SOT−363 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com SC−88/SC70−6/SOT−363 CASE 419B−02 ISSUE Y DATE 11 DEC 2012 STYLE 1: PIN 1. EMITTER 2 2. BASE 2 3. COLLECTOR 1 4. EMITTER 1 5. BASE 1 6. COLLECTOR 2 STYLE 2: CANCELLED STYLE 3: CANCELLED STYLE 4: PIN 1. CATHODE 2. CATHODE 3. COLLECTOR 4. EMITTER 5. BASE 6. ANODE STYLE 5: PIN 1. ANODE 2. ANODE 3. COLLECTOR 4. EMITTER 5. BASE 6. CATHODE STYLE 6: PIN 1. ANODE 2 2. N/C 3. CATHODE 1 4. ANODE 1 5. N/C 6. CATHODE 2 STYLE 7: PIN 1. SOURCE 2 2. DRAIN 2 3. GATE 1 4. SOURCE 1 5. DRAIN 1 6. GATE 2 STYLE 8: CANCELLED STYLE 9: PIN 1. EMITTER 2 2. EMITTER 1 3. COLLECTOR 1 4. BASE 1 5. BASE 2 6. COLLECTOR 2 STYLE 10: PIN 1. SOURCE 2 2. SOURCE 1 3. GATE 1 4. DRAIN 1 5. DRAIN 2 6. GATE 2 STYLE 11: PIN 1. CATHODE 2 2. CATHODE 2 3. ANODE 1 4. CATHODE 1 5. CATHODE 1 6. ANODE 2 STYLE 12: PIN 1. ANODE 2 2. ANODE 2 3. CATHODE 1 4. ANODE 1 5. ANODE 1 6. CATHODE 2 STYLE 13: PIN 1. ANODE 2. N/C 3. COLLECTOR 4. EMITTER 5. BASE 6. CATHODE STYLE 14: PIN 1. VREF 2. GND 3. GND 4. IOUT 5. VEN 6. VCC STYLE 15: PIN 1. ANODE 1 2. ANODE 2 3. ANODE 3 4. CATHODE 3 5. CATHODE 2 6. CATHODE 1 STYLE 16: PIN 1. BASE 1 2. EMITTER 2 3. COLLECTOR 2 4. BASE 2 5. EMITTER 1 6. COLLECTOR 1 STYLE 17: PIN 1. BASE 1 2. EMITTER 1 3. COLLECTOR 2 4. BASE 2 5. EMITTER 2 6. COLLECTOR 1 STYLE 18: PIN 1. VIN1 2. VCC 3. VOUT2 4. VIN2 5. GND 6. VOUT1 STYLE 19: PIN 1. I OUT 2. GND 3. GND 4. V CC 5. V EN 6. V REF STYLE 20: PIN 1. COLLECTOR 2. COLLECTOR 3. BASE 4. EMITTER 5. COLLECTOR 6. COLLECTOR STYLE 21: PIN 1. ANODE 1 2. N/C 3. ANODE 2 4. CATHODE 2 5. N/C 6. CATHODE 1 STYLE 22: PIN 1. D1 (i) 2. GND 3. D2 (i) 4. D2 (c) 5. VBUS 6. D1 (c) STYLE 23: PIN 1. Vn 2. CH1 3. Vp 4. N/C 5. CH2 6. N/C STYLE 24: PIN 1. CATHODE 2. ANODE 3. CATHODE 4. CATHODE 5. CATHODE 6. CATHODE STYLE 25: PIN 1. BASE 1 2. CATHODE 3. COLLECTOR 2 4. BASE 2 5. EMITTER 6. COLLECTOR 1 STYLE 26: PIN 1. SOURCE 1 2. GATE 1 3. DRAIN 2 4. SOURCE 2 5. GATE 2 6. DRAIN 1 STYLE 27: PIN 1. BASE 2 2. BASE 1 3. COLLECTOR 1 4. EMITTER 1 5. EMITTER 2 6. COLLECTOR 2 STYLE 28: PIN 1. DRAIN 2. DRAIN 3. GATE 4. SOURCE 5. DRAIN 6. DRAIN STYLE 29: PIN 1. ANODE 2. ANODE 3. COLLECTOR 4. EMITTER 5. BASE/ANODE 6. CATHODE STYLE 30: PIN 1. SOURCE 1 2. DRAIN 2 3. DRAIN 2 4. SOURCE 2 5. GATE 1 6. DRAIN 1 Note: Please refer to datasheet for style callout. If style type is not called out in the datasheet refer to the device datasheet pinout or pin assignment. DOCUMENT NUMBER: DESCRIPTION: 98ASB42985B SC−88/SC70−6/SOT−363 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. 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