April 2002
FDG6313N
Dual N-Channel, Digital FET
General Description
Features
25 V, 0.50 A continuous, 1.5 A peak.
RDS(ON) = 0.45 Ω @ VGS= 4.5 V,
RDS(ON) =0.60 Ω @ VGS= 2.7 V.
These dual N-Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. This device has been
designed especially for low voltage applications as a
replacement for bipolar digital transistors and small
signal MOSFETs.
Very low level gate drive requirements allowing direct
operation in 3 V circuits (VGS(th) < 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
Compact industry standard SC70-6 surface
mount package.
SC70-6
SuperSOTTM -6
SOT-23
G2
D1
SuperSOTTM -8
S2
SO-8
SOT-223
1 or 4 *
6 or 3
2 or 5
5 or 2
3 or 6
4 or 1
.33
S1
SC70-6
G1
D2
*
* The pinouts are symmetrical; pin 1 and 4 are interchangeable.
Units inside the carrier can be of either orientation and will not affect the functionality of the device.
Absolute Maximum Ratings
TA = 25°C unless otherwise noted
Symbol
Parameter
VDSS
Drain-Source Voltage
VGSS
Gate-Source Voltage
ID
Drain/Output Current
PD
Maximum Power Dissipation
TJ,TSTG
Operating and Storage Temperature Range
ESD
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100 pF / 1500 Ω)
FDG6313N
Units
25
V
- 0.5 to +8
- Continuous
0.5
- Pulsed
V
A
1.5
(Note 1)
0.3
W
-55 to 150
°C
6.0
kV
415
°C/W
THERMAL CHARACTERISTICS
RθJA
Thermal Resistance, Junction-to-Ambient
FDG6313N Rev.A
Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol
Parameter
Conditions
Min
25
Typ
Max
Units
OFF CHARACTERISTICS
BVDSS
Drain-Source Breakdown Voltage
VGS = 0 V, ID = 250 µA
∆BVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
ID = 250 µA, Referenced to 25oC
IDSS
Zero Gate Voltage Drain Current
VDS = 20 V, VGS = 0 V
V
TJ = 55°C
IGSS
Gate - Body Leakage Current
mV/oC
26
VGS = 8 V, VDS = 0 V
1
µA
10
µA
100
nA
ON CHARACTERISTICS (Note 2)
VGS(th)
Gate Threshold Voltage
VDS = VGS, ID = 250 µA
∆VGS(th)/∆TJ
Gate Threshold Voltage Temp.Coefficient
ID = 250 µA, Referenced to 25oC
0.65
-2.6
RDS(ON)
Static Drain-Source On-Resistance
VGS = 4.5 V, ID = 0.5 A
0.34
0.45
0.55
0.77
0.44
0.6
TJ =125°C
VGS = 2.7 V, ID = 0.2 A
ID(ON)
On-State Drain Current
VGS = 2.7 V, VDS = 5 V
gFS
Forward Transconductance
VDS = 5 V, ID = 0.5 A
0.8
1.5
V
mV/oC
0.5
Ω
A
1.45
S
50
pF
DYNAMIC CHARACTERISTICS
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
28
pF
9
pF
SWITCHING CHARACTERISTICS (Note 2)
tD(on)
Turn - On Delay Time
tr
Turn - On Rise Time
tD(off)
Turn - Off Delay Time
tf
Turn - Off Fall Time
Qg
Total Gate Charge
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
VDD = 5 V, ID = 0.5 A,
VGS = 4.5 V, RGEN = 50 Ω
VDS = 5 V, ID = 0.5 A,
VGS = 4.5 V
3
6
ns
8.5
18
ns
17
30
ns
13
25
ns
1.64
2.3
nC
0.38
nC
0.45
nC
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
IS
Maximum Continuous Source Current
VSD
Drain-Source Diode Forward Voltage
VGS = 0 V, IS = 0.25 A
(Note 2)
0.8
0.25
A
1.2
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed
by design while RθCA is determined by the user's board design. RθJA = 415OC/W on minimum pad mounting on FR-4 board in still air.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDG6313N Rev. A
Typical Electrical Characteristics
2
VGS = 4.5V
2.5V
3.0V
2.7V
2.0V
, NORMALIZED
1.2
0.9
0.6
R DSO
(N)
1.5V
0.3
DRAIN-SOURCE ON-RESISTANCE
I D , DRAIN-SOURCE CURRENT (A)
1.5
VGS = 2.0V
1.5
2.5V
2.7V
3.5V
4.5V
1
0.5
0
0
0.5
1
1.5
2
2.5
0
3
0.2
0.4
R DS(on), ON-RESISTANCE (OHM)
I D = 0.5A
VGS = 4.5 V
1.2
1
0.8
1.2
0.6
-50
I D = 0.3A
1.6
1.2
-25
0
25
50
75
100
125
150
TA = 125°C
0.8
0.4
TA = 25°C
0
1
1.5
2
2.5
3
3.5
4
4.5
5
V GS , GATE TO SOURCE VOLTAGE (V)
TJ , JUNCTION TEMPERATURE (°C)
Figure 3. On-Resistance Variation
with Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
1
1
TJ = -55°C
VDS = 5.0V
0.8
I S , REVERSE DRAIN CURRENT (A)
R DS(ON) , NORMALIZED
1
2
1.6
DRAIN-SOURCE ON-RESISTANCE
0.8
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
Figure 1. On-Region Characteristics.
1.4
0.6
ID , DRAIN CURRENT (A)
VDS , DRAIN-SOURCE VOLTAGE (V)
I D, DRAIN CURRENT (A)
3.0V
25°C
125°C
0.6
0.4
0.2
VGS = 0V
TJ = 125°C
0.1
25°C
-55°C
0.01
0.001
0.0001
0
0
0.5
1
1.5
2
VGS , GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics.
2.5
0
0.2
0.4
0.6
0.8
1
1.2
V SD , BODY DIODE FORWARD VOLTAGE (V)
Figure 6 . Body Diode Forward Voltage
Variation with Source Current
and Temperature.
FDG6313N Rev. A
Typical Electrical Characteristics (continued)
200
I D = 0.5A
VDS = 5V
10V
15V
4
CAPACITANCE (pF)
V GS , GATE-SOURCE VOLTAGE (V)
5
3
2
70
Ciss
30
Coss
10
3
0.1
0
0
0.4
0.8
1.2
1.6
2
0.3
1
2
5
10
25
V DS , DRAIN TO SOURCE VOLTAGE (V)
Q g , GATE CHARGE (nC)
Figure 8. Capacitance Characteristics.
Figure 7. Gate Charge Characteristics.
3
50
1m
s
10m
s
IT
IM
)L
N
(O
S
0.5
RD
10
0m
s
1s
0.2
10
s
DC
0.1
VGS = 4.5V
SINGLE PULSE
RθJA = 415 °C/W
TA = 25°C
0.05
0.02
0.01
0.1
DS
30
20
10
1
V
SINGLE PULSE
R θJA=415°C/W
TA= 25°C
40
POWER (W)
1
2
5
10
25
0
0.0001
40
0.001
0.01
0.1
1
10
200
SINGLE PULSE TIME (SEC)
, DRAI N-SOURCE VOLTAGE (V)
Figure 10. Single Pulse Maximum Power
Dissipation.
Figure 9. Maximum Safe Operating Area.
TRANSIENT THERMAL RESISTANCE
1
r(t), NORMALIZED EFFECTIVE
ID , DRAIN CURRENT (A)
Crss
f = 1 MHz
VGS = 0V
1
0.5
D = 0.5
0.2
0.2
0.1
0.05
0.02
0.01
R θJA (t) = r(t) * R θJA
R θJA =415 °C/W
0.1
P(pk)
0.05
t1
0.02
0.01
t2
TJ - TA = P * R θJA (t)
Single Pulse
Duty Cycle, D = t 1/ t 2
0.005
0.002
0.0001
0.001
0.01
0.1
1
10
100
200
t 1, TIME (sec)
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in note 1.
Transient thermal response will change depending on the circuit board design.
FDG6313N Rev. A
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY
PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY
ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT
CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
2. A critical component is any component of a life
1. Life support devices or systems are devices or
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I11
