FDMC8010

FDMC8010 MOSFET – N-Channel, POWERTRENCH) 30 V, 75 A, 1.3 mW General Description www.onsemi.com This N−Channel MOSFET is produced using ON Semiconductor’s advanced POWERTRENCH process that has been especially tailored to minimize the on−state resistance. This device is well suited for applications where ultra low rDS(on) is required in small spaces such as High performance VRM, POL and Oring functions. D Features • • • • D Top Max rDS(on) = 1.3 mW at VGS = 10 V, ID = 30 A Max rDS(on) = 1.8 mW at VGS = 4.5 V, ID = 25 A High Performance Technology for Extremely Low rDS(on) These Devices are Pb−Free and are RoHS Compliant D SS S G D Bottom PQFN8 3.3x3.3, 0.65P CASE 483AW Power 33 Applications • • • • Pin 1 Pin 1 MARKING DIAGRAM DC − DC Buck Converters Point of Load High Efficiency Load Switch and Low Side Switching Oring FET $Y&Z&3&K FDMC 8010 MOSFET MAXIMUM RATINGS (TA = 25°C Unless Otherwise Noted) Symbol Parameter Ratings Units VDS Drain to Source Voltage 30 V VGS Gate to Source Volage (Note 4) ±20 V Drain Current −Continuous (Package limited) TC = 25°C −Continuous (Silicon limited) TC = 25°C −Continuous TA = 25°C (Note 1a) −Pulsed 75 166 30 120 EAS Single Pulse Avalance Energy (Note 3) 153 mJ PD Power Dissipation TC = 25°C 54 W Power Dissipation TA = 25°C (Note 1a) 2.4 ID TJ, TSTG Operating and Storage Junction Temperature Range A −55 to +150 °C Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. $Y &Z &3 &K FDMC8010 = ON Semiconductor Logo = Assembly Plant Code = Numeric Date Code = Lot Code = Specific Device Code S D S D S D G D THERMAL CHARACTERISTICS Symbol Parameter Ratings Unit RθJC Thermal Resistance, Junction to Case 1.3 °C/W RθJA Thermal Resistance, Junction to Ambient (Note 1a) 53 °C/W © Semiconductor Components Industries, LLC, 2017 July, 2019 − Rev. 2 1 ORDERING INFORMATION See detailed ordering, marking and shipping information in the package dimensions section on page 2 of this data sheet. Publication Order Number: FDMC8010/D FDMC8010 PACKAGE MARKING AND ORDERING INFORMATION Device Marking Device Package Reel Size Tape Width Quantity FDMC8010 FDMC8010 Power 33 13” 12 mm 3000 Units ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted) Parameter Symbol Test Condition Min Typ Max Unit OFF CHARACTERISTICS BVDSS Drain to Source Breakdown Voltage ID = 1 mA, VGS = 0 V 30 DBVDSS/DTJ Breakdown Voltage Temperature Coef- ID = 1 mA, referenced to 25°C ficient V 15 mV/°C IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V 1 mA IGSS Gate to Source Leakage Current VGS = 20 V, VDS = 0 V 100 nA 2.5 V ON CHARACTERISTICS VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 1 mA 1.2 DVGS(th)/DTJ Gate to Source Threshold Voltage Tem- ID = 1 mA, referenced to 25°C perature Coefficient rDS(on) gFS Static Drain to Source On Resistance 1.5 −5 mV/°C mW VGS = 10 V, ID = 30 A 0.9 1.3 VGS = 4.5 V, ID = 25 A 1.3 1.8 VGS = 10 V, ID = 30 A, TJ = 125°C 1.3 2 VDS = 5 V, ID = 30 A 188 VDS = 15 V, VGS = 0 V, f = 1 MHz 4405 5860 pF 1570 2090 pF 167 250 pF 0.5 1.25 W 15 27 ns 7.5 15 ns Turn−Off Delay Time 40 64 ns Fall Time 5.3 11 ns 67 94 nC 32 45 nC Forward Transconductance S DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance 0.1 SWITCHING CHARACTERISTICS td(on) tr td(off) tf Turn−On Delay Time Rise Time VDD = 15 V, ID = 30 A, VGS = 10 V, RGEN = 6 W VDD = 15 V ID = 30 A Qg Total Gate Charge VGS = 0 V to 10 V Qg Total Gate Charge VGS = 0 V to 4.5 V Qgs Gate to Source Charge 10 nC Qgd Gate to Drain “Miller” Charge 9.5 nC DRAIN−SOURCE DIODE CHARACTERISTICS VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 2 A (Note 2) 0.6 1.2 VGS = 0 V, IS = 30 A (Note 2) 0.7 1.2 IF = 30 A, di/dt = 100 A/ms 49 78 ns 29 46 nC trr Reverse Recovery Time Qrr Reverse Recovery Charge www.onsemi.com 2 V FDMC8010 NOTES: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. RθJC is guaranteed by design while RθCA is determined by the user’s board design. a. 53 °C/W when mounted on a 1 in2 pad of 2 oz copper. b. 125 °C/W when mounted on a minimum pad of 2 oz copper. SS SF DS DF G SS SF DS DF G 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %. 3. EAS of 153 mJ is based on starting TJ = 25 °C, L = 0.3 mH, IAS = 32 A, VDD = 27 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 47 A. 4. As an N−ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied. www.onsemi.com 3 FDMC8010 TYPICAL CHARACTERISTICS TJ = 25°C Unless Otherwise Noted 5 VGS = 10 V NORMALIZED DRAIN TO SOURCE ON−RESISTANCE ID, DRAIN CURRENT (A) 120 VGS = 4.5 V VGS = 4 V 80 VGS = 3.5 V 40 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX VGS = 3 V 0 0.0 0.2 0.4 4 3 2 1 0 0.6 0 40 5 rDS(ON), DRAIN−TO−SOURCE ON−RESISTANCE (mW) NORMALIZED DRAIN TO SOURCE ON−RESISTANCE 1.0 0.8 25 50 PULSE DURATION = 80 m s DUTY CYCLE = 0.5% MAX 4 ID = 30 A 3 TJ = 125°C 2 1 0 75 100 125 150 TJ = 25°C 2 4 TJ, JUNCTION TEMPERATURE (°C) IS, REVERSE DRAIN CURRENT (A) ID, DRAIN CURRENT (A) PULSE DURATION = 80 m s DUTY CYCLE = 0.5% MAX VDS = 5 V TJ = 150°C TJ = 25°C 40 TJ = −55°C 1.5 2.0 8 10 Figure 4. On−Resistance vs Gate to Source Voltage 120 0 1.0 6 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On Resistance vs Junction Temperature 80 120 Figure 2. Noormalized On−Resistance vs Drain Current and Gate Voltage 1.2 0 80 ID, DRAIN CURRENT (A) ID = 30 A VGS = 10 V 0.6 −75 −50 −25 VGS = 10 V VGS = 4.5 V Figure 1. On−Region Characteristics 1.4 VGS = 4 V VGS = 3.5 V VDS, DRAIN−TO−SOURCE VOLTAGE (V) 1.6 PULSE DURATION = 80ms DUTY CYCLE = 0.5% MAX VGS = 3 V 2.5 3.0 200 100 VGS = 0 V 10 TJ = 150°C 1 TJ = 25°C 0.1 TJ = −55°C 0.01 0.001 0.0 VGS, GATE TO SOURCE VOLTAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current www.onsemi.com 4 FDMC8010 TYPICAL CHARACTERISTICS (continued) TJ = 25°C Unless Otherwise Noted 10 10000 CAPACITANCE (pF) VDD = 15 V 6 VDD = 18 V 4 2 0 IAS, AVALANCHE CURRENT (A) Ciss VDD = 12 V 8 0 20 40 60 Coss 1000 Crss f = 1 MHz VGS = 0 V 100 0.1 80 1 Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 200 TJ = 25°C TJ = 100°C 10 TJ = 125°C 1 0.001 0.01 0.1 1 10 RqJA = 2.3°C/W VGS = 10 V 150 100 VGS = 4.5 V 50 Limited by Package 0 25 100 500 50 tAV, TIME IN AVALANCHE (ms) 100 ms 10 1 ms THIS AREA IS LIMITED BY r DS(on) 10 ms 100 ms SINGLE PULSE TJ = MAX RATED RqJA = 125°C/W TA = 25°C 0.01 0.01 0.1 1s 10 s DC 1 10 100 125 150 Figure 10. Maximum Continuous Drain Current vs Case Temperature P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 200 100 75 TC, CASE TEMPERATURE (°C) Figure 9. Unclamped Inductive Switching Capability 0.1 30 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 1 10 Qg, GATE CHARGE (nC) ID, DRAIN CURRENT (A) VGS, GATE TO SOURCE VOLTAGE (V) ID = 30 A 100200 3000 SINGLE PULSE RqJA = 125°C/W TA = 25°C 1000 100 10 1 0.5 −4 10 VDS, DRAIN TO SOURCE VOLTAGE (V) −3 10 −2 10 −1 10 1 10 100 1000 t, PULSE WIDTH (sec) Figure 11. Forward Bias Safe Operating Area Figure 12. Single Pulse Maximum Power Dissipation www.onsemi.com 5 FDMC8010 TYPICAL CHARACTERISTICS (continued) TJ = 25°C Unless Otherwise Noted NORMALIZED THERMAL IMPEDANCE, ZqJA 2 1 0.1 0.01 DUTY CYCLE−DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.001 NOTES: DUTY FACTOR: D = t 1/t 2 PEAK T J = PDM x Z qJA x R qJA + TA SINGLE PULSE RqJA = 125°C/W 0.0001 −4 10 −3 10 −2 10 −1 10 11 0 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction−to−Ambient Transient Thermal Response Curve POWERTRENCH are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 6 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS WDFN8 3.3X3.3, 0.65P CASE 483AW ISSUE A GENERIC MARKING DIAGRAM* XXXX A Y WW XXXX AYWW DOCUMENT NUMBER: DESCRIPTION: = Specific Device Code = Assembly Location = Year = Work Week 98AON13672G WDFN8 3.3X3.3, 0.65P DATE 10 SEP 2019 *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “G”, may or may not be present. Some products may not follow the Generic Marking. Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 1 OF 1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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