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FDMC8097AC
Dual N & P-Channel PowerTrench® MOSFET
N-Channel: 150 V, 2.4 A, 155 mΩ P-Channel: -150 V, -0.9 A, 1200 mΩ
Features
General Description
Q1: N-Channel
These dual N and P-Channel enhancement mode Power
MOSFETs are produced using Fairchild Semiconductor’s
advanced PowerTrench® process that has been especially
tailored to minimize on-state resistance and yet maintain
superior switching performance. Shrinking the area needed for
implementation of active clamp topology; enabling best in class
power density.
Max rDS(on) = 155 mΩ at VGS = 10 V, ID = 2.4 A
Max rDS(on) = 212 mΩ at VGS = 6 V, ID = 2 A
Q2: P-Channel
Max rDS(on) = 1200 mΩ at VGS = -10 V, ID = -0.9 A
Max rDS(on) = 1400 mΩ at VGS = -6 V, ID = -0.8 A
Applications
Optimised for active clamp forward converters
DC-DC Converter
RoHS Compliant
Active Clamp
Top
Bottom
Pin 1
G1 S1 S1 S1
D1
D2
G2 S2 S2 S2
G1
G2
S1
S2
S1
S2
S1
S2
Power 33
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.
Symbol
VDS
Drain to Source Voltage
Parameter
VGS
Gate to Source Voltage
Drain Current -Continuous
ID
Q1
150
TC = 25 °C
(Note 5)
-Continuous
TC = 100 °C
(Note 5)
-Continuous
TA = 25 °C
-Pulsed
Single Pulse Avalanche Energy
EAS
PD
TJ, TSTG
Q2
-150
Units
V
±20
±25
V
6.3
-2.0
3.9
-1.2
2.4 1a
-0.9 1b
(Note 4)
33
-8.8
(Note 3)
24
6
1.9 1a
1.9 1b
mJ
Power Dissipation for Single Operation
TA = 25 °C
Power Dissipation for Single Operation
TA = 25 °C
0.8 1c
0.8 1d
Power Dissipation for Single Operation
TC = 25 °C
14
10
Operating and Storage Junction Temperature Range
A
-55 to +150
W
°C
Thermal Characteristics
RθJA
65 1a
Thermal Resistance, Junction-to-Ambient
RθJA
Thermal Resistance, Junction-to-Ambient
RθJC
Thermal Resistance, Junction-to-Case
155
1c
8.9
65 1b
155 1d
°C/W
12.5
Package Marking and Ordering Information
Device Marking
FDMC8097AC
Device
FDMC8097AC
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
Package
Power 33
1
Reel Size
13 ”
Tape Width
12 mm
Quantity
3000 units
www.fairchildsemi.com
FDMC8097AC Dual N & P-Channel PowerTrench® MOSFET
August 2015
Symbol
Parameter
Test Conditions
Type
Min.
150
-150
Typ.
Max.
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
ID = -250 μA, VGS = 0 V
Q1
Q2
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
ID = -250 μA, referenced to 25 °C
Q1
Q2
IDSS
Zero Gate Voltage Drain Current
VDS = 120 V, VGS = 0 V
VDS = -120 V, VGS = 0 V
Q1
Q2
1
-1
μA
IGSS
Gate to Source Leakage Current
VGS = ±20 V, VDS = 0 V
VGS = ±25 V, VDS = 0 V
Q1
Q2
±100
±100
nA
nA
4.0
-4.0
V
V
98
122
mV/°C
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
VGS = VDS, ID = -250 μA
Q1
Q2
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
ID = -250 μA, referenced to 25 °C
Q1
Q2
-9
-6
VGS = 10 V, ID = 2.4 A
VGS = 6 V, ID = 2 A
VGS = 10 V, ID = 2.4 A, TJ = 125 °C
Q1
124
155
245
155
212
306
VGS = -10 V, ID = -0.9 A
VGS = -6 V, ID = -0.8 A
VGS = -10 V, ID = -0.9 A, TJ = 125 °C
Q2
930
1030
1682
1200
1400
2171
VDD = 10 V, ID = 2.4 A
VDD = -10 V, ID = -0.9 A
Q1
Q2
6.4
0.75
Q1
VDS = 75 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
279
162
395
230
pF
Q1
Q2
26
13
40
25
pF
Q1
Q2
1.4
0.6
5
5
pF
0.6
3.3
1.5
8.3
Ω
Q1
Q2
5.4
5.2
11
11
ns
Q1
Q2
1.3
1.6
10
10
ns
Q2
VDD = -75 V, ID = -0.9 A,
VGS = -10 V, RGEN = 6 Ω
Q1
Q2
9.1
7.4
18
15
ns
Q1
Q2
2.2
6.3
10
13
ns
VGS = 0 V to 10 V
Q1
VGS = 0 V to -10 V
VDD = 75 V,
VGS = 0 V to 6 V
ID = 2.4 A
VGS = 0 V to -6 V
Q1
Q2
4.4
2.8
6.2
4.0
nC
Q1
Q2
2.9
1.8
4.1
2.6
nC
Q1
Q2
1.3
0.8
nC
Q1
Q2
1.0
0.7
nC
rDS(on)
gFS
Static Drain to Source On Resistance
Forward Transconductance
2.0
-2.0
3.1
-3.0
mV/°C
mΩ
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Rg
Gate Resistance
Q2
VDS = -75 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
0.1
0.1
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Rise Time
td(off)
Turn-Off Delay Time
tf
Fall Time
Qg(TOT)
Total Gate Charge
Qg(TOT)
Total Gate Charge
Qgs
Gate to Source Charge
Qgd
Gate to Drain “Miller” Charge
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
Q1
VDD = 75 V, ID = 2.4 A,
VGS = 10 V, RGEN = 6 Ω
Q2
VDD = -75 V
ID = -0.9 A
2
www.fairchildsemi.com
FDMC8097AC Dual N & P-Channel PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted.
Symbol
Parameter
Test Conditions
Type
Min.
Typ.
Max.
Units
Q1
Q2
0.8
-0.9
1.3
-1.3
V
Q1
Q2
50
44
80
71
ns
Q1
Q2
43
68
69
109
nC
Drain-Source Diode Characteristics
VSD
Source-Drain Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = 2.4 A
VGS = 0 V, IS = -0.9 A
Q1
IF = 2.4 A, di/dt = 100 A/s
Q2
IF = -0.9 A, di/dt = 100 A/s
(Note 2)
(Note 2)
Notes:
1. RθJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined
by the user's board design.
b. 65 °C/W when mounted on
a 1 in2 pad of 2 oz copper
a. 65 °C/W when mounted on
a 1 in2 pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
d. 155 °C/W when mounted on a
minimum pad of 2 oz copper
c. 155 °C/W when mounted on a
minimum pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. Q1: EAS of 24 mJ is based on starting TJ = 25 oC, L = 3 mH, IAS = 4 A, VDD = 150 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 14 A.
Q2: EAS of 6 mJ is based on starting TJ = 25 oC, L = 3 mH, IAS = -2 A, VDD = -150 V, VGS = -10 V. 100% test at L = 0.1 mH, IAS = -8 A.
4. Q1: Pulsed Id please refer to Fig 11 SOA graph for more details.
Q2: Pulsed Id please refer to Fig 24 SOA graph for more details.
5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design.
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
3
www.fairchildsemi.com
FDMC8097AC Dual N & P-Channel PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted.
VGS = 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRAIN CURRENT (A)
10
VGS = 6 V
8
VGS = 5.5 V
6
4
VGS = 5 V
2
0
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 4.5 V
0
1
2
3
4
5
4
VGS = 4.5 V
3
VGS = 5 V
VGS = 5.5 V
2
VGS = 6 V
1
0
0
2
VDS, DRAIN TO SOURCE VOLTAGE (V)
rDS(on), DRAIN TO
2.0
1.5
1.0
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
500
ID = 2.4 A
VGS = 10 V
-50
IS, REVERSE DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
6
TJ = 150 oC
TJ = 25 oC
TJ = -55 oC
0
2
3
4
5
6
200
TJ = 25 oC
100
4
5
20
10
6
7
8
9
10
VGS = 0 V
1
TJ = 150 oC
TJ = 25 oC
0.1
0.01
TJ = -55 oC
0.001
0.0
7
VGS, GATE TO SOURCE VOLTAGE (V)
0.2
0.4
0.6
0.8
1.0
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
TJ = 125 oC
300
Figure 4. On-Resistance vs. Gate to
Source Voltage
VDS = 5 V
2
10
VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
4
8
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
ID = 2.4 A
400
0
-25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
Figure 3. Normalized On Resistance
vs. Junction Temperature
8
6
Figure 2. Normalized On-Resistance
vs. Drain Current and Gate Voltage
2.5
10
4
ID, DRAIN CURRENT (A)
Figure 1. On Region Characteristics
0.5
-75
VGS = 10 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
Figure 6. Source to Drain Diode
Forward Voltage vs. Source Current
4
www.fairchildsemi.com
FDMC8097AC Dual N & P-Channel PowerTrench® MOSFET
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted.
1000
ID = 2.4 A
Ciss
VDD = 50 V
8
VDD = 75 V
6
CAPACITANCE (pF)
VGS, GATE TO SOURCE VOLTAGE (V)
10
VDD = 100 V
4
100
Coss
10
Crss
2
f = 1 MHz
VGS = 0 V
0
0
1
2
3
4
1
0.1
5
1
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance vs. Drain
to Source Voltage
20
8
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
o
RθJC = 8.9 C/W
10
TJ = 25 oC
TJ = 100 oC
TJ = 125 oC
1
0.001
0.01
0.1
1
6
VGS = 10 V
4
2
0
25
10
VGS = 6 V
50
P(PK), PEAK TRANSIENT POWER (W)
ID, DRAIN CURRENT (A)
150
10000
10 μs
10
100 μs
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJC = 8.9 oC/W
0.01
0.1
125
Figure 10. Maximum Continuous Drain
Current vs. Case Temperature
100
0.1
100
TC, CASE TEMPERATURE ( C)
Figure 9. Unclamped Inductive
Switching Capability
1
75
o
tAV, TIME IN AVALANCHE (ms)
TC = 25 oC
1 ms
CURVE BENT TO
MEASURED DATA
1
10
10 ms
DC
100
1000
VDS, DRAIN to SOURCE VOLTAGE (V)
TC = 25 oC
1000
100
10 -5
10
-4
10
-3
10
-2
10
-1
10
1
t, PULSE WIDTH (sec)
Figure 11. Forward Bias Safe
Operating Area
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
SINGLE PULSE
RθJC = 8.9 oC/W
Figure 12. Single Pulse Maximum Power
Dissipation
5
www.fairchildsemi.com
FDMC8097AC Dual N & P-Channel PowerTrench® MOSFET
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted.
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
2
DUTY CYCLE-DESCENDING ORDER
1
0.1
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
t2
NOTES:
0.01
ZθJC(t) = r(t) x RθJC
RθJC = 8.9 oC/W
Peak TJ = PDM x ZθJC(t) + TC
Duty Cycle, D = t1 / t2
SINGLE PULSE
0.001
-5
10
-4
10
-3
-2
10
10
-1
10
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Case Transient Thermal Response Curve
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
6
www.fairchildsemi.com
FDMC8097AC Dual N & P-Channel PowerTrench® MOSFET
Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted.
4
1.8
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
-ID, DRAIN CURRENT (A)
VGS = -10 V
VGS = -7 V
3
VGS = -6 V
VGS = -5.5 V
2
VGS = -5 V
1
0
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
1
2
3
4
-VDS, DRAIN TO SOURCE VOLTAGE (V)
5
VGS = -5.5 V
1.4
1.2
1.0
0.8
0
1
VGS = -10 V
VGS = -7 V
VGS = -6 V
2
3
4
Figure 15. Normalized on-Resistance vs. Drain
Current and Gate Voltage
3000
ID = -0.9 A
VGS = -10 V
2.0
rDS(on), DRAIN TO
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
-75
-50
-25
0
25
50
75
SOURCE ON-RESISTANCE (mΩ)
2.2
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
1.6
-ID, DRAIN CURRENT (A)
Figure 14. On- Region Characteristics
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
2500
ID = -0.9 A
2000
TJ = 125 oC
1500
TJ = 25 oC
1000
4
100 125 150
TJ, JUNCTION TEMPERATURE (oC)
5
6
7
8
9
Figure 17. On-Resistance vs. Gate to
Source Voltage
4
5
-IS, REVERSE DRAIN CURRENT (A)
Figure 16. Normalized On-Resistance
vs. Junction Temperature
3
VDS = -5 V
2
TJ = 150 oC
TJ = 25 oC
1
TJ = -55 oC
0
2
3
4
5
6
VGS = 0 V
1
TJ = 150 oC
0.1
TJ = 25 oC
0.01
TJ = -55 oC
0.001
0.0
7
0.2
0.4
0.6
0.8
1.0
-VGS, GATE TO SOURCE VOLTAGE (V)
-VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 18. Transfer Characteristics
Figure 19. Source to Drain Diode
Forward Voltage vs. Source Current
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
10
-VGS, GATE TO SOURCE VOLTAGE (V)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
-ID, DRAIN CURRENT (A)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = -5 V
7
1.2
www.fairchildsemi.com
FDMC8097AC Dual N & P-Channel PowerTrench® MOSFET
Typical Characteristics (Q2 P-Channel) TJ = 25 °C unless otherwise noted
ID = -0.9 A
Ciss
8
VDD = -75 V
VDD = -50 V
100
CAPACITANCE (pF)
-VGS, GATE TO SOURCE VOLTAGE (V)
1000
10
6
VDD = -100 V
4
Coss
10
Crss
1
2
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
f = 1 MHz
VGS = 0 V
0.1
0.1
3.5
100
2.5
-ID, DRAIN CURRENT (A)
20
-IAS, AVALANCHE CURRENT (A)
10
Figure 21. Capacitance vs. Drain
to Source Voltage
Figure 20. Gate Charge Characteristics
10
TJ = 25 oC
TJ = 100 oC
TJ = 125
oC
2.0
1.5
VGS = -10 V
1.0
VGS = -6 V
0.5
o
RθJC = 12.5 C/W
1
0.001
0.01
0.1
0.0
25
1
75
100
125
150
TC, CASE TEMPERATURE ( C)
Figure 23. Maximum Continuous Drain
Current vs. Case Temperature
Figure 22. Unclamped Inductive
Switching Capability
20
500
P(PK), PEAK TRANSIENT POWER (W)
10
100 μs
1
THIS AREA IS
LIMITED BY rDS(on)
0.1
1 ms
SINGLE PULSE
TJ = MAX RATED
RθJC = 12.5 oC/W
0.01
50
o
tAV, TIME IN AVALANCHE (ms)
-ID, DRAIN CURRENT (A)
1
-VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
CURVE BENT TO
MEASURED DATA
TC = 25 oC
1
10
10 ms
DC
100
500
TC = 25 oC
100
10
1
-4
10
-3
10
-2
10
-1
10
1
t, PULSE WIDTH (sec)
-VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 24. Forward Bias Safe
Operating Area
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
SINGLE PULSE
RθJC = 12.5 oC/W
Figure 25. Single Pulse Maximum Power
Dissipation
8
www.fairchildsemi.com
FDMC8097AC Dual N & P-Channel PowerTrench® MOSFET
Typical Characteristics (Q2 P-Channel) TJ = 25°C unless otherwise noted
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
2
1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
0.1
t2
NOTES:
SINGLE PULSE
0.01
-4
10
ZθJC(t) = r(t) x RθJC
RθJC = 12.5 oC/W
Peak TJ = PDM x ZθJC(t) + TC
Duty Cycle, D = t1 / t2
-3
-2
10
10
-1
10
1
t, RECTANGULAR PULSE DURATION (sec)
Figure 26. Junction-to-Case Transient Thermal Response Curve
©2015 Fairchild Semiconductor Corporation
FDMC8097AC Rev.1.0
9
www.fairchildsemi.com
FDMC8097AC Dual N & P-Channel PowerTrench® MOSFET
Typical Characteristics (Q2 P-Channel) TJ = 25 °C unless otherwise noted
0.10 C
A
3.00
2X
B
8
2.52
(0.20)
5
0.75(2X)
3.00
2.26
3.30
(0.35)
PIN#1
IDENT AREA
(0.20)2X
0.52
0.10 C
TOP VIEW
1
2X
0.45
1.75
4
RECOMMENDED LAND PATTERN
0.80 MAX
0.10 C
(0.20)
0.08 C
0.05
0.00
SEATING
PLANE
PIN #1
IDENT
NOTES:
C
SIDE VIEW
0.30 (2X)
(1.65)
1
A
4
(0.35)
4X
0.163
(0.35)
A. DOES NOT FULLY CONFORM TO
JEDEC REGISTRATION, MO-229.
B. DIMENSIONS ARE IN MILLIMETERS.
C. DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
D. LAND PATTERN RECOMMENDATION IS
BASED ON FSC DESIGN ONLY
E. DRAWING FILE NAME: MKT-MLP08Xrev2.
(0.25) 2X
(2X)
8
(2X)
5
0.30 (4X)
0.65
BOTTOM VIEW
0.10
0.05
C A B
C
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