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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
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FDMC8588
N-Channel PowerTrench® MOSFET
25 V, 40 A, 5.7 mΩ
Features
General Description
Max rDS(on) = 5.7 mΩ at VGS = 4.5 V, ID = 16.5 A
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency and to minimize switch node
ringing of DC/DC converters using either synchronous or
conventional switching PWM controllers. It has been optimized
for low gate charge, low rDS(on), fast switching speed and body
diode reverse recovery performance.
State-of-the-art switching performance
Lower output capacitance, gate resistance, and gate charge
boost efficiency
Shielded gate technology reduces switch node ringing and
increases immunity to EMI and cross conduction
Applications
RoHS Compliant
High side switching for high end computing
High power density DC-DC synchronous buck converter
Bottom
Top
S
D
D
D
Pin 1
S
S
G
D
S
D
S
D
S
D
G
D
Power 33
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
Drain to Source Voltage
Parameter
(Note 5)
Ratings
25
Units
V
VGS
Gate to Source Voltage
(Note 4)
±12
V
Drain Current
- Continuous (Package limited) TC = 25 °C
- Continuous (Silicon Limited)
ID
40
TC = 25 °C
- Continuous
59
(Note 1a)
- Pulsed
PD
TJ, TSTG
A
60
Single Pulse Avalanche Energy
EAS
16.5
(Note 3)
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
29
26
(Note 1a)
Operating and Storage Junction Temperature Range
2.4
-55 to +150
mJ
W
°C
Thermal Characteristics
RθJC
Thermal Resistance, Junction to Case
TC = 25 °C
RθJA
Thermal Resistance, Junction to Ambient
TA = 25 °C
4.7
(Note 1a)
53
°C/W
Package Marking and Ordering Information
Device Marking
08OD
Device
FDMC8588
©2012 Fairchild Semiconductor Corporation
FDMC8588 Rev.D4
Package
Power 33
1
Reel Size
13 ’’
Tape Width
12 mm
Quantity
3000 units
www.fairchildsemi.com
FDMC8588 N-Channel PowerTrench® MOSFET
November 2014
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA , VGS = 0 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
25
ID = 250 μA , referenced to 25 °C
IDSS
Zero Gate Voltage Drain Current
VDS = 20 V, VGS = 0 V
IGSS
Gate to Source Leakage Current, Forward VGS = 12 V, VDS = 0 V
V
17
mV/°C
1
μA
100
nA
1.8
V
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA , referenced to 25 °C
-4
VGS = 10 V, ID = 17 A
3.5
rDS(on)
Static Drain to Source On Resistance
VGS = 4.5 V, ID = 16.5 A
4.3
5.7
VGS = 10 V, ID = 17 A,TJ = 125 °C
4.8
6.9
VDD = 5 V, ID = 16.5 A
85
gFS
Forward Transconductance
0.8
1.4
mV/°C
5.0
mΩ
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Rg
Gate Resistance
VDS = 13 V, VGS = 0 V,
f = 1 MHz
1228
1720
pF
441
620
pF
0.1
69
100
pF
0.5
1.5
Ω
8
16
ns
3
10
ns
25
40
ns
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Rise Time
td(off)
Turn-Off Delay Time
tf
Fall Time
2
10
ns
Qg(TOT)
Total Gate Charge at 4.5V
12
17
nC
Qgs
Total Gate Charge
Qgd
Gate to Drain “Miller” Charge
VDD = 13 V, ID = 16.5A,
VGS = 10 V, RGEN = 6 Ω
VDD = 13 V, ID = 16.5 A
3.0
nC
3.3
nC
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
VGS = 0 V, IS = 2 A
(Note 2)
0.7
1.2
VGS = 0 V, IS = 16.5 A
(Note 2)
0.8
1.2
IF = 16.5 A, di/dt = 100 A/μs
V
V
25
ns
10
nC
Notes:
1. RθJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
b. 125 °C/W when mounted on
a minimum pad of 2 oz copper
a. 53 °C/W when mounted on a
1 in2 pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. EAS of 29 mJ is based on starting TJ = 25 °C, L = 1.2 mH, IAS = 7 A, VDD = 23 V, VGS = 10V. 100% tested at L = 0.1 mH, IAS = 16 A.
4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.
5. The continuous Vds rating is 25V; however, a pulse of 28 V peak voltage for no longer than 3ns duration at 500KHz frequency can be applied.
©2012 Fairchild Semiconductor Corporation
FDMC8588 Rev.D4
2
www.fairchildsemi.com
FDMC8588 N-Channel PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted
3.0
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
60
VGS = 10 V
ID, DRAIN CURRENT (A)
50
VGS = 4.5 V
VGS = 4 V
40
VGS = 3 V
30
VGS = 2.5 V
20
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
10
0
0.0
0.2
0.4
0.6
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
2.5
VGS = 2.5 V
2.0
VGS = 4 V
1.5
1.0
VGS = 4.5 V
0.5
0
10
Figure 1. On Region Characteristics
rDS(on), DRAIN TO
0.8
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
1.0
-50
60
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
15
ID = 16.5 A
10
TJ = 125 oC
5
TJ = 25 oC
0
-25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
0
2
4
6
8
10
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 4. On-Resistance vs. Gate to
Source Voltage
Figure 3. Normalized On Resistance
vs. Junction Temperature
60
IS, REVERSE DRAIN CURRENT (A)
60
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
50
ID, DRAIN CURRENT (A)
50
20
1.2
0.6
-75
40
Figure 2. Normalized On-Resistance
vs. Drain Current and Gate Voltage
ID = 16.5 A
VGS = 10 V
1.4
30
VGS = 10 V
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
1.6
20
VGS = 3 V
VDS = 5 V
40
TJ = 150 oC
30
TJ = 25 oC
20
TJ =
-55 oC
10
0
0.5
1.0
1.5
2.0
2.5
TJ = 150 oC
10
TJ = 25 oC
1
TJ = -55 oC
0.1
0.0
3.0
VGS, GATE TO SOURCE VOLTAGE (V)
0.2
0.4
0.6
0.8
1.0
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
©2012 Fairchild Semiconductor Corporation
FDMC8588 Rev.D4
VGS = 0 V
Figure 6. Source to Drain Diode
Forward Voltage vs. Source Current
3
www.fairchildsemi.com
FDMC8588 N-Channel PowerTrench® MOSFET
Typical Characteristics TJ = 25°C unless otherwise noted
3000
Ciss
ID = 16.5 A
3.6
VDD = 10 V
CAPACITANCE (pF)
VGS, GATE TO SOURCE VOLTAGE (V)
4.5
VDD = 13 V
2.7
VDD = 15 V
1.8
1000
0.9
Coss
Crss
100
f = 1 MHz
VGS = 0 V
0.0
0
2
4
6
8
10
30
0.1
12
Figure 7. Gate Charge Characteristics
30
10
ID, DRAIN CURRENT (A)
70
TJ = 25 oC
TJ = 100 oC
TJ
= 125 oC
60
VGS = 10 V
50
40
30
Limited by Package
VGS = 4.5 V
20 R = 4.7 oC/W
θJC
10
1
0.001
0.01
0.1
1
10
0
25
100
50
tAV, TIME IN AVALANCHE (ms)
125
150
Figure 10. Maximum Continuous Drain
Current vs. Case Temperature
P(PK), PEAK TRANSIENT POWER (W)
1000
100 μs
10
0.1
100
o
100
1
75
TC, CASE TEMPERATURE ( C)
Figure 9. Unclamped Inductive
Switching Capability
ID, DRAIN CURRENT (A)
10
Figure 8. Capacitance vs. Drain
to Source Voltage
50
IAS, AVALANCHE CURRENT (A)
1
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
1 ms
THIS AREA IS
LIMITED BY rDS(on)
10 ms
100 ms
1s
SINGLE PULSE
TJ = MAX RATED
10 s
RθJA = 125 oC/W
DC
TA = 25 oC
0.01
0.01
0.1
1
10
100200
10
SINGLE PULSE
RθJA = 125 oC/W
1
TA = 25 oC
0.5 -4
10
10
-3
-2
10
-1
10
0
10
1
10
100
1000
t, PULSE WIDTH (sec)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
©2012 Fairchild Semiconductor Corporation
FDMC8588 Rev.D4
100
Figure 12. Single Pulse Maximum
Power Dissipation
4
www.fairchildsemi.com
FDMC8588 N-Channel PowerTrench® MOSFET
Typical Characteristics TJ = 25°C unless otherwise noted
2
NORMALIZED THERMAL
IMPEDANCE, ZθJA
1
0.1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
0.01
t2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
o
RθJA = 125 C/W
1E-3
5E-4 -4
10
-3
10
-2
10
-1
0
10
10
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
©2012 Fairchild Semiconductor Corporation
FDMC8588 Rev.D4
5
www.fairchildsemi.com
FDMC8588 N-Channel PowerTrench® MOSFET
Typical Characteristics TJ = 25°C unless otherwise noted
3.40
3.20
A
PKG
C
L
8
3.40
2.37 MIN
(0.45) 8
B
5
1
2.15 MIN
1.70
3.40
3.20
PKG C
L
KEEP
OUT
AREA
SYM
C
L
5
0.70 MIN
(0.40)
(0.65)
4
1
SEE
DETAIL A
4
0.65
0.42 MIN
1.95
LAND PATTERN
RECOMMENDATION
0.10 C A B
0.37
0.27
1
PKG
C
L
1.95
0.65
4
0.50
0.30
(0.20)
2.09
(1.65) 1.89
(0.67)
8
(0.39)
0.52
5
(2.27)
0.10 C
1.00
0.85
0.08 C
0.23
0.18
0.05
0.00
SCALE: 2X
C
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC MO-240, ISSUE A, VAR. BA,
DATED OCTOBER 2002.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING FILE NAME: PQFN08BREV2
SEATING
PLANE
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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