FDMC8588DC
N-Channel Dual CoolTM 33 PowerTrench® MOSFET
25 V, 40 A, 5.7 mΩ
Features
General Description
Dual CoolTM Top Side Cooling PQFN package
This N-Channel MOSFET has been designed specifically to
improve the overall efficiency and to minimize switch node
ringing of DC/DC converters using either synchronous or
conventional switching PWM controllers. It has been optimized
for low gate charge, low rDS(on), fast switching speed and body
diode reverse recovery performance.
Max rDS(on) = 5.7 mΩ at VGS = 4.5 V, ID = 17 A
State-of-the-art switching performance
Lower output capacitance, gate resistance, and gate charge
boost efficiency
Applications
Shielded gate technology reduces switch node ringing and
increases immunity to EMI and cross conduction
High side switching for high end computing
RoHS Compliant
High power density DC-DC synchronous buck converter
Pin 1
S
S
S
G
Pin 1
D
D
Top
Dual
CoolTM
33
D
D
S
D
S
D
S
D
G
D
Bottom
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
Drain to Source Voltage
Parameter
(Note 5)
Ratings
25
Units
V
VGS
Gate to Source Voltage
(Note 4)
±12
V
Drain Current
- Continuous (Package limited) TC = 25 °C
- Continuous (Silicon Limited)
ID
40
TC = 25 °C
- Continuous
73
(Note 1a)
- Pulsed
PD
TJ, TSTG
A
60
Single Pulse Avalanche Energy
EAS
17
(Note 3)
Power Dissipation
TC = 25 °C
Power Dissipation
TA = 25 °C
29
41
(Note 1a)
Operating and Storage Junction Temperature Range
3.0
-55 to +150
mJ
W
°C
Thermal Characteristics
RθJC
Thermal Resistance, Junction to Case
(Top Source)
7.0
RθJC
Thermal Resistance, Junction to Case
(Bottom Drain)
3.0
RθJA
Thermal Resistance, Junction to Ambient
(Note 1a)
42
RθJA
Thermal Resistance, Junction to Ambient
(Note 1b)
105
RθJA
Thermal Resistance, Junction to Ambient
(Note 1i)
17
RθJA
Thermal Resistance, Junction to Ambient
(Note 1j)
26
RθJA
Thermal Resistance, Junction to Ambient
(Note 1k)
12
°C/W
Package Marking and Ordering Information
Device Marking
08DC
Device
FDMC8588DC
©2012 Fairchild Semiconductor Corporation
FDMC8588DC Rev.1.1
Package
Dual CoolTM 33
1
Reel Size
13 ’’
Tape Width
12 mm
Quantity
3000 units
www.fairchildsemi.com
FDMC8588DC N-Channel Dual CoolTM 33 PowerTrench® MOSFET
February 2016
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA , VGS = 0 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
25
ID = 250 μA , referenced to 25 °C
IDSS
Zero Gate Voltage Drain Current
VDS = 20 V, VGS = 0 V
IGSS
Gate to Source Leakage Current, Forward VGS = 12 V, VDS = 0 V
V
5
mV/°C
1
μA
100
nA
1.8
V
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA , referenced to 25 °C
VGS = 10 V, ID = 18 A
3.6
5.0
rDS(on)
Static Drain to Source On Resistance
VGS = 4.5 V, ID = 17 A
4.1
5.7
VGS = 10 V, ID = 18 A,TJ = 125 °C
5.5
7.6
VDD = 5 V, ID = 17 A
103
gFS
Forward Transconductance
0.8
1.2
-4
mV/°C
mΩ
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Rg
Gate Resistance
VDS = 13 V, VGS = 0 V,
f = 1 MHz
1695
pF
493
pF
63
pF
0.4
Ω
8
ns
3
ns
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Rise Time
td(off)
Turn-Off Delay Time
tf
Fall Time
Qg(TOT)
Total Gate Charge at 4.5V
Qgs
Total Gate Charge
Qgd
Gate to Drain “Miller” Charge
VDD = 13 V, ID = 17A,
VGS = 10 V, RGEN = 6 Ω
VDD = 13 V, ID = 17 A
25
ns
2
ns
12
nC
3.0
nC
3.0
nC
Drain-Source Diode Characteristics
VSD
Source to Drain Diode Forward Voltage
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
©2012 Fairchild Semiconductor Corporation
FDMC8588DC Rev.1.1
VGS = 0 V, IS = 2 A
(Note 2)
0.7
1.2
V
VGS = 0 V, IS = 17 A
(Note 2)
0.8
1.2
V
IF = 17 A, di/dt = 100 A/μs
2
25
ns
10
nC
www.fairchildsemi.com
FDMC8588DC N-Channel Dual CoolTM 33 PowerTrench® MOSFET
Electrical Characteristics TJ = 25 °C unless otherwise noted
RθJC
Thermal Resistance, Junction to Case
(Top Source)
7.0
RθJC
Thermal Resistance, Junction to Case
(Bottom Drain)
3.0
RθJA
Thermal Resistance, Junction to Ambient
(Note 1a)
42
RθJA
Thermal Resistance, Junction to Ambient
(Note 1b)
105
RθJA
Thermal Resistance, Junction to Ambient
(Note 1c)
29
RθJA
Thermal Resistance, Junction to Ambient
(Note 1d)
40
RθJA
Thermal Resistance, Junction to Ambient
(Note 1e)
19
RθJA
Thermal Resistance, Junction to Ambient
(Note 1f)
23
RθJA
Thermal Resistance, Junction to Ambient
(Note 1g)
30
RθJA
Thermal Resistance, Junction to Ambient
(Note 1h)
79
RθJA
Thermal Resistance, Junction to Ambient
(Note 1i)
17
RθJA
Thermal Resistance, Junction to Ambient
(Note 1j)
26
RθJA
Thermal Resistance, Junction to Ambient
(Note 1k)
12
RθJA
Thermal Resistance, Junction to Ambient
(Note 1l)
16
°C/W
Notes:
1. RθJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by
the user's board design.
b. 105 °C/W when mounted on
a minimum pad of 2 oz copper
a. 42 °C/W when mounted on a
1 in2 pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
c. Still air, 20.9x10.4x12.7mm Aluminum Heat Sink, 1 in2 pad of 2 oz copper
d. Still air, 20.9x10.4x12.7mm Aluminum Heat Sink, minimum pad of 2 oz copper
e. Still air, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, 1 in2 pad of 2 oz copper
f. Still air, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, minimum pad of 2 oz copper
g. 200FPM Airflow, No Heat Sink,1 in2 pad of 2 oz copper
h. 200FPM Airflow, No Heat Sink, minimum pad of 2 oz copper
i. 200FPM Airflow, 20.9x10.4x12.7mm Aluminum Heat Sink, 1 in2 pad of 2 oz copper
j. 200FPM Airflow, 20.9x10.4x12.7mm Aluminum Heat Sink, minimum pad of 2 oz copper
k. 200FPM Airflow, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, 1 in2 pad of 2 oz copper
l. 200FPM Airflow, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. EAS of 29 mJ is based on starting TJ = 25 °C, L = 1.2 mH, IAS = 7 A, VDD = 23 V, VGS = 10V. 100% tested at L = 0.1 mH, IAS = 16 A.
4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied.
5. The continuous Vds rating is 25V; however, a pulse of 28 V peak voltage for no longer than 3ns duration at 500KHz frequency can be applied.
©2012 Fairchild Semiconductor Corporation
FDMC8588DC Rev.1.1
3
www.fairchildsemi.com
FDMC8588DC N-Channel Dual CoolTM 33 PowerTrench® MOSFET
Thermal Characteristics
3.0
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
60
VGS = 10 V
ID, DRAIN CURRENT (A)
50
VGS = 4.5 V
VGS = 4 V
40
VGS = 3 V
30
VGS = 2.5 V
20
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
10
0
0.0
0.2
0.4
0.6
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
2.5
VGS = 2.5 V
2.0
VGS = 4 V
1.5
1.0
VGS = 4.5 V
0.5
0
10
Figure 1. On Region Characteristics
rDS(on), DRAIN TO
0.8
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
1.0
-50
60
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
15
ID = 17 A
10
TJ = 125 oC
5
TJ = 25 oC
0
-25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
0
2
4
6
8
10
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 4. On-Resistance vs Gate to
Source Voltage
Figure 3. Normalized On Resistance
vs Junction Temperature
60
IS, REVERSE DRAIN CURRENT (A)
60
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
50
ID, DRAIN CURRENT (A)
50
20
1.2
0.6
-75
40
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
ID = 17 A
VGS = 10 V
1.4
30
VGS = 10 V
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
1.6
20
VGS = 3 V
VDS = 5 V
40
TJ = 150 oC
30
TJ = 25 oC
20
TJ =
-55 oC
10
0
0.5
1.0
1.5
2.0
2.5
TJ = 150 oC
10
TJ = 25 oC
1
TJ = -55 oC
0.1
0.0
3.0
VGS, GATE TO SOURCE VOLTAGE (V)
0.2
0.4
0.6
0.8
1.0
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
©2012 Fairchild Semiconductor Corporation
FDMC8588DC Rev.1.1
VGS = 0 V
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
4
www.fairchildsemi.com
FDMC8588DC N-Channel Dual CoolTM 33 PowerTrench® MOSFET
Typical Characteristics TJ = 25°C unless otherwise noted
3000
ID = 17 A
Ciss
VDD = 10 V
3.6
CAPACITANCE (pF)
VGS, GATE TO SOURCE VOLTAGE (V)
4.5
VDD = 13 V
2.7
VDD = 15 V
1.8
1000
Coss
Crss
100
0.9
f = 1 MHz
VGS = 0 V
0.0
0
3
6
9
12
30
0.1
15
1
Figure 7. Gate Charge Characteristics
80
10
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
30
Figure 8. Capacitance vs Drain
to Source Voltage
50
TJ = 25 oC
TJ
= 100 oC
TJ = 125 oC
1
0.001
0.01
0.1
1
10
VGS = 10 V
60
40
Limited by Package
o
RθJC = 3.0 C/W
20
0
25
100
50
tAV, TIME IN AVALANCHE (ms)
100
125
150
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
P(PK), PEAK TRANSIENT POWER (W)
1000
100 μs
10
0.1
75
o
100
1
VGS = 4.5 V
TC, CASE TEMPERATURE ( C)
Figure 9. Unclamped Inductive
Switching Capability
ID, DRAIN CURRENT (A)
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
1 ms
10 ms
THIS AREA IS
LIMITED BY rDS(on)
100 ms
1s
SINGLE PULSE
TJ = MAX RATED
10 s
RθJA = 105 oC/W
DC
TA = 25 oC
0.01
0.01
0.1
1
10
100200
10
SINGLE PULSE
RθJA = 105 oC/W
1
TA = 25 oC
0.5 -4
10
10
-3
-2
10
-1
10
0
10
1
10
100
1000
t, PULSE WIDTH (sec)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 11. Forward Bias Safe
Operating Area
©2012 Fairchild Semiconductor Corporation
FDMC8588DC Rev.1.1
100
Figure 12. Single Pulse Maximum
Power Dissipation
5
www.fairchildsemi.com
FDMC8588DC N-Channel Dual CoolTM 33 PowerTrench® MOSFET
Typical Characteristics TJ = 25°C unless otherwise noted
2
NORMALIZED THERMAL
IMPEDANCE, ZθJA
1
0.1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
0.01
t2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
o
RθJA = 105 C/W
1E-3
5E-4 -4
10
-3
10
-2
10
-1
0
10
10
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
©2012 Fairchild Semiconductor Corporation
FDMC8588DC Rev.1.1
6
www.fairchildsemi.com
FDMC8588DC N-Channel Dual CoolTM 33 PowerTrench® MOSFET
Typical Characteristics TJ = 25°C unless otherwise noted
3.30
3.40
2.37 MIN
A
PKG
CL
B
8
5
8
SYM
CL
KEEP
OUT
AREA
5
(0.45)
2.15 MIN
PKG
CL
3.30
PKG
CL
(0.40)
0.70 MIN
(0.65)
1
4
1
SEE DETAIL 'A'
4
0.65
0.42 MIN
1.95
LAND PATTERN
RECOMMENDATION
0.10 C A B
1.95
0.65
0.32±0.05
1
4
0.40±0.10
(0.20)
PKG
CL
3.30±0.10
2.00±0.10
(0.39)
8
0.52
5
(2.27)
3.30±0.10
0.10 C
1.00±0.05
0.08 C
0.05
0.00
0.20±0.025
SCALE: 2X
C
SEATING
PLANE
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC MO-240, ISSUE A, VAR. BA,
DATED OCTOBER 2002.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-2009.
E) DRAWING FILE NAME: PQFN08CREV3
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Definition of Terms
Datasheet Identification
Product Status
Advance Information
Formative / In Design
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
Definition
Datasheet contains the design specifications for product development. Specifications may change
in any manner without notice.
Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
Semiconductor reserves the right to make changes at any time without notice to improve design.
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The datasheet is for reference information only.
Rev. I77
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