FDMD86100

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This literature is subject to all applicable copyright laws and is not for resale in any manner. FDMD86100 Dual N-Channel Shielded Gate PowerTrench® MOSFET 100 V, 39 A, 10.5 mΩ Features General Description „ Common source configuration to eliminate PCB routing This package integrates two N-Channel devices connected internally in common-source configuration and incorporates Shielded Gate technology. This enables very low package parasitics and optimized thermal path to the common source pad on the bottom. Provides a very small footprint (5 x 6 mm) for higher power density. „ Large source pad on bottom of package for enhanced thermals „ Shielded Gate MOSFET Technology „ Max rDS(on) = 10.5 mΩ at VGS = 10 V, ID = 10 A „ Max rDS(on) = 17.3 mΩ at VGS = 6 V, ID = 7.8 A Applications „ Ideal for flexible layout in secondary side synchronous rectification „ Isolated DC-DC Synchronous Rectifiers „ Common Ground Load Switches „ Termination is Lead-free and RoHS Compliant „ 100% UIL tested Top Bottom G1 Pin 1 Pin 1 D1 D1 G1 1 8 D2 D1 2 7 D2 D1 3 6 D2 D1 4 5 G2 D1 S1 / S2 D2 D2 D2 G2 S1,S2 to backside Power 5 x 6 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current ID Drain Current TJ, TSTG ±20 V TC = 25 °C -Continuous TC = 100 °C (Note 5) 24 -Continuous TA = 25 °C (Note 1a) 10 -Pulsed PD Units V -Continuous Single Pulse Avalanche Energy EAS Power Dissipation TC = 25 °C Power Dissipation TA = 25 °C (Note 5) Ratings 100 39 (Note 4) 299 (Note 3) 337 33 (Note 1a) Operating and Storage Junction Temperature Range 2.2 -55 to +150 A mJ W °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient 3.7 (Note 1a) 55 °C/W Package Marking and Ordering Information Device Marking FDMD86100 Device FDMD86100 ©2015 Fairchild Semiconductor Corporation FDMD86100 Rev.C1 Package Power 5 x 6 1 Reel Size 13 ’’ Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMD86100 Dual N-Channel Shielded Gate PowerTrench® MOSFET February 2015 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 4.0 V 100 V 7 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C -10 VGS = 10 V, ID = 10 A 7.8 10.5 rDS(on) Static Drain to Source On Resistance VGS = 6 V, ID = 7.8 A 12 17.3 14.5 19.5 2.0 VGS = 10 V, ID = 10 A, TJ = 125 °C gFS Forward Transconductance VDD = 5 V, ID = 10 A 3.0 mV/°C 26 mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 50 V, VGS = 0 V f = 1 MHz 0.1 1469 2060 pF 321 450 pF 12 20 pF 1.3 3.3 Ω Switching Characteristics td(on) Turn-On Delay Time 13 23 ns tr Rise Time 4.3 10 ns td(off) Turn-Off Delay Time 18 32 ns tf Fall Time 4.1 10 ns Qg(TOT) Total Gate Charge VGS = 0 V to 10 V 21 30 nC Qg(TOT) Total Gate Charge VGS = 0 V to 6 V 13 18 Qgs Gate to Source Charge Qgd Gate to Drain “Miller” Charge VDD = 50 V, ID = 10 A VGS = 10 V, RGEN = 6 Ω VDD = 50 V ID = 10 A nC 6.6 nC 4.1 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 10 A (Note 2) 0.8 1.3 V VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 2 A (Note 2) 0.7 1.2 V trr Reverse Recovery Time Qrr Reverse Recovery Charge IF = 10 A, di/dt = 100 A/μs 46 74 ns 46 74 nC NOTES: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθCA is determined by the user's board design. b.125 °C/W when mounted on a minimum pad of 2 oz copper a. 55 °C/W when mounted on a 1 in2 pad of 2 oz copper SS SF DS DF G SS SF DS DF G 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %. 3. EAS of 337 mJ is based on starting TJ = 25 oC, L = 3 mH, IAS = 15 A, VDD = 100 V, VGS = 10 V. 100% tested at L = 0.1 mH, IAS = 47 A. 4. Pulsed Id please refer to Fig 11 SOA graph for more details. 5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design. ©2015 Fairchild Semiconductor Corporation FDMD86100 Rev.C1 2 www.fairchildsemi.com FDMD86100 Dual N-Channel Shielded Gate PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted 150 120 VGS = 7 V 90 VGS = 6.5 V 60 VGS = 6 V 30 VGS = 5.5 V PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0 1 2 3 4 4 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) VGS = 10 V VGS = 5.5 V VGS = 6 V 3 VGS = 6.5 V 2 VGS = 7 V 1 0 5 0 30 VDS, DRAIN TO SOURCE VOLTAGE (V) 80 rDS(on), DRAIN TO 1.6 1.4 1.2 1.0 0.8 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID = 10 A VGS = 10 V 1.8 60 40 TJ = 125 oC 20 -50 -25 0 25 50 75 0 100 125 150 4 IS, REVERSE DRAIN CURRENT (A) ID, DRAIN CURRENT (A) VDS = 5 V 90 TJ = 150 oC TJ = 25 oC 30 TJ = -55 oC 3 4 5 6 7 8 6 7 8 9 9 200 100 VGS = 0 V 10 TJ = 150 oC 1 TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.001 0.0 10 0.2 0.4 0.6 0.8 1.0 VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current ©2015 Fairchild Semiconductor Corporation FDMD86100 Rev.C1 10 Figure 4. On-Resistance vs Gate to Source Voltage PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 60 5 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On- Resistance vs Junction Temperature 2 150 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX ID = 10 A TJ, JUNCTION TEMPERATURE (oC) 0 120 TJ = 25 oC 0.6 -75 120 90 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 2.2 150 60 ID, DRAIN CURRENT (A) Figure 1. On-Region Characteristics 2.0 VGS = 10 V PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 3 1.2 www.fairchildsemi.com FDMD86100 Dual N-Channel Shielded Gate PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 5000 ID = 10 A Ciss VDD = 25 V 1000 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 50 V 6 VDD = 75 V 4 Coss 100 Crss 10 2 0 f = 1 MHz VGS = 0 V 0 6 12 18 1 0.1 24 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 100 40 o ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) RθJC = 3.7 C/W TJ = 25 oC TJ = 100 oC 10 TJ = 125 oC 1 0.001 0.01 0.1 1 10 32 VGS = 10 V 24 VGS = 6 V 16 8 0 25 100 50 75 100 Figure 10. Maximum Continuous Drain Current vs Case Temperature 500 P(PK), PEAK TRANSIENT POWER (W) 20000 SINGLE PULSE RθJC = 3.7 oC/W ID, DRAIN CURRENT (A) 10000 100 10 μs 10 THIS AREA IS LIMITED BY rDS(on) 100 μs SINGLE PULSE TJ = MAX RATED 1 ms o RθJC = 3.7 C/W TC = 25 oC 0.1 0.1 150 TC, CASE TEMPERATURE ( C) Figure 9. Unclamped Inductive Switching Capability 1 125 o tAV, TIME IN AVALANCHE (ms) CURVE BENT TO MEASURED DATA 1 10 10 ms DC 100 300 1000 100 10 -5 10 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 11. Forward Bias Safe Operating Area ©2015 Fairchild Semiconductor Corporation FDMD86100 Rev.C1 TA = 25 oC Figure 12. Single Pulse Maximum Power Dissipation 4 www.fairchildsemi.com FDMD86100 Dual N-Channel Shielded Gate PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 2 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: 0.01 ZθJC(t) = r(t) x RθJC RθJC = 3.7 oC/W Peak TJ = PDM x ZθJC(t) + TC Duty Cycle, D = t1 / t2 SINGLE PULSE 0.001 -5 10 -4 10 -3 -2 10 10 -1 10 1 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Case Transient Thermal Response Curve ©2015 Fairchild Semiconductor Corporation FDMD86100 Rev.C1 5 www.fairchildsemi.com FDMD86100 Dual N-Channel Shielded Gate PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 5.00±0.10 0.10 C 2X PKG CL 8 KEEP-OUT AREA A 3.81 1.91 8 B 5 1.27 6 7 5 0.52 (8X) 0.72 (6X) 0.70 (2X) 1.79 CL PKG PIN #1 INDICATOR 6.00±0.10 1 2.88 1.72 (2X) 0.60 (2X) 0.10 C 4 1 2X 2 3 1.79 3.58 5.00 RECOMMENDED LAND PATTERN C A B C 0.08 C C 0.30 0.20 0.42±.05 (6X) 1 4 0.80 0.70 0.10 0.05 1.27 3 6.22 0.10 C SIDE VIEW 0.39 TYP 2 0.97 TOP VIEW SEE DETAIL A (0.78) 2X 0.30 (2X) 4 0.05 0.00 SEATING PLANE 0.56±.10 (6X) 1.56±.10 2X NOTES: (1.74) 0.30±.05 4X 3.48±.05 (1.04) 0.70 TYP 8 7 6 0.30±.05 2X 5 0.76 3.42 (2X) 3.48±.05 BOTTOM VIEW (0.92) 2X (SCALE: 2X) A) PACKAGE REFERENCE : TO JEDEC REGISTRATION, MO-240B, VARIATION AA. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009 E) IT IS RECOMMENDED TO HAVE NO TRACES OR VIAS WITHIN THE KEEP-OUT AREA F) DRAWING FILE NAME: PQFN08OREV1 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. 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