FDMF6700
Driver plus FET Multi-chip Module
tm
Benefits
General Description
Fully optimized system efficiency. Higher efficiency levels
are achievable compared with conventional discrete
components.
The FDMF6700 is a fully optimized integrated 12V Driver plus
MOSFET power stage solution for high current synchronous
buck DC-DC applications. The device integrates a driver IC and
two Power MOSFETs into a space saving, 6mm x 6mm, 40-pin
Power66™ package. Fairchild Semiconductor’s integrated
approach optimizes the complete switching power stage with
regards to driver to FET dynamic performance, system
inductance and overall solution ON resistance. Package
parasitics and problematical layouts associated with
conventional discrete solutions are greatly reduced. This
integrated approach results in significant board space saving,
therefore maximizing footprint power density. This solution is
based on the Intel™ DrMOS specification.
Space savings of up to 50% PCB versus discrete solutions.
Higher frequency of operation.
Simpler system design and board layout. Reduced time in
component selection and optimization.
Features
12V typical Input Voltage
Output current up to 25A
500KHz switching frequency capable
Applications
Internal adaptive gate drive
Integrated bootstrap diode
Desktop and server VR11.x V-core and non V-core buck
converters.
Peak Efficiency >85%
Under-voltage Lockout
Output disable for lost phase shutdown
CPU/GPU power train in game consoles and high end
desktop systems.
Low profile SMD package
High-current DC-DC Point of Load (POL) converters
RoHS Compliant
Networking and telecom microprocessor voltage regulators
Small form factor voltage regulator modules
Powertrain Application Circuit
12V
CVCC
VCIN
DISB
VIN
DISB
BOOT
CBOOT
PWM
Input
PWM
CGND
VSWH
OUTPUT
COUT
PGND
Figure 1. Powertrain Application Circuit
Ordering Information
Part
Current Rating
Max
[A]
Input Voltage
Typical
[V]
Frequency
Max
[KHz]
Device
Marking
FDMF6700
25
12
500
FDMF6700
©2007 Fairchild Semiconductor Corporation
FDMF6700 Rev. B
1
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FDMF6700 Driver plus FET Multi-chip Module
May 2007
BOOT VCIN
HDRV
VIN
DISB
PWM
1.2
2.2
VSWH
1.2
VCIN
LDRV
CGND
PGND
Figure 2. Functional Block Diagram
CGND
NC
VCIN
BOOT
CGND
VSWH
NC
TEST PAD1
VIN
VIN
Pin Configuration
1
PWM
DISB
TEST PAD2
CGND
VSWH
PGND
PGND
PGND
PGND
PGND
10
40
11
(VIN)
(CGND)
(VSWH)
20
31
21
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
VSWH
30
VIN
VIN
VIN
VIN
VSWH
VSWH
VSWH
VSWH
VSWH
VSWH
Figure 3. Power66 40L Bottom View
FDMF6700 Rev. B
2
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FDMF6700 Driver plus FET Multi- chip Module
Functional Block Diagram
Pin
Name
1,5,37,A
CGND
2,7
NC
Function
IC Ground. Ground return for driver IC.
No connect
3
VCIN
IC Supply. +12V chip bias power. Bypass with a 1µF ceramic capacitor.
4
BOOT
Bootstrap Supply Input. Provides voltage supply to high-side MOSFET driver. Connect
bootstrap capacitor.
6,15-21,36,C
VSWH
Switch Node Input. SW Provides return for high-side bootstrapped driver and acts as a
sense point for the adaptive shoot-thru protection.
9-4,B
VIN
8
TEST PAD 1
Power Input. Output stage supply voltage.
For manufacturing test only. HDRV pin. This pin must be floated. Must not be connected to
any pin.
22-35
PGND
38
TEST PAD 2
Power ground. Output stage ground. Source pin of low side MOSFET(s).
For manufacturing test only. LDRV pin. This pin must be floated. Must not be connected to
any pin.
39
DISB
Output Disable. When low, this pin disable FET switching (HDRV and LDRV are held low).
40
PWM
PWM Signal Input. This pin accepts a logic-level PWM signal from the controller.
Absolute Maximum Rating
Parameter
Min.
Max.
Units
VCIN to PGND
-0.5
15
V
VIN to PGND
-0.5
15
V
-0.3
5.5
V
-1
15
V
PWM, DSIB to GND
VSWH to PGND
Continuous
Transient (t = 100ns, fsw = 500KHz)
-5
25
V
-0.3
15
V
Continuous
-0.3
30
V
Transient (t = 100ns, fsw = 500KHz)
-0.3
33
V
BOOT to VSWH
BOOT to PGND
IO(AV)
VIN = 12V, VO = 1.3V, fsw = 500KHz, TPCB = 100°C
25
A
IO(PK)
VIN = 12V, tPULSE = 10µs
65
A
RθJPCB
Junction to PCB Thermal Resistance (note 1)
6.5
°C/W
PD
TPCB = 100°C (note 1)
7.7
W
150
°C
Operating and Storage Junction Temperature Range
-55
Recommended Operating Range
Parameter
Min.
Typ.
Max.
Units
VCIN
Control Circuit Supply Voltage
6.4
12
13.5
V
VIN
Output Stage Supply Voltage
6.4
12
14
V
Electrical Characteristics
VIN = 12V, TA = 25°C unless otherwise noted.
Parameter
Symbol
Control Circuit Supply Current
ICIN
Undervoltage lockout threshold
VTH(UVLO)(2)
PWM Input High Voltage
VIH(PWM)
FDMF6700 Rev. B
Conditions
Min.
Typ.
Max.
fSW = 0Hz, VDISB = 0V
3.5
8
fSW = 500KHz, VDISB = 5V
18
Units
mA
Turn-on
6
V
Turn-off
5.25
V
3.5
3
V
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FDMF6700 Driver plus FET Multi- chip Module
Pin Description
VIN = 12V, TA = 25°C unless otherwise noted.
Parameter
Symbol
Conditions
Min.
PWM Input Low Voltage
VIL(PWM)
PWM Input Current
IPWM
-1
Output Disable Input High Voltage
VIH(DISB)
2.5
Output Disable Input Low Voltage
VIL(DISB)
Output Disable Input Current
IDISB
Output Stage Leakage Current
IIN_LEAKAGE
VDISB = 0V
Propagation Delay
Max.
Units
0.8
V
1
µA
V
-1
0.8
V
1
µA
250
µA
41
ns
VIN = 12V, VOUT = 1.3V,
37
ns
fsw = 500KHz, IO = 25A
34
ns
53
ns
tPDL(LDRV)(3)
tPDL(HDRV)(3)
tPDH(LDRV)(3)
tPDH(HDRV)(3)
Typ.
Note 1: Package power dissipation based on 4 layer, 2 square inch, 2 oz. copper pad. RθJPCB is the steady state junction to PCB
thermal resistance with PCB temperature referenced at VSWH pin.
Note 2: When combined with controller, driver UVLO must be less than that of controller.
Note 3: tPDL(LDRV/HRDV) refers to HIGH-to-LOW transition, tPDH(LDRV/HDRV) refers to LOW-to-HIGH transition.
FDMF6700 Rev. B
4
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FDMF6700 Driver plus FET Multi- chip Module
Electrical Characteristics
30
8
VIN = 12V
VOUT = 1.3V
L = 0.68uH
25
6
PLOSS, W
ILOAD, A
20
15
fSW = 500KHz
4
10
fSW = 300KHz
VIN = 12V
VOUT = 1.3V
fSW = 500KHz
L = 0.68uH
5
2
0
0
0
25
50
75
100
o
PCB Temperature, C
125
0
150
5
10
15
20
25
ILOAD, A
Figure 4. Safe Operating Area vs. PCB Temperature
Figure 5. Module Power Loss vs. Output Current
(VO measured at VSWH pin)
1.25
1.20
1.15
PLOSS (NORMALIZED)
PLOSS (NORMALIZED)
1.2
VIN = 12V
VOUT = 1.3V
IOUT = 25A
L = 0.68uH
1.10
1.05
1.00
1.1
1.0
VOUT = 1.3V
IOUT = 25A
L = 0.68uH
fSW = 300KHz
0.95
0.90
0.9
200
250
300
350
400
450
500
6
8
10
Switching Frequency, KHz
Figure 6. Power Loss vs. Switching Frequency
1.6
PLOSS (NORMALIZED)
PLOSS (NORMALIZED)
1.05
1.03
VIN = 12V
VOUT = 1.3V
IOUT = 25A
L = 0.68uH
fSW = 300KHz
0.95
7
8
1.4
1.2
1.0
0.8
9
10
11
12
0.8
13
1.2
1.6
2.0
2.4
2.8
3.2
Output Voltage, V
Driver Supply Voltage, V
Figure 8. Power Loss vs. Supply Voltage
FDMF6700 Rev. B
16
VIN = 12V
IOUT = 25A
L = 0.68uH
fSW = 300KHz
1.08
0.98
14
Figure 7. Power Loss vs. Input Voltage
1.10
1.00
12
Input Voltage, V
Figure 9. Power Loss vs. Output Voltage
5
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FDMF6700 Driver plus FET Multi-chip Module
Typical Characteristics
4.4
4.0
1.05
Supply Current, mA
PLOSS (NORMALIZED)
4.2
1.00
VIN = 12V
VOUT = 1.3V
IOUT = 25A
fSW = 300KHz
0.95
3.8
PWM=DISB=5V
3.6
3.4
3.2
PWM=DISB=0V
3.0
2.8
0.90
0.3
0.4
0.5
0.6
0.7
0.8
0.9
6
1.0
7
8
9
Figure 10. Power Loss vs. Output Inductance
12
13
14
15
20
VCIN = 12V
VCIN = 12V
IQ
3.2
16
IQ_OFF
Supply Current, mA
Supply Current, mA
11
Figure 11. Supply Current vs. Supply Voltage
3.3
3.1
3.0
2.9
12
8
4
2.8
-50
-25
0
25
50
75
100
125
0
150
0
o
100
200
300
Frequency, kHz
Temperature, C
Figure 12. Supply Current vs. Temperature
400
500
Figure 13. Supply Current vs. Frequency
2.0
2.0
VCIN = 12V
VIH
1.9
DISB Threshold Voltage, V
1.9
DISB Threshold Voltage, V
10
Supply Voltage, V
Output Inductance, uH
1.8
1.7
1.6
VIL
1.5
VIH
1.8
1.7
1.6
VIL
1.5
1.4
1.4
6
7
8
9
10
11
12
13
14
15
-50
Figure 14. DISB Threshold Voltage vs. Driver Supply Voltage
FDMF6700 Rev. B
-25
0
25
50
75
100
125
150
Temperature, oC
Driver Supply Voltage, V
Figure 15. DISB Threshold Voltage vs. Temperature
6
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FDMF6700 Driver plus FET Multi-chip Module
1.10
VCIN = 12V
VIH
2.7
PWM Threshold Voltage, V
PWM Threshold Voltage, V
2.7
2.4
2.1
1.8
VIL
1.5
VIH
2.4
2.1
1.8
VIL
1.5
1.2
1.2
6
7
8
9
10
11
12
13
14
15
-50
-25
0
Figure 16. PWM Threshold Voltage vs. Driver Supply Voltage
50
75
100
125
150
Figure 17. PWM Threshold Voltage vs. Temperature
-13
36
35
VBOOT - GND, V
-11
-9
VSW, V
25
Temperature, oC
Driver Supply Voltage, V
-7
-5
34
33
32
31
30
-3
0
100
200
300
400
0
500
100
200
300
400
500
Transient Duration, nsec
Transient Duration, nsec
Figure 18. VSWH vs. Transient Duration
Figure 19. Boot to Ground Voltage vs. Transient Duration
PWM
PWM
HDRV
HDRV
LDRV
LDRV
VIN = 12V
VCIN = 12V
VOUT = 1.3V
fsw = 500KHz
IOUT = 0A
VSWH
VSWH
Figure 20. Switching Waveform at Iout = 0A
FDMF6700 Rev. B
VIN = 12V
VCIN = 12V
VOUT = 1.3V
fsw = 500KHz
IOUT = 25A
Figure 21. Switching Waveform at Iout = 25A
7
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FDMF6700 Driver plus FET Multi-chip Module
3.0
3.0
PWM
HDRV
HDRV
LDRV
LDRV
VSWH
VIN = 12V
VCIN = 12V
VOUT = 1.3V
fsw = 500KHz
IOUT = 25A
VSWH
Figure 23. Switching Waveform (Falling Edge)
Figure 22. Switching Waveform (Rising edge)
FDMF6700 Rev. B
VIN = 12V
VCIN = 12V
VOUT = 1.3V
fsw = 500KHz
IOUT = 25A
8
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FDMF6700 Driver plus FET Multi-chip Module
PWM
Adaptive Gate Drive Circuit
Circuit Description
The driver IC embodies an advanced design that ensures
minimum MOSFET dead-time while eliminating potential
shoot-through (cross-conduction) currents. It senses the state of
the MOSFETs and adjusts the gate drive, adaptively, to ensure
they do not conduct simultaneously. Refer to Figure 24 and 25
for the relevant timing waveforms.
The FDMF6700 is a driver plus FET module optimized for
synchronous buck converter topology. A single PWM input
signal is all that is required to properly drive the high-side and
the low-side MOSFETs. Each part is capable of driving speeds
up to 500KHz.
To prevent overlap during the low-to-high switching transition
(Q2 OFF to Q1 ON), the adaptive circuitry monitors the voltage
at the LDRV pin. When the PWM signal goes HIGH, Q2 will
begin to turn OFF after some propagation delay (tPDL(LDRV)).
Once the LDRV pin is discharged below ~1.2V, Q1 begins to
turn ON after adaptive delay tPDH(HDRV).
Low-Side Driver
The low-side driver (LDRV) is designed to drive a ground
referenced low RDS(ON) N-channel MOSFET. The bias for LDRV
is internally connected between VCIN and CGND. When the
driver is enabled, the driver's output is 180° out of phase with
the PWM input. When the driver is disabled (DISB = 0V), LDRV
is held low.
To preclude overlap during the high-to-low transition (Q1 OFF to
Q2 ON), the adaptive circuitry monitors the voltage at the SW
pin. When the PWM signal goes LOW, Q1 will begin to turn OFF
after some propagation delay (tPDL(HDRV)). Once the VSWH pin
falls below ~2.2V, Q2 begins to turn ON after adaptive delay
tpdh(LDRV).
High-Side Driver
The high-side driver (HDRV) is designed to drive a floating
N-channel MOSFET. The bias voltage for the high-side driver is
developed by a bootstrap supply circuit, consisting of the
internal diode and external bootstrap capacitor (CBOOT). During
start-up, VSWH is held at PGND, allowing CBOOT to charge to
VCIN through the internal diode. When the PWM input goes
high, HDRV will begin to charge the high-side MOSFET's gate
(Q1). During this transition, charge is removed from CBOOT and
delivered to Q1's gate. As Q1 turns on, VSWH rises to VIN,
forcing the BOOT pin to VIN +VC(BOOT), which provides
sufficient VGS enhancement for Q1. To complete the switching
cycle, Q1 is turned off by pulling HDRV to VSWH. CBOOT is then
recharged to VCIN when VSWH falls to PGND. HDRV output is
in phase with the PWM input. When the driver is disabled, the
high-side gate is held low.
Additionally, VGS of Q1 is monitored. When VGS(Q1) is
discharged below ~1.2V, a secondary adaptive delay is initiated,
which results in Q2 being driven ON after tPDH(LDRV), regardless
of SW state. This function is implemented to ensure CBOOT is
recharged each switching cycle, particularly for cases where the
power convertor is sinking current and SW voltage does not fall
below the 2.2V adaptive threshold. Secondary delay tPDH(HDRV)
is longer than tPDH(LDRV).
VIH(DISB)
DISB
VIL(DISB)
tPDH(DISB)
tPDL(DISB)
LDRV / HDRV
Figure 24. Output Disable Timing
VIH(PWM)
PWM
VIL(PWM)
tPDL(LDRV)
LDRV
1.2V
tPDH(HDRV)
HDRV-SW
tPDL(HDRV)
tPDH(LDRV)
SW
2.2V
Figure 25. Adaptive Gate Drive Timing
FDMF6700 Rev. B
9
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FDMF6700 Driver plus FET Multi-chip Module
Description of Operation
FDMF6700 Driver plus FET Multi-chip Module
Typical Application
VCIN 12V
VIN 12V
VCIN DISB
PWM
BOOT
VIN FDMF6700 VSWH
CGND
PGND
HDRV LDRV
VCC
PWM1
PWM
PWM2
Controller PWM3
PWM4
LDRV
EN
Signal
GND
Power
GND
VCIN DISB
BOOT
PWM
VIN FDMF6700 VSWH
CGND
PGND
HDRV LDRV
VCIN DISB
PWM
BOOT
VIN FDMF6700 VSWH
CGND
PGND
HDRV LDRV
VOUT
VCIN DISB
PWM
BOOT
VIN FDMF6700 VSWH
CGND
PGND
HDRV LDRV
Figure 26. Typical Application
Application Information
Supply Capacitor Selection
For the supply input (VCIN) of the FDMF6700, a local ceramic
bypass capacitor is recommended to reduce the noise and to
supply the peak current. Use at least a 1µF, X7R or X5R capacitor. Keep this capacitor close to the FDMF6700 VCIN and
CGND pins.
The average diode forward current, IF(AVG), can be estimated
by:
Bootstrap Circuit
where fSW is the switching frequency of the controller. The peak
surge current rating of the internal diode should be checked
in-circuit, since this is dependent on the equivalent impedance
of the entire bootstrap circuit, including the PCB traces. For
applications requiring higher IF, an external diode may be used
in parallel to the internal diode.
IF(AVG) = QG x fSW
The bootstrap circuit uses a charge storage capacitor (CBOOT)
and the internal diode, as shown in Figure 26. Selection of
these components should be done after the high-side MOSFET
has been chosen. The required capacitance is determined
using the following equation:
CBOOT >=
QG
∆VBOOT
(2)
(1)
where QG is the total gate charge of the high-side MOSFET,
and ∆VBOOT is the voltage droop allowed on the high-side
MOSFET drive. For example, the QG of the internal high-side
MOSFET is about 21nC @ 12VGS. For an allowed droop of
~300mV, the required bootstrap capacitance is > 100nF. A good
quality ceramic capacitor must be used.
FDMF6700 Rev. B
10
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1. Input bypass capacitors should be close to VIN and GND pin
of FDMF6700 to help reduce input current ripple component
induced by switching operation.
Refer to Figure 27 for module power loss testing method. Power
loss calculation are as follows:
(a) PIN
= (VIN x IIN) + (VCIN x ICIN) (W)
(b) POUT
= VO x IOUT (W)
(c) PLOSS
= PIN - POUT (W)
2. It is critical that the VSWH copper has minimum area for
lower switching noise emission. VSWH copper trace should
also be wide enough for high current flow. Other signal routing
path, such as PWM IN and BOOT signal, should be considered
with care to avoid noise pickup from VSWH copper area.
3. Output inductor location should be as close as possible to the
FDMF6700 for lower power loss due to copper trace.
PCB Layout Guideline
4. Place ceramic bypass capacitor and boot capacitor as close
to VCIN and BOOT pin of FDMF6700 in order to supply stable
power. Routing width and length should also be considered.
Figure 28. shows a proper layout example of FDMF6700 and
critical parts. All of high current flow path, such as VIN, VSWH,
VOUT and GND copper, should be short and wide for better and
stable current flow, heat radiation and system performance.
5. Use multiple Vias on each copper area to interconnect each
top, inner and bottom layer to help smooth current flow and heat
conduction. Vias should be relatively large and of reasonable
inductance.
Following is a guideline which the PCB designer should
consider:
DISB
CBOOT
PWM input
PWM
ICIN
VCIN
A
DISB
BOOT
FDMF6700
VSWH
VCIN
IIN
VIN
A
CVIN
VIN
IOUT
L
CVCIN
A
V VO
CGND
PGND
IC Ground
Power Ground
VOUT
COUT
Figure 27. Power Loss Measurement Block Diagram
Figure 28. Typical PCB Layout Example (Top View)
FDMF6700 Rev. B
11
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FDMF6700 Driver plus FET Multi-chip Module
Module Power Loss Measurement and
Calculation
FDMF6700 Driver plus FET Multi-chip Module
Dimensional Outline and Pad layout
FDMF6700 Rev. B
12
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HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
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As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I28
© 2007 Fairchild Semiconductor Corporation
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