FDMF6707C

FDMF6707C - Extra-Small, High-Performance, HighFrequency DrMOS Module Benefits Description  Ultra-Compact 6x6mm PQFN, 72% Space-Saving Compared to Conventional Discrete Solutions    Fully Optimized System Efficiency The XS™ DrMOS family is Fairchild’s next-generation, fully optimized, integrated MOSFET plus driver power stage solution for high-current, high-frequency, synchronous buck DC-DC applications. The FDMF6707C integrates a driver IC, two power MOSFETs, and a bootstrap Schottky diode into a thermally enhanced, ultra-compact 6x6 mm PQFN package. Clean Switching Waveforms with Minimal Ringing High-Current Handling Features With an integrated approach, the complete switching power stage is optimized for driver and MOSFET dynamic performance, system inductance, and power MOSFET RDS(ON). XS™ DrMOS uses Fairchild's highperformance PowerTrench® MOSFET technology, which dramatically reduces switch ringing, eliminating the snubber circuit in most buck converter applications.       Over 93% Peak-Efficiency   Driver Output Disable Function (DISB# Pin)  Fairchild PowerTrench® Technology MOSFETs for Clean Voltage Waveforms and Reduced Ringing Applications  Fairchild SyncFET™ (Integrated Schottky Diode) Technology in the Low-Side MOSFET High-Performance Gaming Motherboards   Integrated Bootstrap Schottky Diode   Adaptive Gate Drive Timing for Shoot-Through Protection       Desktop Computers, V-Core and Non-V-Core DC-DC Converters Under-Voltage Lockout (UVLO)   Workstations  Networking and Telecom Microprocessor Voltage Regulators  Small Form-Factor Voltage Regulator Modules High-Current Handling of 50 A High-Performance PQFN Copper-Clip Package 3-State 5.0 V PWM Input Driver Skip-Mode SMOD# (Low-Side Gate Turn Off) Input Thermal Warning Flag for Over-Temperature Condition Internal Pull-Up and Pull-Down for SMOD# and DISB# Inputs, Respectively Optimized for Switching Frequencies up to 1MHz A new driver IC with reduced dead times and propagation delays further enhances performance. A thermal warning function indicates potential overtemperature situations. FDMF6707C also incorporates features such as Skip Mode (SMOD) for improved lightload efficiency, along with a three-state 5 V PWM input for compatibility with a wide range of PWM controllers. Low-Profile SMD Package Fairchild Green Packaging and RoHS Compliance ® Based on the Intel 4.0 DrMOS Standard Compact Blade Servers, V-Core and Non-V-Core DC-DC Converters High-Current DC-DC Point-of-Load (POL) Converters Ordering Information Part Number Current Rating Package Top Mark FDMF6707C 50 A 40-Lead, Clipbond PQFN DrMOS, 6.0mm x 6.0 mm Package FDMF6707C © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.2 www.fairchildsemi.com FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module April 2013 Figure 1. Typical Application Circuit DrMOS Block Diagram VDRV VIN BOOT UVLO VCIN Q1 HS Power MOSFET DBoot DISB# GH Logic GH Level Shift 10µA 30kΩ FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module Typical Application Circuit PHASE VCIN Dead-Time RUP_PWM Input 3-State Logic PWM Control VSWH VDRV RDN_PWM GL GL Logic THWN# VCIN 30kΩ Temp. Sense Q2 LS Power MOSFET 10µA CGND Figure 2. © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.2 PGND SMOD# DrMOS Block Diagram www.fairchildsemi.com 2 Figure 3. Bottom View Figure 4. Top View Pin Definitions Pin # 1 Name Description When SMOD#=HIGH, the low-side driver is the inverse of PWM input. When SMOD#=LOW, SMOD# the low-side driver is disabled. This pin has a 10 µA internal pull-up current source. Do not add a noise filter capacitor. 2 VCIN IC bias supply. Minimum 1 µF ceramic capacitor is recommended from this pin to CGND. 3 VDRV Power for gate driver. Minimum 1 µF ceramic capacitor is recommended, connected as close as possible from this pin to CGND. 4 BOOT Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a bootstrap capacitor from this pin to PHASE. 5, 37, 41 CGND IC ground. Ground return for driver IC. 6 GH 7 FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module Pin Configuration For manufacturing test only. This pin must float; must not be connected to any pin. PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin. 8 NC No connect. The pin is not electrically connected internally, but can be connected to VIN for convenience. 9 - 14, 42 VIN Power input. Output stage supply voltage. 15, 29 35, 43 VSWH Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point for the adaptive shoot-through protection. 16 – 28 PGND Power ground. Output stage ground. Source pin of the low-side MOSFET. 36 GL 38 THWN# 39 DISB# Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are held LOW). This pin has a 10µA internal pull-down current source. Do not add a noise filter capacitor. 40 PWM PWM signal input. This pin accepts a three-state 5V PWM signal from the controller. For manufacturing test only. This pin must float; must not be connected to any pin. Thermal warning flag, open collector output. When temperature exceeds the trip limit, the output is pulled LOW. THWN# does not disable the module. © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.2 www.fairchildsemi.com 3 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit VCIN Supply Voltage Referenced to CGND -0.3 6.0 V VDRV Drive Voltage Referenced to CGND -0.3 6.0 V VDISB# Output Disable Referenced to CGND -0.3 6.0 V VPWM PWM Signal Input Referenced to CGND -0.3 6.0 V VSMOD# VGL VTHWN# VIN VBOOT Skip Mode Input Referenced to CGND -0.3 6.0 V Low Gate Manufacturing Test Pin Referenced to CGND -0.3 6.0 V Thermal Warning Flag Referenced to CGND -0.3 6.0 V Power Input Referenced to PGND, CGND -0.3 25.0 V Referenced to VSWH, PHASE -0.3 6.0 V Referenced to CGND -0.3 25.0 V Referenced to VSWH, PHASE -0.3 6.0 V Referenced to CGND -0.3 25.0 V Bootstrap Supply VGH High Gate Manufacturing Test Pin VPHS PHASE Referenced to CGND -0.3 25.0 V Referenced to PGND, CGND (DC Only) -0.3 25.0 V Referenced to PGND, VIH_DISB). Table 1. Exiting Three-State Condition When exiting a valid three-state condition, the FDMF6707C design follows the PWM input command. If the PWM input goes from three-state to LOW, the lowside MOSFET is turned on. If the PWM input goes from three-state to HIGH, the high-side MOSFET is turned on, as illustrated in Figure 25. The FDMF6707C design allows for short propagation delays when exiting the three-state window (see Electrical Characteristics). UVLO and Disable Logic UVLO DISB# Driver State 0 X Disabled (GH, GL=0) 1 0 Disabled (GH, GL=0) 1 1 Enabled (See Table 2) 1 Open Disabled (GH, GL=0) Low-Side Driver The low-side driver (GL) is designed to drive a groundreferenced low RDS(ON) N-channel MOSFET. The bias for GL is internally connected between VDRV and CGND. When the driver is enabled, the driver's output is 180° out of phase with the PWM input. When the driver is disabled (DISB#=0 V), GL is held LOW. Note: 3. DISB# internal pull-down current source is 10 µA. Thermal Warning Flag (THWN#) The FDMF6707C provides a thermal warning flag (THWN#) to advise of over-temperature conditions. The thermal warning flag uses an open-drain output that pulls to CGND when the activation temperature (150°C) is reached. The THWN# output returns to highimpedance state once the temperature falls to the reset temperature (135°C). The THWN# output requires a pull-up resistor, which can be connected to VCIN. THWN# does NOT disable the DrMOS module. HIGH THWN# Logic State High-Side Driver The high-side driver is designed to drive a floating N-channel MOSFET. The bias voltage for the high-side driver is developed by a bootstrap supply circuit consisting of the internal Schottky diode and external bootstrap capacitor (CBOOT). During startup, VSWH is held at PGND, allowing CBOOT to charge to VDRV through the internal diode. When the PWM input goes HIGH, GH begins to charge the gate of the high-side MOSFET (Q1). During this transition, the charge is removed from CBOOT and delivered to the gate of Q1. As Q1 turns on, VSWH rises to VIN, forcing the BOOT pin to VIN + VBOOT, which provides sufficient VGS enhancement for Q1. To complete the switching cycle, Q1 is turned off by pulling GH to VSWH. CBOOT is then recharged to VDRV when VSWH falls to PGND. GH output is in-phase with the PWM input. The high-side gate is held LOW when the driver is disabled or the PWM signal is held within the three-state window for longer than the three-state hold-off time, tD_HOLD-OFF. 135°C Reset 150°C Temperature Activation Temperature Normal Operation Thermal Warning LOW TJ_driver IC Figure 24. FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module Functional Description THWN Operation © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.2 www.fairchildsemi.com 11 The driver IC design ensures minimum MOSFET dead time, while eliminating potential shoot-through (crossconduction) currents. It senses the state of the MOSFETs and adjusts the gate drive adaptively to prevent simultaneous conduction. Figure 25 provides the timing waveforms. To prevent overlap during the LOW-to-HIGH switching transition (Q2 off to Q1 on), the adaptive circuitry monitors the voltage at the GL pin. When the PWM signal goes HIGH, Q2 turns off after a propagation delay (tPD_PHGLL). Once the GL pin is discharged below ~1 V, Q1 turns on after adaptive delay, tD_DEADON. V IH_PWM To prevent overlap during the HIGH-to-LOW transition (Q1 off to Q2 on), the adaptive circuitry monitors the voltage at the VSWH pin. When the PWM signal goes LOW, Q1 turns off after a propagation delay (tPD_PLGHL). Once the VSWH pin falls below ~2.2 V, Q2 turns on after adaptive delay, tD_DEADOFF. Additionally, VGS(Q1) is monitored. When VGS(Q1) is discharged below ~1.2 V, a secondary adaptive delay is initiated that results in Q2 being driven on after tD_TIMEOUT, regardless of VSWH state. This function ensures CBOOT is recharged each switching cycle in the event that the VSWH voltage does not fall below the 2.2 V adaptive threshold. Secondary delay tD_TIMEOUT is longer than tD_DEADOFF. V IH_PWM V IH_PWM V IH PWM V TRI_HI V TRI_HI V TRI_LO V IL_PWM V IL_PWM tR_GH PWM less than t D_HOLD - OFF GH to VSWH tF_GH 90% tD_HOLD -OFF 10% V IN CCM DCM DCM V OUT 2.2V VSWH GL 90% 90% 1.0V tPD_PHGLL tD_DEADON 10% 10% tPD_PLGHL tR_GL tF_GL tD_DEADOFF tPD_TSGHH Enter 3-State tD_HOLD -OFF Enter 3 -State Exit 3-State tPD_TSGHH Exit 3 State less than t D_HOLD - OFF tD_HOLD-OFF tPD_TSGLH Enter 3 -State FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module Adaptive Gate Drive Circuit Exit 3-State Notes: tPD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal. Example (tPD_PHGLL – PWM going HIGH to LS VGS (GL) going LOW) tD_xxx = delay from IC generated signal to IC generated signal. Example (tD_DEADON – LS VGS (GL) LOW to HS VGS (GH) HIGH) PWM tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (SMOD# held LOW) Exiting 3-state tPD_TSGHH = PWM 3-state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS tPD_TSGLH = PWM 3-state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS SMOD# tPD_SLGLL = SMOD# fall to LS VGS fall, VIL_SMOD to 90% LS VGS tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS Dead Times tD_DEADON = LS VGS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS tD_DEADOFF = VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS Figure 25. © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.2 PWM and 3-StateTiming Diagram www.fairchildsemi.com 12 The SMOD function allows higher converter efficiency under light-load conditions. During SMOD, the low-side FET gate signal is disabled (held LOW), preventing discharging of the output capacitors as the filter inductor current attempts reverse current flow – also known as Diode Emulation Mode. Table 2. When the SMOD# pin is pulled HIGH, the synchronous buck converter works in Synchronous Mode. This mode allows for gating on the low-side FET. When the SMOD# pin is pulled LOW, the low-side FET is gated off. If the SMOD# pin is connected to the PWM controller, the controller can actively enable or disable SMOD when the controller detects light-load condition from output current sensing. This pin is active LOW. See Figure 26 for timing delays. SMOD Logic DISB# PWM SMOD# GH GL 0 X X 0 0 1 3-State X 0 0 1 0 0 0 0 1 1 0 1 0 1 0 1 0 1 1 1 1 1 0 Note: 4. The SMOD feature is intended to have low propagation delay between the SMOD signal and the low-side FET VGS response time to control diode emulation on a cycle-by-cycle basis. SMOD# V IH_SMOD V IL_SMOD V IH_PWM V IH_PWM V IL_PWM PWM 90% GH to VSWH 10% 10% DCM V OUT CCM CCM 2.2V VSWH GL 90% 1.0V tPD_PHGLL tD_DEADON 10% FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module Skip Mode (SMOD) 10% tPD_PLGHL tPD_PHGHH tPD_SLGLL tD_DEADOFF Delay from SMOD# going LOW to LS VGS LOW tPD_SHGLH Delay from SMOD# going HIGH to LS V GS HIGH HS turn -on with SMOD# LOW Figure 26. © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.2 SMOD Timing Diagram www.fairchildsemi.com 13 Supply Capacitor Selection VCIN Filter For the supply inputs (VDRV and VCIN), a local ceramic bypass capacitor is required to reduce noise and to supply peak transient currents during gate drive switching action. It is recommended to use a minimum capacitor value of 1 µF X7R or X5R. Keep this capacitor close to the VCIN and VDRV pins and connect it to the GND plane with vias. The VDRV pin provides power to the gate drive of the high-side and low-side power MOSFETs. In most cases, VDRV can be connected directly to VCIN, which supplies power to the logic circuitry of the gate driver. For additional noise immunity, an RC filter can be inserted between VDRV and VCIN. Recommended values would be 10 Ω (RVCIN) placed between VDRV and VCIN and 1 µF (CVCIN) from VCIN to CGND (see Figure 27). Bootstrap Circuit Power Loss and Efficiency The bootstrap circuit uses a charge storage capacitor (CBOOT), as shown in Figure 27. A bootstrap capacitance of 100 nF X7R or X5R capacitor is typically adequate. A series bootstrap resistor may be needed for specific applications to improve switching noise immunity. The boot resistor may be required when operating near the maximum rated VIN and is effective at controlling the high-side MOSFET turn-on slew rate and VSHW overshoot. Typical RBOOT values from 0.5 Ω to 2.0 Ω are effective in reducing VSWH overshoot. Figure 27. Figure 28. © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.2 Measurement and Calculation Refer to Figure 28 for power loss testing method. Power loss calculations are: PIN=(VIN x IIN) + (V5V x I5V) (W) PSW=VSW x IOUT (W) POUT=VOUT x IOUT (W) PLOSS_MODULE=PIN - PSW (W) PLOSS_BOARD=PIN - POUT (W) EFFMODULE=100 x PSW/PIN (%) EFFBOARD=100 x POUT/PIN (%) (1) (2) (3) (4) (5) (6) (7) FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module Application Information Block Diagram With VCIN Filter Power Loss Measurement www.fairchildsemi.com 14 boot capacitor (CBOOT) and DrMOS BOOT pin. The BOOT-to-VSWH loop size, including RBOOT and CBOOT, should be as small as possible. The boot resistor may be required when operating near the maximum rated VIN. The boot resistor is effective at controlling the high-side MOSFET turn-on slew rate and VSHW overshoot. RBOOT can improve noise operating margin in synchronous buck designs that may have noise issues due to ground bounce or high positive and negative VSWH ringing. However, inserting a boot resistance lowers the DrMOS efficiency. Efficiency versus noise trade-offs must be considered. RBOOT values from 0.5 Ω to 2.0 Ω are typically effective in reducing VSWH overshoot. Figure 29 provides an example of a proper layout for the FDMF6707C and critical components. All of the highcurrent paths, such as VIN, VSWH, VOUT, and GND copper, should be short and wide for low inductance and resistance. This technique achieves a more stable and evenly distributed current flow, along with enhanced heat radiation and system performance. The following guidelines are recommendations for the PCB designer: 1. Input ceramic bypass capacitors must be placed close to the VIN and PGND pins. This helps reduce the high-current power loop inductance and the input current ripple induced by the power MOSFET switching operation. The VIN and PGND pins handle large current transients with frequency components greater than 100 MHz. If possible, these pins should be connected directly to the VIN and board GND planes. The use of thermal relief traces in series with these pins is discouraged since this adds inductance to the power path. Added inductance in series with the VIN or PGND pin degrades system noise immunity by increasing positive and negative VSWH ringing. 2. The VSWH copper trace serves two purposes. In addition to being the high-frequency current path from the DrMOS package to the output inductor, it also serves as a heat sink for the low-side MOSFET in the DrMOS package. The trace should be short and wide enough to present a low-impedance path for the high-frequency, high-current flow between the DrMOS and inductor to minimize losses and temperature rise. Note that the VSWH node is a high-voltage and high-frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. Since this copper trace also acts as a heat sink for the lower FET, balance using the largest area possible to improve DrMOS cooling while maintaining acceptable noise emission. 8. CGND pad and PGND pins should be connected to the GND plane copper with multiple vias for stable grounding. Poor grounding can create a noise transient offset voltage level between CGND and PGND. This could lead to faulty operation of the gate driver and MOSFETs. 9. Ringing at the BOOT pin is most effectively controlled by close placement of the boot capacitor. Do not add an additional BOOT to PGND capacitor: this may lead to excess current flow through the BOOT diode. 3. An output inductor should be located close to the FDMF6707C to minimize the power loss due to the VSWH copper trace. Care should also be taken so the inductor dissipation does not heat the DrMOS. 4. PowerTrench® MOSFETs are used in the output stage. The power MOSFETs are effective at minimizing ringing due to fast switching. In most cases, no VSWH snubber is required. If a snubber is used, it should be placed close to the VSWH and PGND pins. The resistor and capacitor need to be of proper size for the power dissipation. 10. The SMOD# and DISB# pins have weak internal pull-up and pull-down current sources, respectively. These pins should not have any noise filter capacitors. Do not to float these pins unless absolutely necessary. 11. Use multiple vias on each copper area to interconnect top, inner, and bottom layers to help distribute current flow and heat conduction. Vias should be relatively large and of reasonably low inductance. Critical high-frequency components, such as RBOOT, CBOOT, the RC snubber, and bypass capacitors should be located as close to the respective DrMOS module pins as possible on the top layer of the PCB. If this is not feasible, they should be connected from the backside through a network of low-inductance vias. 5. VCIN, VDRV, and BOOT capacitors should be placed as close as possible to the VCIN to CGND, VDRV to CGND, and BOOT to PHASE pins to ensure clean and stable power. Routing width and length should be considered. 6. Include a trace from PHASE to VSWH to improve noise margin. Keep the trace as short as possible. 7. The layout should include a placeholder to insert a small-value series boot resistor (RBOOT) between the © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.2 FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module PCB Layout Guidelines www.fairchildsemi.com 15 Bottom View Figure 29. © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.2 PCB Layout Example FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module Top View www.fairchildsemi.com 16 FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module Physical Dimensions B 0.10 C PIN#1 INDICATOR 6.00 2X 5.80 A 4.50 30 21 31 6.00 20 0.40 2.50 0.65 0.25 1.60 0.10 C 11 40 2X 1 SEE 0.60 DETAIL 'A' 0.50 TYP TOP VIEW 10 0.35 0.15 2.10 0.40 21 FRONT VIEW 4.40±0.10 (2.20) 0.10 C A B 0.05 C 0.30 30 0.20 (40X) 31 20 0.50 PIN #1 INDICATOR 0.20 MAY APPEAR AS OPTIONAL 2.40±0.10 (0.70) 1.50±0.10 11 10 0.40 2.00±0.10 (0.20) 0.50 (40X) 0.30 40 1 2.00±0.10 0.50 NOTES: UNLESS OTHERWISE SPECIFIED (0.20) BOTTOM VIEW A) DOES NOT FULLY CONFORM TO JEDEC REGISTRATION MO-220, DATED MAY/2005. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. E) DRAWING FILE NAME: PQFN40AREV3 1.10 0.90 0.10 C 0.08 C 0.30 0.20 2.10 LAND PATTERN RECOMMENDATION 0.05 0.00 DETAIL 'A' C SEATING PLANE SCALE: 2:1 Figure 30. 40-Lead, Clipbond PQFN DrMOS, 6.0x6.0 mm Package Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.2 www.fairchildsemi.com 17 FDMF6707C - Extra-Small High-Performance, High-Frequency DrMOS Module © 2011 Fairchild Semiconductor Corporation FDMF6707C • Rev. 1.0.2 www.fairchildsemi.com 18