FDMF6824B — Extra-Small, High-Performance,
High-Frequency DrMOS Module
Benefits
Description
Ultra-Compact 6x6 mm PQFN, 72% Space-Saving
Compared to Conventional Discrete Solutions
Fully Optimized System Efficiency
The XS™ DrMOS family is Fairchild’s next-generation,
fully optimized, ultra-compact, integrated MOSFET plus
driver power stage solution for high-current, highfrequency, synchronous buck DC-DC applications. The
FDMF6824B integrates a driver IC, two power
MOSFETs, and a bootstrap Schottky diode into a
thermally enhanced, ultra-compact 6x6mm package.
Clean Switching Waveforms with Minimal Ringing
High-Current Handling
Features
With an integrated approach, the complete switching
power stage is optimized with regard to driver and
MOSFET dynamic performance, system inductance,
and power MOSFET RDS(ON). XS™ DrMOS uses
Fairchild's high-performance PowerTrench® MOSFET
technology, which dramatically reduces switch ringing,
eliminating the need for snubber circuit in most buck
converter applications.
Over 93% Peak-Efficiency
Driver Output Disable Function (DISB# Pin)
Internal Pull-Up and Pull-Down for SMOD# and
DISB# Inputs, Respectively
A driver IC with reduced dead times and propagation
delays further enhances the performance. A thermal
warning function warns of a potential over-temperature
situation. The FDMF6824B also incorporates a Skip
Mode (SMOD#) for improved light-load efficiency. The
FDMF6824B also provides a 3-state 5 V PWM input for
compatibility with a wide range of PWM controllers.
Fairchild PowerTrench® Technology MOSFETs for
Clean Voltage Waveforms and Reduced Ringing
Applications
Fairchild SyncFET™ (Integrated Schottky Diode)
Technology in Low-Side MOSFET
High-Performance Gaming Motherboards
Integrated Bootstrap Schottky Diode
Adaptive Gate Drive Timing for Shoot-Through
Protection
Desktop Computers, V-Core and Non-V-Core
DC-DC Converters
Under-Voltage Lockout (UVLO)
Workstations
Small Form-Factor Voltage Regulator Modules
High-Current Handling: 55 A
High-Performance PQFN Copper-Clip Package
3-State 5 V PWM Input Driver
Skip-Mode SMOD# (Low-Side Gate Turn Off) Input
Thermal Warning Flag for Over-Temperature
Condition
Optimized for Switching Frequencies up to 1 MHz
Low-Profile SMD Package
Fairchild Green Packaging and RoHS Compliance
Based on the Intel® 4.0 DrMOS Standard
Compact Blade Servers, V-Core and Non-V-Core
DC-DC Converters
High-Current DC-DC Point-of-Load Converters
Networking and Telecom Microprocessor Voltage
Regulators
Ordering Information
Part Number
Current Rating
Package
Top Mark
FDMF6824B
55 A
40-Lead, Clipbond PQFN DrMOS, 6.0 mm x 6.0 mm Package
FDMF6824B
© 2012 Fairchild Semiconductor Corporation
FDMF6824B • Rev. 1.0.1
www.fairchildsemi.com
FDMF6824B — Extra-Small, High-Performance, High-Frequency DrMOS Module
January 2014
VIN
3V ~ 16V
V5V
CVIN
CVDRV
VCIN
VDRV
DISB#
VIN
RBOOT
DISB#
BOOT
PWM Input
CBOOT
PWM
FDMF6824B
OFF
PHASE
SMOD#
ON
VOUT
VSWH
LOUT
Open-Drain
Output
THWN#
COUT
PGND
CGND
Figure 1.
Typical Application Circuit
DrMOS Block Diagram
VDRV
BOOT
VIN
UVLO
VCIN
Q1
HS Power
MOSFET
DBoot
DISB#
GH
Level-Shift
GH
Logic
10µA
30k
PHASE
VCIN
FDMF6824B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Typical Application Circuit
Dead-Time
RUP_PWM
Input
3-State
Logic
PWM
Control
VSWH
VDRV
RDN_PWM
GL
GL
Logic
THWN#
VCIN
30k
Temp.
Sense
Q2
LS Power
MOSFET
10µA
CGND
Figure 2.
© 2012 Fairchild Semiconductor Corporation
FDMF6824B • Rev. 1.0.1
PGND
SMOD#
DrMOS Block Diagram
www.fairchildsemi.com
2
GH
PHASE
NC
VIN
VIN
PGND
PGND
PGND
PGND
26
Figure 4.
27
28
29
30
40
CGND
PGND
25
39
BOOT
PGND
24
38
VDRV
PGND
23
DISB#
THWN#
37
VCIN
PGND
22
PWM
CGND
36
SMOD#
Bottom View
21
VSWH
21
VSWH
22
VSWH
43
PGND
23
CGND
41
PGND
24
VIN
42
PGND
Figure 3.
25
1
PGND
26
2
PGND
27
3
PGND
28
4
PGND
29
5
PGND
30
VSWH
PGND
VSWH
VSWH
6
GL
35
20
PGND
7
VSWH
34
19
PGND
VSWH
8
VSWH
33
PGND
PGND
9
VSWH
32
PGND
VSWH
10
VSWH
31
11
12
13
14
15
16
17
PGND
18
PGND
19
PGND
20
PGND
SMOD#
VSWH
VCIN
VSWH
VDRV
VIN
BOOT
VIN
CGND
VIN
31
VIN
32
VIN
33
VSWH
43
VIN
18
VIN
42
VIN
17
34
CGND
41
VIN
GH
10
PHASE
9
NC
8
VIN
7
16
35
VSWH
6
15
36
VSWH
5
14
37
GL
4
13
38
CGND
3
12
39
THWN#
2
11
40
DISB#
1
VIN
PWM
VSWH
Top View
Pin Definitions
Pin #
1
Name
Description
When SMOD#=HIGH, the low-side driver is the inverse of the PWM input. When
SMOD# SMOD#=LOW, the low-side driver is disabled. This pin has a 10 µA internal pull-up current
source. Do not add a noise filter capacitor.
2
VCIN
IC bias supply. Minimum 1 µF ceramic capacitor is recommended from this pin to CGND.
3
VDRV
Power for the gate driver. Minimum 1µF ceramic capacitor is recommended to be connected as
close as possible from this pin to CGND.
4
BOOT
Bootstrap supply input. Provides voltage supply to the high-side MOSFET driver. Connect a
bootstrap capacitor from this pin to PHASE.
5, 37, 41
CGND
IC ground. Ground return for driver IC.
6
GH
7
FDMF6824B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Pin Configuration
For manufacturing test only. This pin must float; it must not be connected to any pin.
PHASE Switch node pin for bootstrap capacitor routing. Electrically shorted to VSWH pin.
8
NC
No connect. The pin is not electrically connected internally, but can be connected to VIN for
convenience.
9 - 14, 42
VIN
Power input. Output stage supply voltage.
15, 29 35, 43
VSWH
Switch node input. Provides return for high-side bootstrapped driver and acts as a sense point
for the adaptive shoot-through protection.
16 – 28
PGND
Power ground. Output stage ground. Source pin of the low-side MOSFET.
36
GL
38
THWN#
39
DISB#
Output disable. When LOW, this pin disables the power MOSFET switching (GH and GL are
held LOW). This pin has a 10 µA internal pull-down current source. Do not add a noise filter
capacitor.
40
PWM
PWM signal input. This pin accepts a three-state 5 V PWM signal from the controller.
For manufacturing test only. This pin must float; it must not be connected to any pin.
Thermal warning flag, open collector output. When temperature exceeds the trip limit, the
output is pulled LOW. THWN# does not disable the module.
© 2012 Fairchild Semiconductor Corporation
FDMF6824B • Rev. 1.0.1
www.fairchildsemi.com
3
Stresses exceeding the Absolute Maximum Ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
Max.
Unit
VCIN
Supply Voltage
Referenced to CGND
-0.3
6.0
V
VDRV
Drive Voltage
Referenced to CGND
-0.3
6.0
V
VDISB#
Output Disable
Referenced to CGND
-0.3
6.0
V
VPWM
PWM Signal Input
Referenced to CGND
-0.3
6.0
V
Skip Mode Input
Referenced to CGND
-0.3
6.0
V
Low Gate Manufacturing Test Pin
Referenced to CGND
-0.3
6.0
V
Thermal Warning Flag
Referenced to CGND
-0.3
6.0
V
Power Input
Referenced to PGND, CGND
-0.3
25.0
V
Referenced to VSWH, PHASE
-0.3
6.0
V
Referenced to CGND
-0.3
25.0
V
Referenced to VSWH, PHASE
-0.3
6.0
V
Referenced to CGND
-0.3
25.0
V
Referenced to CGND
-0.3
25.0
V
Referenced to PGND, CGND (DC Only)
-0.3
25.0
V
Referenced to PGND, VIH_DISB).
Table 1.
Exiting Three-State Condition
When exiting a valid three-state condition, the
FDMF6824B follows the PWM input command. If the
PWM input goes from three-state to LOW, the low-side
MOSFET is turned on. If the PWM input goes from
three-state to HIGH, the high-side MOSFET is turned
on. This is illustrated in Figure 27. The FDMF6824B
design allows for short propagation delays when exiting
the three-state window (see Electrical Characteristics).
UVLO and Disable Logic
UVLO
DISB#
Driver State
0
X
Disabled (GH, GL=0)
1
0
Disabled (GH, GL=0)
1
1
Enabled (see Table 2)
1
Open
Disabled (GH, GL=0)
Low-Side Driver
The low-side driver (GL) is designed to drive a groundreferenced, low-RDS(ON), N-channel MOSFET. The bias
for GL is internally connected between the VDRV and
CGND pins. When the driver is enabled, the driver's
output is 180° out of phase with the PWM input. When
the driver is disabled (DISB#=0 V), GL is held LOW.
Note:
3. DISB# internal pull-down current source is 10 µA.
Thermal Warning Flag (THWN#)
The FDMF6824B provides a thermal warning flag
(THWN#) to warn of over-temperature conditions. The
thermal warning flag uses an open-drain output that
pulls to CGND when the activation temperature (150°C)
is reached. The THWN# output returns to a highimpedance state once the temperature falls to the reset
temperature (135°C). For use, the THWN# output
requires a pull-up resistor, which can be connected to
VCIN. THWN# does NOT disable the DrMOS module.
HIGH
THWN#
Logic
State
High-Side Driver
The high-side driver (GH) is designed to drive a floating
N-channel MOSFET. The bias voltage for the high-side
driver is developed by a bootstrap supply circuit
consisting of the internal Schottky diode and external
bootstrap capacitor (CBOOT). During startup, VSWH is held
at PGND, allowing CBOOT to charge to VDRV through the
internal diode. When the PWM input goes HIGH, GH
begins to charge the gate of the high-side MOSFET (Q1).
During this transition, the charge is removed from CBOOT
and delivered to the gate of Q1. As Q1 turns on, VSWH
rises to VIN, forcing the BOOT pin to VIN + VBOOT, which
provides sufficient VGS enhancement for Q1. To complete
the switching cycle, Q1 is turned off by pulling GH to
VSWH. CBOOT is then recharged to VDRV when VSWH falls to
PGND. GH output is in-phase with the PWM input. The
high-side gate is held LOW when the driver is disabled or
the PWM signal is held within the three-state window for
longer than the three-state hold-off time, tD_HOLD-OFF.
135°C Reset 150°C
Temperature Activation
Temperature
Normal
Operation
Thermal
Warning
LOW
FDMF6824B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Functional Description
TJ_driver IC
Figure 26.
THWN Operation
© 2012 Fairchild Semiconductor Corporation
FDMF6824B • Rev. 1.0.1
www.fairchildsemi.com
12
The driver IC advanced design ensures minimum
MOSFET dead-time, while eliminating potential shootthrough (cross-conduction) currents. It senses the state
of the MOSFETs and adjusts the gate drive adaptively
to ensure they do not conduct simultaneously. Figure 27
provides the relevant timing waveforms. To prevent
overlap during the LOW-to-HIGH switching transition
(Q2 off to Q1 on), the adaptive circuitry monitors the
voltage at the GL pin. When the PWM signal goes
V IH_PWM
To preclude overlap during the HIGH-to-LOW transition
(Q1 off to Q2 on), the adaptive circuitry monitors the
voltage at the GH-to-PHASE pin pair. When the PWM
signal goes LOW, Q1 begins to turn off after a
propagation delay (tPD_PLGHL). Once the voltage across
GH-to-PHASE falls below 2.2 V, Q2 begins to turn on
after adaptive delay tD_DEADOFF.
V IH_PWM
V IH_PWM
V IH_PWM
V TRI_HI
V TRI_HI
tD_HOLD-OFF
V TRI_LO
V IL_PWM
V IL_PWM
tR_GH
PWM
tF_GH
9 0%
GH
to
VSWH
1 0%
V IN
DCM
DCM
CCM
V OUT
2.2V
VSWH
tR_GL
GL
tF_GL
90%
9 0%
1.0V
tPD_PHGLL
tD_DEADON
1 0%
1 0%
tPD_PLGHL
tPD_TSGHH
tD_HOLD-OFF
t PD_TSGHH
tD_HOLD-OFF tPD_TSGLH
tD_DEADOFF
Exit
3 -state
Enter
3 -state
Enter
3 -state
Exit
3 -state
Enter
3 -state
Exit
3 -state
Notes:
tPD_xxx = propagation delay from external signal (PWM, SMOD#, etc.) to IC generated signal.
Example (tPD_PHGLL – PWM going HIGH to LS VGS (GL) going LOW)
tD_xxx = delay from IC generated signal to IC generated signal. Example (tD_DEADON – LS VGS (GL) LOW to HS VGS (GH) HIGH)
PWM
tPD_PHGLL = PWM rise to LS VGS fall, VIH_PWM to 90% LS VGS
tPD_PLGHL = PWM fall to HS VGS fall, VIL_PWM to 90% HS VGS
tPD_PHGHH = PWM rise to HS VGS rise, VIH_PWM to 10% HS VGS (SMOD# held LOW)
Exiting 3-state
tPD_TSGHH = PWM 3-state to HIGH to HS VGS rise, VIH_PWM to 10% HS VGS
tPD_TSGLH = PWM 3-state to LOW to LS VGS rise, VIL_PWM to 10% LS VGS
SMOD#
tPD_SLGLL = SMOD# fall to LS VGS fall, VIL_SMOD to 90% LS VGS
tPD_SHGLH = SMOD# rise to LS VGS rise, VIH_SMOD to 10% LS VGS
Dead Times
tD_DEADON = LS VGS fall to HS VGS rise, LS-comp trip value (~1.0V GL) to 10% HS VGS
tD_DEADOFF = VSWH fall to LS VGS rise, SW-comp trip value (~2.2V VSWH) to 10% LS VGS
Figure 27.
© 2012 Fairchild Semiconductor Corporation
FDMF6824B • Rev. 1.0.1
FDMF6824B — Extra-Small, High-Performance, High-Frequency DrMOS Module
HIGH, Q2 begins to turn off after a propagation delay
(tPD_PHGLL). Once the GL pin is discharged below 1.0 V,
Q1 begins to turn on after adaptive delay tD_DEADON.
Adaptive Gate Drive Circuit
PWM and 3-StateTiming Diagram
www.fairchildsemi.com
13
The Skip Mode function allows for higher converter
efficiency when operated in light-load conditions. When
SMOD# is pulled LOW, the low-side MOSFET gate
signal is disabled (held LOW), preventing discharge of
the output capacitors as the filter inductor current
attempts reverse current flow – known as “Diode
Emulation” Mode.
Table 2.
SMOD# Logic
DISB#
PWM
SMOD#
GH
GL
0
X
X
0
0
1
3-State
X
0
0
1
0
0
0
0
1
1
0
1
0
1
0
1
0
1
1
1
1
1
0
Note:
4. The SMOD# feature is intended to have a short propagation delay between the SMOD# signal and the low-side
FET VGS response time to control diode emulation on a cycle-by-cycle basis.
SMOD#
V IH_SMOD
V IL_SMOD
V IH_PWM
V IH_PWM
V IL_PWM
PWM
90%
GH
to
VSWH
1 0%
1 0%
DCM
V OUT
CCM
CCM
2.2V
FDMF6824B — Extra-Small, High-Performance, High-Frequency DrMOS Module
When the SMOD# pin is pulled HIGH, the synchronous
buck converter works in Synchronous Mode. This mode
allows for gating on the Low Side MOSFET. When the
SMOD# pin is pulled LOW, the low-side MOSFET is
gated off. If the SMOD# pin is connected to the PWM
controller, the controller can actively enable or disable
SMOD# when the controller detects light-load condition
from output current sensing. Normally this pin is active
LOW. See Figure 28 for timing delays.
Skip Mode (SMOD#)
VSWH
GL
90%
1.0V
tPD_PHGLL
tD_DEADON
1 0%
1 0%
tPD_PLGHL
tPD_PHGHH
tPD_SLGLL
tD_DEADOFF
Delay from SMOD# going
LOW to LS VGS LOW
tPD_SHGLH
Delay from SMOD# going
HIGH to LS V GS HIGH
HS turn -on with SMOD# LOW
Figure 28.
© 2012 Fairchild Semiconductor Corporation
FDMF6824B • Rev. 1.0.1
SMOD# Timing Diagram
www.fairchildsemi.com
14
Supply Capacitor Selection
VCIN Filter
For the supply inputs (VCIN), a local ceramic bypass
capacitor is recommended to reduce noise and to
supply the peak current. Use at least a 1 µF X7R or X5R
capacitor. Keep this capacitor close to the VCIN pin and
connect it to the GND plane with vias.
The VDRV pin provides power to the gate drive of the
high-side and low-side power MOSFET. In most cases,
it can be connected directly to VCIN, the pin that
provides power to the logic section of the driver. For
additional noise immunity, an RC filter can be inserted
between the VDRV and VCIN pins. Recommended
values would be 10 Ω and 1 µF.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(CBOOT), as shown in Figure 30. A bootstrap capacitance
of 100 nF X7R or X5R capacitor is usually adequate. A
series bootstrap resistor may be needed for specific
applications to improve switching noise immunity. The
boot resistor may be required when operating above
15 VIN and is effective at controlling the high-side
MOSFET turn-on slew rate and VSHW overshoot. RBOOT
values from 0.5 to 3.0 Ω are typically effective in
reducing VSWH overshoot.
V5V
A
I5V
RVCIN
CVDRV
Power Loss and Efficiency
Measurement and Calculation
Refer to Figure 30 for power loss testing method.
Power loss calculations are:
CVCIN
PIN=(VIN x IIN) + (V5V x I5V) (W)
(1)
PSW=VSW x IOUT (W)
(2)
POUT=VOUT x IOUT (W)
(3)
PLOSS_MODULE=PIN - PSW (W)
(4)
PLOSS_BOARD=PIN - POUT (W)
(5)
EFFMODULE=100 x PSW/PIN (%)
(6)
EFFBOARD=100 x POUT/PIN (%)
(7)
CVIN
A
IIN
VIN
VCIN
VDRV
VIN
DISB#
DISB#
RBOOT
PWM
Input
BOOT
PWM
OFF
FDMF6824B
FDM 67 5
F
CBOOT
0
IOUT
VSWH
SMOD#
ON
Open Drain
Output
A
LOUT
PHASE
THWN#
Figure 29.
V5V
A
I5V
PWM
Input
CVIN
RBOOT
BOOT
PWM
FDMF6824B
FDM
5
CBOOT
IOUT
VSWH
SMOD#
A
LOUT
PHASE
THWN#
CGND
Figure 30.
© 2012 Fairchild Semiconductor Corporation
FDMF6824B • Rev. 1.0.1
VIN
VIN
VCIN
F
OpenDrain
Output
A
IIN
DISB#
OFF
ON
COUT
Block Diagram With VCIN Filter
CVDRV
VDRV
DISB#
VOUT
V VSW
PGND
CGND
FDMF6824B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Application Information
V VSW
PGND
COUT
Power Loss Measurement
www.fairchildsemi.com
15
Figure 31 and Figure 32 provide an example of a proper
layout for the FDMF6824B and critical components. All
of the high-current paths, such as VIN, VSWH, VOUT,
and GND copper, should be short and wide for low
inductance and resistance. This aids in achieving a
more stable and evenly distributed current flow, along
with enhanced heat radiation and system performance.
the high-side MOSFET turn-on slew rate and VSHW
overshoot. RBOOT can improve noise operating
margin in synchronous buck designs that may have
noise issues due to ground bounce or high positive
and negative VSWH ringing. Inserting a boot
resistance lowers the DrMOS efficiency. Efficiency
versus noise trade-offs must be considered. RBOOT
values from 0.5 to 3.0 are typically effective in
reducing VSWH overshoot.
Recommendations for PCB Designers
1. Input ceramic bypass capacitors must be placed
close to the VIN and PGND pins. This helps reduce
the high-current power loop inductance and the input
current ripple induced by the power MOSFET
switching operation.
2. The VSWH copper trace serves two purposes. In
addition to being the high-frequency current path
from the DrMOS package to the output inductor, it
serves as a heat sink for the low-side MOSFET in
the DrMOS package. The trace should be short and
wide enough to present a low-impedance path for
the high-frequency, high-current flow between the
DrMOS and inductor. The short and wide trace
minimizes electrical losses as well as the DrMOS
temperature rise. Note that the VSWH node is a highvoltage and high-frequency switching node with high
noise potential. Care should be taken to minimize
coupling to adjacent traces. Since this copper trace
acts as a heat sink for the lower MOSFET, balance
using the largest area possible to improve DrMOS
cooling while maintaining acceptable noise emission.
8. The VIN and PGND pins handle large current
transients with frequency components greater than
100 MHz. If possible, these pins should be
connected directly to the VIN and board GND
planes. The use of thermal relief traces in series with
these pins is discouraged since this adds inductance
to the power path. This added inductance in series
with either the VIN or PGND pin degrades system
noise immunity by increasing positive and negative
VSWH ringing.
9. GND pad and PGND pins should be connected to
the GND copper plane with multiple vias for stable
grounding. Poor grounding can create a noise
transient offset voltage level between CGND and
PGND. This could lead to faulty operation of the gate
driver and MOSFETs.
10. Ringing at the BOOT pin is most effectively
controlled by close placement of the boot capacitor.
Do not add an additional BOOT to the PGND
capacitor. This may lead to excess current flow
through the BOOT diode.
3. An output inductor should be located close to the
FDMF6824B to minimize the power loss due to the
VSWH copper trace. Care should also be taken so the
inductor dissipation does not heat the DrMOS.
11. The SMOD# and DISB# pins have weak internal
pull-up and pull-down current sources, respectively.
These pins should not have any noise filter
capacitors. Do not to float these pins unless
absolutely necessary.
4. PowerTrench® MOSFETs are used in the output
stage and are effective at minimizing ringing due to
fast switching. In most cases, no VSWH snubber is
required. If a snubber is used, it should be placed
close to the VSWH and PGND pins. The selected
resistor and capacitor need to be the proper size for
power dissipation.
12. Use multiple vias on the VIN and VOUT copper
areas to interconnect top, inner, and bottom layers
to distribute current flow and heat conduction. Do
not put many vias on the VSWH copper to avoid
extra parasitic inductance and noise on the
switching waveform. As long as efficiency and
thermal performance are acceptable, place only
one VSWH copper on the top layer and use no vias
on the VSWH copper to minimize switch node
parasitic noise. Vias should be relatively large and
of reasonably low inductance. Critical highfrequency components, such as RBOOT, CBOOT, RC
snubber, and bypass capacitors; should be located
as close to the respective DrMOS module pins as
possible on the top layer of the PCB. If this is not
feasible, they can be connected from the backside
through a network of low-inductance vias.
5. VCIN, VDRV, and BOOT capacitors should be
placed as close as possible to the VCIN-to-CGND,
VDRV-to-CGND, and BOOT-to-PHASE pin pairs to
ensure clean and stable power. Routing width and
length should be considered as well.
6. Include a trace from the PHASE pin to the VSWH pin
to improve noise margin. Keep this trace as short as
possible.
7. The layout should include the option to insert a
small-value series boot resistor between the boot
capacitor and BOOT pin. The boot-loop size,
including RBOOT and CBOOT, should be as small as
possible. The boot resistor may be required when
operating above 15 VIN and is effective at controlling
© 2012 Fairchild Semiconductor Corporation
FDMF6824B • Rev. 1.0.1
FDMF6824B — Extra-Small, High-Performance, High-Frequency DrMOS Module
PCB Layout Guidelines
www.fairchildsemi.com
16
Figure 32.
© 2012 Fairchild Semiconductor Corporation
FDMF6824B • Rev. 1.0.1
PCB Layout Example (Top View)
FDMF6824B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Figure 31.
PCB Layout Example (Bottom View)
www.fairchildsemi.com
17
FDMF6824B — Extra-Small, High-Performance, High-Frequency DrMOS Module
Physical Dimensions
B
0.10 C
PIN#1
INDICATOR
6.00
2X
5.80
A
4.50
30
21
31
6.00
20
0.40
2.50
0.65
0.25
1.60
0.10 C
11
40
2X
1
SEE 0.60
DETAIL 'A' 0.50 TYP
TOP VIEW
10
0.35
0.15
2.10
0.40 21
FRONT VIEW
4.40±0.10
(2.20)
0.10
C A B
0.05
C
0.30
30 0.20 (40X)
31
20
0.50
PIN #1 INDICATOR
0.20 MAY APPEAR AS
OPTIONAL
2.40±0.10
(0.70)
1.50±0.10
11
10
0.40
2.00±0.10
(0.20)
0.50 (40X)
0.30
40
1
2.00±0.10
0.50
NOTES: UNLESS OTHERWISE SPECIFIED
(0.20)
BOTTOM VIEW
A) DOES NOT FULLY CONFORM TO JEDEC
REGISTRATION MO-220, DATED
MAY/2005.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) DRAWING FILE NAME: PQFN40AREV3
1.10
0.90
0.10 C
0.08 C
0.30
0.20
2.10
LAND PATTERN
RECOMMENDATION
0.05
0.00
DETAIL 'A'
C
SEATING
PLANE
SCALE: 2:1
Figure 33.
40-Lead, Clipbond PQFN DrMOS, 6.0x6.0 mm Package
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/dwg/PQ/PQFN40A.pdf.
© 2012 Fairchild Semiconductor Corporation
FDMF6824B • Rev. 1.0.1
www.fairchildsemi.com
18
FDMF6824B — Extra-Small, High-Performance, High-Frequency DrMOS Module
© 2012 Fairchild Semiconductor Corporation
FDMF6824B • Rev. 1.0.1
www.fairchildsemi.com
19
