FDMS3604S

FDMS3604S MOSFET – N-Channel, POWERTRENCH), Power Stage, Asymetric Dual General Description This device includes two specialized N−Channel MOSFETs in a dual PQFN package. The switch node has been internally connected to enable easy placement and routing of synchronous buck converters. The control MOSFET (Q1) and synchronous SyncFET™ (Q2) have been designed to provide optimal power efficiency. www.onsemi.com G1 D1 D1 D1 D1 PHASE (S1/D2) Features Q1: N−Channel • Max rDS(on) = 8 mW at VGS = 10 V, ID = 13 A • Max rDS(on) = 11 mW at VGS = 4.5 V, ID = 11 A Q2: N−Channel • Max rDS(on) = 2.6 mW at VGS = 10 V, ID = 23 A • Max rDS(on) = 3.5 mW at VGS = 4.5 V, ID = 21 A • Low Inductance Packaging Shortens Rise/Fall Times, Resulting in Lower Switching Losses • MOSFET Integration Enables Optimum Layout for Lower Circuit Inductance and Reduced Switch Node Ringing • This Device is Pb−Free and is RoHS Compliant G2 S2 S2 S2 Top Bottom PQFN8 5x6, 1.27P CASE 483AJ MARKING DIAGRAM $Y&Z&3&K 22CA N7CC Applications • • • • Computing Communications General Purpose Point of Load Notebook VCORE $Y &Z &3 &K 22CA N7CC = ON Semiconductor Logo = Assembly Plant Code = Numeric Date Code = Lot Code = Specific Device Code PIN CONFIGURATION S2 5 S2 6 Q2 PHASE S2 7 G2 8 Q1 4 D1 3 D1 2 D1 1 G1 ORDERING INFORMATION See detailed ordering and shipping information on page 2 of this data sheet. © Semiconductor Components Industries, LLC, 2011 January, 2020 − Rev. 3 1 Publication Order Number: FDMS3604S/D FDMS3604S MOSFET MAXIMUM RATINGS TA = 25°C Unless Otherwise Noted Parameter Symbol Q1 Q2 Units VDS Drain to Source Voltage 30 30 V VDSt Drain to Source Transient Voltage ( tTransient < 100 ns) 33 33 V VGS Gate to Source Voltage (Note 3) ±20 ±20 V ID Drain Current −Continuous (Package limited) TC = 25 °C 30 40 −Continuous (Silicon limited) TC = 25 °C 60 130 −Continuous TA = 25 °C 13 (Note 1a) 23 (Note 1b) 40 100 40 (Note 4) 60 (Note 5) Power Dissipation for Single Operation TA = 25 °C 2.2 (Note 1a) 2.5 (Note 1b) Power Dissipation for Single Operation TA = 25 °C 1.0 (Note 1c) 1.0 (Note 1d) −Pulsed EAS PD TJ, TSTG Single Pulse Avalanche Energy Operating and Storage Junction Temperature Range −55 to +150 A mJ W °C THERMAL CHARACTERISTICS Symbol Parameter Q1 Q2 Unit °C/W RθJA Thermal Resistance, Junction to Ambient 57 (Note 1a) 50 (Note 1b) RθJA Thermal Resistance, Junction to Ambient 125 (Note 1c) 120 (Note 1d) RθJC Thermal Resistance, Junction to Case 3.5 2 PACKAGE MARKING AND ORDERING INFORMATION Device Marking Device Package Reel Size Tape Width Quantity 22CA N7CC FDMS3604S Power 56 13” 12 mm 3000 Units www.onsemi.com 2 FDMS3604S ELECTRICAL CHARACTERISTICS TJ = 25°C Unless Otherwise Noted Parameter Symbol Column Head Test Conditions Type Min 30 30 Typ Max Units OFF CHARACTERISTICS BVDSS Drain to Source Breakdown Voltage ID = 250 mA, VGS = 0 V ID = 1 mA, VGS = 0 V Q1 Q2 V DBVDSS / DTJ Breakdown Voltage Temperature Coefficient ID = 250 mA, referenced to 25°C ID = 10 mA, referenced to 25°C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V Q1 Q2 1 500 mA IGSS Gate to Source Leakage Current, Forwad VGS = 20 V, VDS= 0 V Q1 Q2 100 100 nA 2.7 3 V 15 12 mV/°C ON CHARACTERISTICS VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 mA VGS = VDS, ID = 1 mA Q1 Q2 DVGS(th) / DTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 mA, referenced to 25°C ID = 10 mA, referenced to 25°C Q1 Q2 −6 −5 Drain to Source On Resistance VGS = 10 V, ID = 13 A VGS = 4.5 V, ID = 11 A VGS = 10 V, ID = 13 A , TJ = 125°C Q1 5.8 8.5 7.8 8 11 10.8 VGS = 10 V, ID = 23 A VGS = 4.5 V, ID = 21 A VGS = 10 V, ID = 23 A , TJ = 125°C Q2 2.0 3.0 2.6 2.6 3.5 4 VDS = 5 V, ID = 13 A VDS = 5 V, ID = 23 A Q1 Q2 61 130 Q1: VDS = 15 V, VGS = 0 V, f = 1 MHz Q2: VDS = 15 V, VGS = 0 V, f = 1 MHz Q1 Q2 1340 3240 1785 4310 pF Q1 Q2 485 1230 645 1635 pF 53 103 80 155 pF 0.6 0.8 2 3 W Q1 Q2 8.2 13 16 23 ns Q1 Q2 2.5 4.8 10 10 ns Turn−Off Delay Time Q1 Q2 20 31 32 50 ns Fall Time Q1 Q2 2.2 3.4 10 10 ns Q1 Q2 21 47 29 66 nC Q1 Q2 10 22 14 31 nC rDS(on) gFS Forward Transconductance 1.1 1.1 2 1.8 mV/°C mW S DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Q1 Q2 Gate Resistance Q1 Q2 Rg 0.2 0.2 SWITCHING CHARACTERISTICS td(on) tr td(off) tf Turn−On Delay Time Rise Time Q1: VDD = 15 V, ID = 13 A, RGEN = 6 W Q2: VDD = 15 V, ID = 23 A, RGEN = 6 W Q1 VDD = 15 V, ID = 13 A Q2 VDD = 15 V, ID = 23 A Qg Total Gate Charge VGS = 0 V to 10 V Qg Total Gate Charge VGS = 0 V to 4.5 V Qgs Gate to Source Gate Charge Q1 Q2 3.9 9 nC Qgd Gate to Drain “Miller” Charge Q1 Q2 3.1 5.5 nC www.onsemi.com 3 FDMS3604S ELECTRICAL CHARACTERISTICS TJ = 25°C Unless Otherwise Noted (continued) Symbol Column Head Test Conditions Parameter Type Min Typ Max Units DRAIN−SOURCE DIODE CHARACTERISTICS VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 13 A (Note 2) VGS = 0 V, IS = 23 A (Note 2) Q1 Q2 0.8 0.8 1.2 1.2 V trr Reverse Recovery Time Q1 Q2 25 32 40 51 ns Qrr Reverse Recovery Charge Q1 IF = 13 A, di/dt = 100 A/ms Q2 IF = 23 A, di/dt = 300 A/ms Q1 Q2 9 39 18 62 nC 1. RqJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR−4 material. RqJC is guaranteed by design while RqCA is determined by the user’s board design. b. 50 °C/W when mounted on a 1 in2 pad of 2 oz copper a. 57 °C/W when mounted on a 1 in2 pad of 2 oz copper c. 125 °C/W when mounted on a minimum pad of 2 oz copper 2. 3. 4. 5. d. 120 °C/W when mounted on a minimum pad of 2 oz copper Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%. As an N−ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied. EAS of 40 mJ is based on starting TJ = 25°C; N−ch: L = 1 mH, IAS = 9 A, VDD = 27 V, VGS = 10 V. 100% test at L = 0.3 mH, IAS = 14 A. EAS of 60 mJ is based on starting TJ = 25°C; N−ch: L = 1 mH, IAS = 11 A, VDD = 27 V, VGS = 10 V. 100% test at L = 0.3 mH, IAS = 18 A. www.onsemi.com 4 FDMS3604S TYPICAL CHARACTERISTICS (Q1 N−CHANNEL) TJ = 25°C Unless Otherwise Noted 4 40 NORMALIZED DRAIN TO SOURCE ON−RESISTANCE ID, DRAIN CURRENT (A) VGS = 10 V VGS = 6 V 30 VGS = 4.5 V VGS = 4 V 20 VGS = 3.5 V 10 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 0 0.0 0.2 0.4 0.6 0.8 VGS = 3.5 V PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 3 VGS = 4 V 2 VGS = 4.5 V VGS = 6 V 1 0 1.0 VGS = 10 V 0 10 VDS, DRAIN TO SOURCE VOLTAGE (V) rDS(on) , DRAIN TO 1.2 1.0 0.8 TJ = 125oC 8 4 TJ = 25oC 0 10 0.1 40 1000 10 P( PK) , PEAK TRANSIENT POWER (W) (A) IS, REVERSE DRAIN CURRENT 1 TJ = 150 oC 1 ms TJ = THIS AREA IS LIMITED BY rDS(on) SINGLE PULSE TJ = MAX RATED o RqJA = 125 C/W 25 oC 4 6 8 10 Figure 4. On−Resistance vs Gate to Source Voltage 100 ms VDS = 5 V 2 VGS, GATE TO SOURCE VOLTAGE (V) PULSE DURATION = 80ms DUTY CYCLE = 0.5% MAX 20 D ID, IDRAIN CURRENT (A)(A) , DRAIN CURRENT 10 ID = 13 A 12 Figure 3. Normalized On Resistance vs Junction Temperature 30 PULSE DURATION = 80ms DUTY CYCLE = 0.5% MAX 16 0.6 −75 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) 100 40 20 ID = 13 A VGS = 10 V SOURCE ON−RESISTANCE( mW) NORMALIZED DRAIN TO SOURCE ON−RESISTANCE 1.4 30 Figure 2. Normalized On−Resistance vs Drain Current and Gate Voltage Figure 1. On−Region Characteristics 1.6 20 ID, DRAIN CURRENT (A) 10 ms 100 ms 1s o TJ = −55 10 C s DC 0 T = 25oC 1.5 A 2.0 2.5 3.0 3.5 4.0 0.01 VGS, GATE TO SOURCE VOLTAGE (V) 0.01 0.1 1 10 100 200 VGS = 0 V SINGLE PULSE RqJA = 1255C/W 100 1 TA = 255C TJ = 150 oC TJ = 25 oC 0.1 10 0.01 1 0.001 0.0 0.1 −4 10 TJ = −55oC 0.2 0.4 0.6 0.8 1.0 VSD FORWARD VOLTAGE100 (V) −3, BODY −2DIODE−1 10 10 10 1 10 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current www.onsemi.com 5 1.2 1000 FDMS3604S TYPICAL CHARACTERISTICS (Q1 N−CHANNEL) TJ = 25°C Unless Otherwise Noted (continued) 2000 ID = 13 A VDD = 10 V 1000 8 VDD = 15 V CAPACITANCE (pF) VGS , GATE TO SOURCE VOLTAGE (V) 10 6 VDD = 20 V 4 Ciss Coss 100 Crss 2 0 f = 1 MHz VGS = 0 V 0 5 10 15 20 10 0.1 25 1 10 30 Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 20 100 o ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) RqJC = 3.5 C/W 10 TJ = 25 oC TJ = 100 oC TJ = 125 oC 1 0.01 0.1 1 80 VGS = 10 V 60 VGS = 4.5 V 40 20 Limited by Package 10 0 25 100 50 P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 150 1000 100 10 1 ms 10 ms THIS AREA IS LIMITED BY rDS(on) 100 ms 1s SINGLE PULSE TJ = MAX RATED 10 s RqJA = 125oC/W 0.01 0.01 125 Figure 10. Maximum Continuous Drain Current vs Case Temperature 100 0.1 100 TC, CASE TEMPERATURE (C) Figure 9. Unclamped Inductive Switching Capability 1 75 o tAV, TIME IN AVALANCHE (ms) DC TA = 25oC 0.1 1 10 100 200 SINGLE PULSE RqJA = 125 oC/W 100 TA = 25 oC 10 1 0.1 −4 10 VDS, DRAIN to SOURCE VOLTAGE (V) −3 10 −2 10 −1 10 1 10 100 1000 t, PULSE WIDTH (sec) Figure 11. Forward Bias Safe Operating Area Figure 12. Single Pulse Maximum Power Dissipation www.onsemi.com 6 FDMS3604S TYPICAL CHARACTERISTICS (Q1 N−CHANNEL) TJ = 25°C Unless Otherwise Noted (continued) 2 NORMALIZED THERMAL IMPEDANCE, ZqJA 1 0.1 DUTY CYCLE−DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t 2 PEAK TJ = PDM x ZqJA x RqJA + TA RqJA = 125 oC/W (Note 1c) 0.001 −4 10 −3 10 −2 10 −1 10 11 0 100 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction−to−Ambient Transient Thermal Response Curve www.onsemi.com 7 1000 FDMS3604S TYPICAL CHARACTERISTICS (Q2 N−CHANNEL) TJ = 25°C Unless Otherwise Noted 100 NORMALIZED DRAIN TO SOURCE ON−RESISTANCE VGS = 4.5 V 80 ID, DRAIN CURRENT (A) 8 VGS = 10 V VGS = 4 V 60 VGS = 3.5 V 40 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 20 0 0.0 VGS = 3 V 0.2 0.4 0.6 0.8 VGS = 3 V 6 VGS = 3.5 V 4 0 1.0 VGS = 10 V 0 20 100 rDS(on) , DRAIN TO 1.4 1.2 1.0 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX SOURCE ON−RESISTANCE(mW) NORMALIZED DRAIN TO SOURCE ON−RESISTANCE 80 12 ID = 23 A VGS = 10 V 9 ID = 23 A 6 TJ = 125 oC 3 TJ = 25 oC 0.8 −75 −50 −25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE o(C) 0 100 IS, REVERSE DRAIN CURRENT (A) VDS = 5 V 60 TJ = 125 oC 40 TJ = 25 oC 20 TJ = −55oC 2.5 3.0 3.5 4 6 8 1 0 Figure 17. On−Resistance vs Gate to Source Voltage PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 2.0 2 VGS, GATE TO SOURCE VOLTAGE (V) Figure 16. Normalized On−Resistance vs Junction Temperature ID, DRAIN CURRENT (A) 60 Figure 15. Normalized On−Resistance vs Drain Current and Gate Voltage 1.6 0 1.5 40 ID, DRAIN CURRENT (A) Figure 14. On−Region Characteristics 80 VGS = 4.5 V VGS = 4 V 2 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 PULSE DURATION = 80 ms DUTY CYCLE = 0.5% MAX 10 TJ = 125 oC 1 TJ = 25 oC 0.1 TJ = −55 oC 0.01 0.001 0.0 4.0 VGS = 0 V 0.2 0.4 0.6 0.8 1.0 1.2 VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 18. Transfer Characteristics Figure 19. Source to Drain Diode Forward Voltage vs Source Current www.onsemi.com 8 FDMS3604S TYPICAL CHARACTERISTICS (Q2 N−CHANNEL) TJ = 25°C Unless Otherwise Noted (continued) 10000 ID = 23 A 8 Ciss VDD = 10 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 6 VDD = 15 V 4 VDD = 20 V 1000 Coss 100 Crss 2 0 f = 1 MHz VGS = 0 V 0 10 20 30 40 10 0.1 50 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 21. Capacitance vs Drain to Source Voltage Figure 20. Gate Charge Characteristics 50 160 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) o RqJC = 2 C/W TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 120 VGS = 10 V 80 VGS = 4.5 V 40 Limited by Package 1 0.01 0.1 1 10 100 0 25 1000 50 150 1000 P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 125 Figure 23. Maximum Continuous Drain Current vs Case Temperature 200 100 1 ms 10 0.1 100 TC, CASE TEMPERATURE (C) Figure 22. Unclamped Inductive Switching Capability 1 75 o tAV, TIME IN AVALANCHE (ms) 10 ms THIS AREA IS LIMITED BY rDS(on) 100 ms 1s SINGLE PULSE TJ = MAX RATED 10s RqJA = 120 oC/W DC TA = 25 oC 0.01 0.01 0.1 1 10 100200 SINGLE PULSE RqJA = 120 oC/W 100 TA = 25 oC 10 1 0.1 −3 10 −2 10 −1 10 1 10 100 1000 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 24. Forward Bias Safe Operating Area Figure 25. Single Pulse Maximum Power Dissipation www.onsemi.com 9 FDMS3604S TYPICAL CHARACTERISTICS (Q2 N−CHANNEL) TJ = 25°C Unless Otherwise Noted (continued) 2 NORMALIZED THERMAL IMPEDANCE, ZqJA 1 0.1 DUTY CYCLE−DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 SINGLE PULSE 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x Z qJA x R qJA + TA R qJA = 120 oC/W (Note 1c) 0.001 −3 10 −2 −1 10 10 1 100 10 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 26. Junction−to−Ambient Transient Thermal Response Curve SyncFET Schottky Body Diode Characteristics ON Semiconductor’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 27 shows the reverse recovery characteristic of the FDMS3604S. Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. 25 −2 CURRENT (A) 20 IDSS, REVERSE LEAKAGE CURRENT (A) 10 didt = 300 A/m s 15 10 5 0 −5 0 50 100 150 200 TJ = 125 oC −3 10 TJ = 100 oC −4 10 −5 10 −6 10 TIME (ns) TJ = 25 oC 0 5 10 15 20 25 30 VDS, REVERSE VOLTAGE (V) Figure 27. FDMS3604S SyncFET Body Diode Reverse Recovery Characteristics Figure 28. SyncFET Body Diode Reverse Leakage versus Drain−source Voltage www.onsemi.com 10 FDMS3604S APPLICATION INFORMATION Switch Node Ringing Suppression ON Semiconductor’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the Figure 29, the Power Stage solution rings significantly less than competitor solutions under the same set of test conditions. Power Stage Device *Patent Pending Competitorrs Solution Figure 29. Power Stage Phase Node Rising Edge, High Turn On Figure 30. Shows the Power Stage in a Buck Converter Topology www.onsemi.com 11 FDMS3604S Recommended PCB Layout Guidelines As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2), should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout procedure is discussed below to maximize the electrical and thermal performance of the part. Figure 31. Recommended PCB Layout Following is a guideline, not a requirement which the PCB designer should consider: 3. Output inductor location should be as close as 1. Input ceramic bypass capacitors C1 and C2 must possible to the Power Stage device for lower be placed close to the D1 and S2 pins of Power power loss due to copper trace resistance. A Stage to help reduce parasitic inductance and High shorter and wider PHASE trace to the inductor Frequency conduction loss induced by switching reduces the conduction loss. Preferably the Power operation. C1 and C2 show the bypass capacitors Stage should be directly in line (as shown in placed close to the part between D1 and S2. Input Figure 32) with the inductor for space savings and capacitors should be connected in parallel close to compactness the part. Multiple input caps can be connected 4. The POWERTRENCH Technology MOSFETs depending upon the application used in the Power Stage are effective at 2. The PHASE copper trace serves two purposes; In minimizing phase node ringing. It allows the part addition to being the current path from the Power to operate well within the breakdown voltage Stage package to the output inductor (L), it also limits. This eliminates the need to have an external serves as heat sink for the lower FET in the Power snubber circuit in most cases. If the designer Stage package. The trace should be short and wide chooses to use an RC snubber, it should be placed enough to present a low resistance path for the close to the part between the PHASE pad and S2 high current flow between the Power Stage and the pins to dampen the high−frequency ringing inductor. This is done to minimize conduction 5. The driver IC should be placed close to the Power losses and limit temperature rise. Please note that Stage part with the shortest possible paths for the the PHASE node is a high voltage and high High Side gate and Low Side gates through a wide frequency switching node with high noise trace connection. This eliminates the effect of potential. Care should be taken to minimize parasitic inductance and resistance between the coupling to adjacent traces. The reference layout driver and the MOSFET and turns the devices on in Figure 31 shows a good balance between the and off as efficiently as possible. At thermal and electrical performance of Power Stage www.onsemi.com 12 FDMS3604S 7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction. Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected from the backside via a network of low inductance vias higher−frequency operation this impedance can limit the gate current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses. Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This provides a very compact path for the drive signals and improves efficiency of the part 6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET SyncFET IS trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries. www.onsemi.com 13 MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PQFN8 5X6, 1.27P (SAWN TYPE) CASE 483AJ ISSUE A DOCUMENT NUMBER: DESCRIPTION: 98AON13659G PQFN8 5X6, 1.27P DATE 08 FEB 2021 Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. 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ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com MECHANICAL CASE OUTLINE PACKAGE DIMENSIONS PQFN8 5X6, 1.27P (PUNCHED TYPE) CASE 483AJ ISSUE A DATE 08 FEB 2021 D 0.10 C (2X) SEE DETAIL B PKG CL 8 c 5 L2 PKG CL E 1 E1 (SCALE: 2X) 0.10 C (2X) 4 b1 (8X) TOP VIEW 0.10 C D1 SEE DETAIL C c A 8X 0.08 C SIDE VIEW (SCALE: 2X) D2 0.10 0.05 e/2 z1 1 2 3 E3 (6X) C 4 SEATING PLANE C A B C L1 (3X) E4 k e4 E2 e3 D3 k1 8 L (5X) z (3X) 6 7 5 b (8X) e e1 BOTTOM VIEW DOCUMENT NUMBER: DESCRIPTION: 98AON13659G PQFN8 5X6, 1.27P Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red. PAGE 2 OF 2 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. © Semiconductor Components Industries, LLC, 2019 www.onsemi.com onsemi, , and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. 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