FDMS3606AS

PowerTrench® Power Stage General Description 30 V Asymmetric Dual N-Channel MOSFET This device includes two specialized N-Channel MOSFETs in a Features dual PQFN package. The switch node has been internally Q1: N-Channel „ Max rDS(on) = 8 mΩ at VGS = 10 V, ID = 13 A connected to enable easy placement and routing of synchronous „ Max rDS(on) = 11 mΩ at VGS = 4.5 V, ID = 11 A SyncFET (Q2) have been designed to provide optimal power buck converters. The control MOSFET (Q1) and synchronous efficiency. Q2: N-Channel „ Max rDS(on) = 1.9 mΩ at VGS = 10 V, ID = 27 A Applications „ Max rDS(on) = 2.8 mΩ at VGS = 4.5 V, ID = 23 A „ Computing „ Low inductance packaging shortens rise/fall times, resulting in lower switching losses „ Communications „ MOSFET integration enables optimum layout for lower circuit inductance and reduced switch node ringing „ General Purpose Point of Load „ Notebook VCORE „ RoHS Compliant „ Sever G1 D1 D1 D1 D1 PHASE (S1/D2) G2 S2 S2 Top Power 56 S2 Bottom S2 5 S2 6 S2 7 G2 8 Q2 4 D1 PHASE 3 D1 2 D1 1 G1 Q1 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current ID TJ, TSTG Units V V (Note 3) ±20 ±20 TC = 25 °C 30 40 -Continuous (Silicon limited) TC = 25 °C 60 148 -Continuous TA = 25 °C 131a 271b -Pulsed PD Q2 30 -Continuous (Package limited) Single Pulse Avalanche Energy EAS Q1 30 40 100 404 1625 A mJ Power Dissipation for Single Operation TA = 25 °C 2.21a 2.51b Power Dissipation for Single Operation TA = 25 °C 1.01c 1.01d Operating and Storage Junction Temperature Range -55 to +150 W °C Thermal Characteristics RθJA 571a Thermal Resistance, Junction to Ambient RθJA Thermal Resistance, Junction to Ambient RθJC Thermal Resistance, Junction to Case 1c 125 3.5 501b 1201d °C/W 2 Package Marking and Ordering Information Device Marking 22CA N9CC Device Package Reel Size Tape Width Quantity FDMS3606AS Power 56 13 ” 12 mm 3000 units ©2011 Semiconductor Components Industries, LLC. October-2017, Rev. 3 Publication Order Number: FDMS3606AS/D FDMS3606AS PowerTrench® Power Stage FDMS3606AS Parameter Symbol Test Conditions Type Min 30 30 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ID = 1 mA, VGS = 0 V Q1 Q2 ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C ID = 10 mA, referenced to 25 °C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V Q1 Q2 1 500 μA μA IGSS Gate to Source Leakage Current, Forward VGS = 20 V, VDS= 0 V Q1 Q2 100 100 nA nA 2.7 3 V V 15 20 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA VGS = VDS, ID = 1 mA Q1 Q2 ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C ID = 10 mA, referenced to 25 °C Q1 Q2 -6 -5 VGS = 10 V, ID = 13 A VGS = 4.5 V, ID = 11 A VGS = 10 V, ID = 13 A , TJ = 125 °C Q1 5.8 8.5 7.8 8 11 10.8 VGS = 10 V, ID = 27 A VGS = 4.5 V, ID = 23 A VGS = 10 V, ID = 27 A , TJ = 125 °C Q2 1.4 2 1.9 1.9 2.8 2.8 VDS = 5 V, ID = 13 A VDS = 5 V, ID = 27 A Q1 Q2 61 154 Q1: VDS = 15 V, VGS = 0 V, f = 1 MHZ Q1 Q2 1273 4129 1695 5490 pF Q1 Q2 461 1527 615 2030 pF Q1 Q2 50 98 75 150 pF 0.6 0.8 2 3 Ω rDS(on) gFS Drain to Source On Resistance Forward Transconductance 1.1 1.1 2 1.8 mV/°C mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance Q2: VDS = 15 V, VGS = 0 V, f = 1 MHZ Q1 Q2 0.2 0.2 Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg Total Gate Charge Qg Total Gate Charge Qgs Gate to Source Gate Charge Qgd Gate to Drain “Miller” Charge Q1: VDD = 15 V, ID = 13 A, RGEN = 6 Ω Q2: VDD = 15 V, ID = 27 A, RGEN = 6 Ω VGS = 0 V to 10 V Q1 VDD = 15 V, VGS = 0 V to 4.5 V ID = 13 A Q2 VDD = 15 V, ID = 27 A www.onsemi.com 2 Q1 Q2 8.2 15 16 27 ns Q1 Q2 2.5 5.5 10 11 ns Q1 Q2 20 36 32 58 ns Q1 Q2 2.2 3.4 10 10 ns Q1 Q2 21 59 29 83 nC Q1 Q2 10 27 14 38 nC Q1 Q2 3.9 12 nC Q1 Q2 3.1 5.7 nC FDMS3606AS PowerTrench® Power Stage Electrical Characteristics TJ = 25 °C unless otherwise noted Symbol Parameter Test Conditions Type Min Typ Max Units Q1 Q2 0.8 0.8 1.2 1.2 V Q1 Q2 25 39 40 62 ns Q1 Q2 9 57 18 91 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 13 A VGS = 0 V, IS = 27 A (Note 2) (Note 2) Q1 IF = 13 A, di/dt = 100 A/μs Q2 IF = 27 A, di/dt = 300 A/μs Notes: 1: RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. b. 50 °C/W when mounted on a 1 in2 pad of 2 oz copper a. 57 °C/W when mounted on a 1 in2 pad of 2 oz copper c. 125 °C/W when mounted on a minimum pad of 2 oz copper d. 120 °C/W when mounted on a minimum pad of 2 oz copper 2: Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3: As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied. 4: EAS of 40 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 9 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 14 A. 5: EAS of 162 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 18 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 27 A. www.onsemi.com 3 FDMS3606AS PowerTrench® Power Stage Electrical Characteristics TJ = 25 °C unless otherwise noted 4 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 40 ID, DRAIN CURRENT (A) VGS = 10 V VGS = 6 V 30 VGS = 4.5 V VGS = 4 V 20 10 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 3.5 V 0 0.0 0.2 0.4 0.6 0.8 3 VGS = 4 V 2 VGS = 4.5 V 1 VGS = 6 V 0 1.0 0 10 20 ID, DRAIN CURRENT (A) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 1. On Region Characteristics rDS(on), DRAIN TO 1.2 1.0 0.8 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 1.4 40 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 16 ID = 13 A 12 TJ = 125 oC 8 4 TJ = 25 oC 0 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On Resistance vs Junction Temperature Figure 4. On-Resistance vs Gate to Source Voltage 40 40 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX IS, REVERSE DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 30 20 ID = 13 A VGS = 10 V -50 VGS = 10 V Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 0.6 -75 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 3.5 V 30 VDS = 5 V TJ = 150 oC 20 TJ = 25 oC 10 TJ = -55 oC 0 1.5 2.0 2.5 3.0 3.5 4.0 VGS, GATE TO SOURCE VOLTAGE (V) VGS = 0 V 10 1 TJ = 150 oC TJ = 25 oC 0.1 0.01 TJ = -55 oC 0.001 0.0 0.2 0.4 0.6 0.8 1.0 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current www.onsemi.com 4 1.2 FDMS3606AS PowerTrench® Power Stage Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted 2000 ID = 13 A VDD = 10 V 1000 Ciss 8 VDD = 15 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 6 VDD = 20 V 4 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 0 0 5 10 15 20 10 0.1 25 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 20 100 o ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) RθJC = 3.5 C/W 10 TJ = 25 oC TJ = 100 oC TJ = 125 oC 1 0.01 0.1 1 80 VGS = 10 V 60 VGS = 4.5 V 40 20 Limited by Package 10 0 25 100 50 P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 150 1000 100us 10 1 ms 10 ms THIS AREA IS LIMITED BY rDS(on) 100 ms 1s SINGLE PULSE TJ = MAX RATED 10s RθJA = 125 oC/W DC TA = 25 oC 0.01 0.01 125 Figure 10. Maximum Continuous Drain Current vs Case Temperature 100 0.1 100 o Figure 9. Unclamped Inductive Switching Capability 1 75 TC, CASE TEMPERATURE ( C) tAV, TIME IN AVALANCHE (ms) 0.1 1 10 100 200 VDS, DRAIN to SOURCE VOLTAGE (V) SINGLE PULSE RθJA = 125 oC/W 100 TA = 25 oC 10 1 0.1 -4 10 -3 10 -2 10 -1 10 1 10 100 t, PULSE WIDTH (sec) Figure 11. Forward Bias Safe Operating Area Figure 12. Single Pulse Maximum Power Dissipation www.onsemi.com 5 1000 FDMS3606AS PowerTrench® Power Stage Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 125 C/W (Note 1c) 0.001 -4 10 -3 10 -2 10 -1 10 1 10 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve www.onsemi.com 6 100 1000 FDMS3606AS PowerTrench® Power Stage Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted 25 oC unlenss otherwise noted 8 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 100 VGS = 10 V ID, DRAIN CURRENT (A) 80 VGS = 4.5 V 60 VGS = 4 V VGS = 3.5 V 40 20 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 3 V 0 0.0 0.2 0.4 0.6 0.8 6 VGS = 3.5 V 4 VGS = 10 V 0 1.0 0 20 40 60 80 100 ID, DRAIN CURRENT (A) Figure 14. On-Region Characteristics Figure 15. Normalized on-Resistance vs Drain Current and Gate Voltage 1.6 rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 -75 -50 SOURCE ON-RESISTANCE (mΩ) 8 ID = 27 A VGS = 10 V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 4.5 V VGS = 4 V 2 VDS, DRAIN TO SOURCE VOLTAGE (V) 100 = 25 oC 40 20 TJ = -55 oC 2.0 2.5 4 TJ = 125 oC 2 TJ = 25 oC 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) IS, REVERSE DRAIN CURRENT (A) TJ = 125 oC 60 0 1.5 ID = 27 A 100 80 TJ 6 Figure 17. On-Resistance vs Gate to Source Voltage PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VDS = 5 V PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) Figure 16. Normalized On-Resistance vs Junction Temperature ID, DRAIN CURRENT (A) PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 3 V 3.0 3.5 VGS, GATE TO SOURCE VOLTAGE (V) VGS = 0 V 10 TJ = 125 oC 1 TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.001 0.0 0.2 0.4 0.6 0.8 1.0 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 19. Source to Drain Diode Forward Voltage vs Source Current Figure 18. Transfer Characteristics www.onsemi.com 7 1.2 FDMS3606AS PowerTrench® Power Stage Typical Characteristics (Q2 N-Channel) TJ = 10000 ID = 27A Ciss 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 10 V 6 VDD = 15 V 4 VDD = 20 V 1000 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 0 0 10 20 30 40 50 10 0.1 60 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 21. Capacitance vs Drain to Source Voltage Figure 20. Gate Charge Characteristics 200 50 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) o RθJC = 2 C/W TJ = 25 oC 10 TJ = 100 oC TJ = 125 1 0.01 0.1 1 150 VGS = 10 V 100 VGS = 4.5 V 50 oC Limited by Package 10 100 0 25 1000 50 150 1000 P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 125 Figure 23. Maximun Continuous Drain Current vs Case Temperature 200 100 1 ms 10 10 ms 0.1 100 o Figure 22. Unclamped Inductive Switching Capability 1 75 TC, CASE TEMPERATURE ( C) tAV, TIME IN AVALANCHE (ms) THIS AREA IS LIMITED BY rDS(on) 100 ms 1s SINGLE PULSE TJ = MAX RATED 10s RθJA = 120 oC/W DC TA = 25 oC 0.01 0.01 0.1 1 10 100200 SINGLE PULSE RθJA = 120 oC/W 100 TA = 25 oC 10 1 0.1 -3 10 -2 10 -1 10 1 10 100 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 25. Single Pulse Maximum Power Dissipation Figure 24. Forward Bias Safe Operating Area www.onsemi.com 8 1000 FDMS3606AS PowerTrench® Power Stage Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted 2 TJ = 25 oC unless otherwise noted DUTY CYCLE-DESCENDING ORDER NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 SINGLE PULSE 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 120 C/W (Note 1d) 0.001 -3 10 -2 10 -1 10 1 10 t, RECTANGULAR PULSE DURATION (sec) Figure 26. Junction-to-Ambient Transient Thermal Response Curve www.onsemi.com 9 100 1000 FDMS3606AS PowerTrench® Power Stage Typical Characteristics (Q2 N-Channel) SyncFET Schottky body diode Characteristics ON Semiconductor’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 27 shows the reverse recovery characteristic of the FDMS3606AS. 25 CURRENT (A) 20 didt = 300 A/μs 15 10 5 0 0 50 100 150 200 250 300 IDSS, REVERSE LEAKAGE CURRENT (A) -2 30 -5 Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. TIME (ns) 10 TJ = 125 oC -3 10 TJ = 100 oC -4 10 -5 10 TJ = 25 oC -6 10 0 5 10 15 20 25 30 VDS, REVERSE VOLTAGE (V) Figure 27. FDMS3606AS SyncFET body diode reverse recovery characteristic www.onsemi.com 10 Figure 28. SyncFET body diode reverse leakage versus drain-source voltage FDMS3606AS PowerTrench® Power Stage Typical Characteristics (continued) 1. Switch Node Ringing Suppression ON Semiconductor’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage solution rings significantly less than competitor solutions under the same set of test conditions. Competitors solution Power Stage Device Figure 29. Power Stage phase node rising edge, High Side Turn on *Patent Pending www.onsemi.com 11 FDMS3606AS PowerTrench® Power Stage Application Information FDMS3606AS PowerTrench® Power Stage Figure 30. Shows the Power Stage in a buck converter topology 2. Recommended PCB Layout Guidelines As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2), should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout procedure is discussed below to maximize the electrical and thermal performance of the part. Figure 31. Recommended PCB Layout www.onsemi.com 12 1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic inductance and high frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected depending upon the application. 2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance between the thermal and electrical performance of Power Stage. 3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be directly in line (as shown in figure 31) with the inductor for space savings and compactness. 4. The PowerTrench® Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen the high-frequency ringing. 5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the MOSFET and turns the devices on and off as efficiently as possible. At higher-frequency operation this impedance can limit the gate current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses. Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This provides a very compact path for the drive signals and improves efficiency of the part. 6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET. 7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction. Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected from the backside via a network of low inductance vias. www.onsemi.com 13 FDMS3606AS PowerTrench® Power Stage Following is a guideline, not a requirement which the PCB designer should consider: ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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