FDMS3620S

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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. FDMS3620S PowerTrench® PowerStage 25V Asymmetric Dual N-Channel MOSFET General Description Features Q1: N-Channel This device includes two specialized N-Channel MOSFETs in a „ Max rDS(on) = 4.7 mΩ at VGS = 10 V, ID = 17.5 A dual PQFN package. The switch node has been internally „ Max rDS(on) = 5.5 mΩ at VGS = 4.5 V, ID = 16 A connected to enable easy placement and routing of synchronous Q2: N-Channel buck converters. The control MOSFET (Q1) and synchronous „ Max rDS(on) = 1.0 mΩ at VGS = 10 V, ID = 38 A SyncFET (Q2) have been designed to provide optimal power efficiency. „ Max rDS(on) = 1.2 mΩ at VGS = 4.5 V, ID = 35 A Applications „ Low inductance packaging shortens rise/fall times, resulting in lower switching losses „ Computing „ MOSFET integration enables optimum layout for lower circuit inductance and reduced switch node ringing „ Communications „ General Purpose Point of Load „ RoHS Compliant „ Notebook VCORE G1 Pin 1 D1 D1 D1 D1 Pin 1 PHASE (S1/D2) G2 S2 S2 Top Power 56 S2 Bottom S2 5 S2 6 S2 7 G2 8 Q2 4 D1 PHASE 3 D1 2 D1 1 G1 Q1 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current ID TJ, TSTG Units V V (Note 4) ±12 ±12 TC = 25 °C 30 49 -Continuous (Silicon limited) TC = 25 °C 76 211 -Continuous TA = 25 °C 17.51a 381b 70 150 -Pulsed PD Q2 25 -Continuous (Package limited) Single Pulse Avalanche Energy EAS Q1 25 (Note 3) 29 135 mJ Power Dissipation for Single Operation TA = 25 °C 2.21a 2.51b Power Dissipation for Single Operation TA = 25 °C 1.01c 1.01d Operating and Storage Junction Temperature Range A W -55 to +150 °C Thermal Characteristics RθJA Thermal Resistance, Junction to Ambient 571a 501b RθJA Thermal Resistance, Junction to Ambient 1251c 1201d RθJC Thermal Resistance, Junction to Case 3.0 1.7 °C/W Package Marking and Ordering Information Device Marking 08OD 06OD Device Package Reel Size Tape Width Quantity FDMS3620S Power 56 13 ” 12 mm 3000 units ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev.C1 1 www.fairchildsemi.com FDMS3620S PowerTrench® PowerStage July 2012 Symbol Parameter Test Conditions Type Min 25 25 Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ID = 1 mA, VGS = 0 V Q1 Q2 ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C ID = 10 mA, referenced to 25 °C Q1 Q2 IDSS Zero Gate Voltage Drain Current VDS = 20 V, VGS = 0 V Q1 Q2 1 500 μA μA IGSS Gate to Source Leakage Current VGS = 12/-8 V, VDS= 0 V Q1 Q2 ±100 ±100 nA nA 2.0 2.2 V V 12 16 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA VGS = VDS, ID = 1 mA Q1 Q2 ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C ID = 10 mA, referenced to 25 °C Q1 Q2 -4 -4 VGS = 10 V, ID = 17.5 A VGS = 4.5 V, ID = 16 A VGS = 10 V, ID = 17.5 A,TJ =125 °C Q1 3.8 4.4 5.4 4.7 5.5 7.0 VGS = 10 V, ID = 38 A VGS = 4.5 V, ID = 35 A VGS = 10 V, ID =38 A ,TJ =125 °C Q2 0.8 0.9 1.1 1.0 1.2 1.5 VDS = 5 V, ID = 17.5 A VDS = 5 V, ID = 38 A Q1 Q2 100 271 S Q1: VDS = 13 V, VGS = 0 V, f = 1 MHZ Q1 Q2 1570 6861 pF Q1 Q2 448 1828 pF Q1 Q2 61 232 pF rDS(on) gFS Drain to Source On Resistance Forward Transconductance 0.8 1.1 1.2 1.3 mV/°C mΩ Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance Q2: VDS = 13 V, VGS = 0 V, f = 1 MHZ Q1 Q2 0.1 0.1 0.4 0.6 3.3 3.5 Ω Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg Total Gate Charge Qg Total Gate Charge Qgs Gate to Source Gate Charge Qgd Gate to Drain “Miller” Charge ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev.C1 Q1: VDD = 13 V, ID = 17.5 A, RGEN = 6 Ω Q2: VDD = 13 V, ID = 38 A, RGEN = 6 Ω VGS = 0 V to 10 V Q1 VDD = 13 V, VGS = 0 V to 4.5 V ID = 17.5 A Q2 VDD = 13 V, ID = 38 A 2 Q1 Q2 7 14 ns Q1 Q2 2 7 ns Q1 Q2 23 41 ns Q1 Q2 2 5 ns Q1 Q2 26 106 nC Q1 Q2 12 50 nC Q1 Q2 3.3 12.9 nC Q1 Q2 2.7 12 nC www.fairchildsemi.com FDMS3620S PowerTrench® PowerStage Electrical Characteristics TJ = 25 °C unless otherwise noted Symbol Parameter Test Conditions Type Min Typ Max Units Q1 Q2 0.8 0.8 1.2 1.2 V Q1 Q2 23 38 ns Q1 Q2 9 54 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 17.5 A VGS = 0 V, IS = 38 A (Note 2) (Note 2) Q1 IF = 17.5 A, di/dt = 100 A/μs Q2 IF = 38 A, di/dt = 300 A/μs Notes: 1.RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. c. 50 °C/W when mounted on a 1 in2 pad of 2 oz copper a. 57 °C/W when mounted on a 1 in2 pad of 2 oz copper b. 125 °C/W when mounted on a minimum pad of 2 oz copper d. 120 °C/W when mounted on a minimum pad of 2 oz copper 2 Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. Q1 :EAS of 29 mJ is based on starting TJ = 25 oC; N-ch: L = 0.3 mH, IAS = 14 A, VDD = 23 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 20 A. Q2: EAS of 135 mJ is based on starting TJ = 25 oC; N-ch: L = 0.3 mH, IAS = 30 A, VDD = 23 V, VGS = 10 V. 100% test at L= 0.1 mH, IAS = 44 A. 4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied. ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev.C1 3 www.fairchildsemi.com FDMS3620S PowerTrench® PowerStage Electrical Characteristics TJ = 25 °C unless otherwise noted 70 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 60 ID, DRAIN CURRENT (A) 3.0 VGS = 10 V VGS = 4.5 V 50 VGS = 3.5 V 40 VGS = 3 V 30 VGS = 2.5 V 20 10 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0.0 0.3 0.6 0.9 1.2 1.5 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 2.5 VGS = 2.5 V 2.0 VGS = 3 V 1.5 1.0 VGS = 3.5 V VGS = 4.5 V VGS = 10 V 0.5 0 10 20 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 1. On Region Characteristics rDS(on), DRAIN TO 1.2 1.0 0.8 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 1.4 -50 IS, REVERSE DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 40 TJ = 150 oC 30 TJ = 25 oC 20 TJ = -55 oC 10 1.5 2.0 2.5 8 TJ = 125 oC 4 TJ = 25 oC 2 3 4 5 6 7 8 9 10 VGS = 0 V 10 TJ = 150 oC 1 TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.001 0.0 3.0 VGS, GATE TO SOURCE VOLTAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 6. Source to Drain Diode Forward Voltage vs Source Current Figure 5. Transfer Characteristics ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev.C1 12 70 VDS = 5 V 1.0 16 Figure 4. On-Resistance vs Gate to Source Voltage 50 0 0.5 70 VGS, GATE TO SOURCE VOLTAGE (V) PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 60 60 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX ID = 17.5 A 0 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) Figure 3. Normalized On Resistance vs Junction Temperature 70 50 20 ID = 17.5 A VGS = 10 V 0.6 -75 40 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.8 1.6 30 ID, DRAIN CURRENT (A) 4 www.fairchildsemi.com FDMS3620S PowerTrench® PowerStage Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted 2000 ID = 17.5 A 1000 Ciss 8 VDD = 10 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 15 V 6 VDD = 13 V 4 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 0 0 4 8 12 16 20 24 10 0.1 28 1 Figure 7. Gate Charge Characteristics 80 70 10 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 30 Figure 8. Capacitance vs Drain to Source Voltage 30 TJ = 25 oC TJ = 100 oC TJ = 125 oC 60 VGS = 10 V 50 VGS = 4.5 V 40 30 20 Limited by Package o RθJC = 3.0 C/W 10 1 0.001 0.01 0.1 1 10 0 25 50 50 125 150 Figure 10. Maximum Continuous Drain Current vs Case Temperature 100 P(PK), PEAK TRANSIENT POWER (W) 1000 100 μs 10 1 ms 0.1 100 TC, CASE TEMPERATURE ( C) Figure 9. Unclamped Inductive Switching Capability 1 75 o tAV, TIME IN AVALANCHE (ms) ID, DRAIN CURRENT (A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) 10 ms THIS AREA IS LIMITED BY rDS(on) 100 ms SINGLE PULSE TJ = MAX RATED 1s 10s RθJA = 125 oC/W DC TA = 25 oC 0.01 0.01 0.1 1 10 100 VDS, DRAIN to SOURCE VOLTAGE (V) o RθJA = 125 C/W 100 10 1 0.5 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, PULSE WIDTH (sec) Figure 11. Forward Bias Safe Operating Area ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev.C1 SINGLE PULSE Figure 12. Single Pulse Maximum Power Dissipation 5 www.fairchildsemi.com FDMS3620S PowerTrench® PowerStage Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted 2 DUTY CYCLE-DESCENDING ORDER NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 SINGLE PULSE 0.01 t2 o NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA RθJA = 125 C/W (Note 1b) 0.001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev.C1 6 www.fairchildsemi.com FDMS3620S PowerTrench® PowerStage Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted 150 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 4.5 V VGS = 3.5 V 120 ID, DRAIN CURRENT (A) 6 VGS = 10 V VGS = 3 V 90 VGS = 2.5 V 60 30 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0 0.3 0.6 0.9 4 3 VGS = 3 V 2 VGS = 3.5 V 1 0 30 rDS(on), DRAIN TO 1.2 1.0 0.8 0 25 50 75 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 1.4 4 ID = 38 A 3 2 TJ = 125 oC 1 TJ = 25 oC 0 100 125 150 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 17. On-Resistance vs Gate to Source Voltage Figure 16. Normalized On-Resistance vs Junction Temperature 200 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX IS, REVERSE DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 150 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX TJ, JUNCTION TEMPERATURE (oC) 120 120 5 ID = 38 A VGS = 10 V 150 90 Figure 15. Normalized on-Resistance vs Drain Current and Gate Voltage 1.6 -25 60 ID, DRAIN CURRENT (A) Figure 14. On-Region Characteristics -50 VGS = 10 V VGS = 4.5 V 0 VDS, DRAIN TO SOURCE VOLTAGE (V) 0.6 -75 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 2.5 V 5 VDS = 5 V 90 TJ = 150 oC 60 TJ = 25 oC 30 100 VGS = 0 V TJ = 150 oC 10 TJ = 25 oC 1 TJ = -55 oC TJ = -55 oC 0 1.0 1.5 2.0 2.5 3.0 0 VGS, GATE TO SOURCE VOLTAGE (V) Figure 18. Transfer Characteristics ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev.C1 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 19. Source to Drain Diode Forward Voltage vs Source Current 7 www.fairchildsemi.com FDMS3620S PowerTrench® PowerStage Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted 10000 VGS, GATE TO SOURCE VOLTAGE (V) 10 ID = 38 A Ciss 6 VDD = 13 V VDD = 10 V 4 CAPACITANCE (pF) 8 VDD = 15 V 1000 Coss 100 Crss 2 0 f = 1 MHz VGS = 0 V 0 20 40 60 80 100 10 0.1 120 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 21. Capacitance vs Drain to Source Voltage Figure 20. Gate Charge Characteristics 210 100 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) VGS = 10 V 180 TJ = 25 oC TJ = 100 oC 10 150 VGS = 4.5 V 120 90 60 30 TJ = 125 oC 1 0.001 0.01 0.1 1 o RθJC = 1.7 C/W 10 100 0 25 1000 50 150 10000 100 P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 125 Figure 23. Maximum Continuous Drain Current vs Case Temperature 1000 100 us 10 0.1 100 o Figure 22. Unclamped Inductive Switching Capability 1 75 TC, CASE TEMPERATURE ( C) tAV, TIME IN AVALANCHE (ms) 1 ms THIS AREA IS LIMITED BY rDS(on) 10 ms 100 ms SINGLE PULSE TJ = MAX RATED 1s 10 s DC o RθJA = 120 C/W TA = 25 oC 0.01 0.01 0.1 1 10 100 TA = 25 oC 100 10 1 0.1 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, PULSE WIDTH (s) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 24. Forward Bias Safe Operating Area ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev.C1 SINGLE PULSE RθJA = 120 oC/W 1000 Figure 25. Single Pulse Maximum Power Dissipation 8 www.fairchildsemi.com FDMS3620S PowerTrench® PowerStage Typical Characteristics (Q2 N-Channel) TJ = 25°C unless otherwise noted NORMALIZED THERMAL IMPEDANCE, ZθJA 2 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM 0.01 t1 t2 SINGLE PULSE 0.001 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA o RθJA = 120 C/W Note 1d 0.0001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (s) Figure 26. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev.C1 9 www.fairchildsemi.com FDMS3620S PowerTrench® PowerStage Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted SyncFET Schottky body diode Characteristics Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. Fairchild’s SyncFET process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 27 shows the reverse recovery characteristic of the FDMS3620S. -2 IDSS, REVERSE LEAKAGE CURRENT (A) 45 40 35 CURRENT (A) 30 25 di/dt = 300 A/μs 20 15 10 5 0 -5 0 50 100 150 200 250 300 350 TIME (ns) TJ = 125 oC -3 10 TJ = 100 oC -4 10 -5 10 TJ = 25 oC -6 10 0 5 10 15 20 25 VDS, REVERSE VOLTAGE (V) Figure 28. SyncFET body diode reverse leakage versus drain-source voltage Figure 27. FDMS3620S SyncFET body diode reverse recovery characteristic ©2012 Fairchild Semiconductor Corporation FDMS3620S Rev.C1 10 10 www.fairchildsemi.com FDMS3620S PowerTrench® PowerStage Typical Characteristics (Q2 N-Channel) CL B PKG CL 8 A 0.00 (2X) 2.00 5.10 4.90 0.10 C 4.00 5 8 7 6 1.27 TYP 0.65 TYP 5 0.63 6.25 5.90 PKG CL 2.52 1.60 KEEP OUT AREA 2.15 0.00 CL 4.16 1.21 2.13 1 PIN # 1 INDICATOR 4 0.10 C (2X) 1.18 TOP VIEW 2 1 0.63 SEE DETAIL A 3 4 2.31 3.15 0.59 3.18 5.10 RECOMMENDED LAND PATTERN FOR SAWN / PUNCHED TYPE SIDE VIEW 0.10 0.05 0.45 0.25 3.16 2.80 0.65 0.38 1 2 3 (6X) C A B C 0.70 0.36 4 1.34 1.12 0.10 C 8X 0.08 C 1.10 0.90 0.35 0.15 0.66±.05 2.25 2.05 4.08 3.70 0.65 0.38 8 0.44 0.24 7 6 5 1.27 3.81 BOTTOM VIEW 1.02 0.82 0.61 (8X) 0.31 (SCALE: 2X) 0.05 0.00 C SEATING PLANE 5.10 4.90 0.10 C (2X) SEE DETAIL B PKG CL 8 0.35 0.15 5 0.28 0.08 PKG 6.25 5.90 CL 1 (SCALE: 2X) 0.10 C (2X) 4 0.41 (8X) 0.21 TOP VIEW 10° 5.90 5.70 5.00 4.80 SEE DETAIL C 0.10 C 0.35 0.15 8X 0.08 C C SIDE VIEW 1.10 0.90 0.45 0.25 (6X) 3.16 2.80 0.65 0.38 1 2 3 0.70 0.36 4 0.10 0.05 0.65 0.38 0.44 0.24 2.25 2.05 8 7 6 5 1.27 3.81 BOTTOM VIEW C A B C 1.34 1.12 0.66±.05 4.08 3.70 (SCALE: 2X) SEATING PLANE 1.02 0.82 0.61 0.31 (8X) NOTES: UNLESS OTHERWISE SPECIFIED A) PACKAGE STANDARD REFERENCE: JEDEC REGISTRATION, MO-240, VARIATION AA. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. E) IT IS RECOMMENDED TO HAVE NO TRACES OR VIAS WITHIN THE KEEP OUT AREA. F) DRAWING FILE NAME: PQFN08EREV6. G) FAIRCHILD SEMICONDUCTOR ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. 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