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PowerTrench® Power Stage
Asymmetric Dual N-Channel MOSFET
Features
General Description
Q1: N-Channel
This device includes two specialized N-Channel MOSFETs in a
Max rDS(on) = 8 mΩ at VGS = 10 V, ID = 13 A
dual PQFN package. The switch node has been internally
Max rDS(on) = 11 mΩ at VGS = 4.5 V, ID = 11 A
connected to enable easy placement and routing of synchronous
buck converters. The control MOSFET (Q1) and synchronous
Q2: N-Channel
SyncFET (Q2) have been designed to provide optimal power
Max rDS(on) = 2.8 mΩ at VGS = 10 V, ID = 23 A
efficiency.
Max rDS(on) = 3.8 mΩ at VGS = 4.5 V, ID = 21 A
Applications
Low inductance packaging shortens rise/fall times, resulting in
lower switching losses
Computing
MOSFET integration enables optimum layout for lower circuit
inductance and reduced switch node ringing
Communications
General Purpose Point of Load
RoHS Compliant
Notebook VCORE
G1
D1
D1
D1
D1
PHASE
(S1/D2)
G2
S2
S2
Top
Power 56
S2
Bottom
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Symbol
VDS
Drain to Source Voltage
Parameter
VGS
Gate to Source Voltage
Drain Current
ID
TJ, TSTG
Units
V
V
(Note 3)
±20
±20
TC = 25 °C
30
55
-Continuous (Silicon limited)
TC = 25 °C
54
123
-Continuous
TA = 25 °C
131a
231b
40
100
404
604
-Pulsed
PD
Q2
30
-Continuous (Package limited)
Single Pulse Avalanche Energy
EAS
Q1
30
2.51b
1.01d
TA = 25 °C
2.2
Power Dissipation for Single Operation
TA = 25 °C
1.01c
Operating and Storage Junction Temperature Range
mJ
1a
Power Dissipation for Single Operation
A
W
-55 to +150
°C
Thermal Characteristics
Thermal Resistance, Junction to Ambient
571a
501b
RθJA
Thermal Resistance, Junction to Ambient
1251c
1201d
RθJC
Thermal Resistance, Junction to Case
3.5
2.0
RθJA
°C/W
Package Marking and Ordering Information
Device Marking
22CA
F10CC
Device
Package
Reel Size
Tape Width
Quantity
FDMS3686S
Power 56
13 ”
12 mm
3000 units
©2012 Fairchild Semiconductor Corporation
FDMS3686S Rev.C1
1
www.fairchildsemi.com
FDMS3686S PowerTrench® Power Stage
January 2012
FDMS3686S
Symbol
Parameter
Test Conditions
Type
Min
30
30
Typ
Max
Units
Off Characteristics
BVDSS
Drain to Source Breakdown Voltage
ID = 250 μA, VGS = 0 V
ID = 1 mA, VGS = 0 V
Q1
Q2
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
Q1
Q2
IDSS
Zero Gate Voltage Drain Current
VDS = 24 V, VGS = 0 V
Q1
Q2
1
500
μA
μA
IGSS
Gate to Source Leakage Current,
Forwad
VGS = 20 V, VDS= 0 V
Q1
Q2
100
100
nA
nA
2.7
3.0
V
V
15
19
mV/°C
On Characteristics
VGS(th)
Gate to Source Threshold Voltage
VGS = VDS, ID = 250 μA
VGS = VDS, ID = 1 mA
Q1
Q2
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient
ID = 250 μA, referenced to 25 °C
ID = 10 mA, referenced to 25 °C
Q1
Q2
-6
-4
VGS = 10 V, ID = 13 A
VGS = 4.5 V, ID = 11 A
VGS = 10 V, ID = 13 A , TJ = 125 °C
Q1
5.8
8.5
7.8
8
11
10.8
VGS = 10 V, ID = 23 A
VGS = 4.5 V, ID = 21 A
VGS = 10 V, ID = 23 A , TJ = 125 °C
Q2
2.2
3.0
3.1
2.8
3.8
4.0
VDS = 5 V, ID = 13 A
VDS = 5 V, ID = 23 A
Q1
Q2
61
124
Q1:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
1340
1820
1785
2420
pF
Q1
Q2
485
725
645
965
pF
Q1
Q2
53
86
80
130
pF
0.6
0.9
2
3
Ω
rDS(on)
gFS
Drain to Source On Resistance
Forward Transconductance
1.1
1.1
2
1.5
mV/°C
mΩ
S
Dynamic Characteristics
Ciss
Input Capacitance
Coss
Output Capacitance
Crss
Reverse Transfer Capacitance
Rg
Gate Resistance
Q2:
VDS = 15 V, VGS = 0 V, f = 1 MHZ
Q1
Q2
0.2
0.2
Switching Characteristics
td(on)
Turn-On Delay Time
tr
Rise Time
td(off)
Turn-Off Delay Time
tf
Fall Time
Qg
Total Gate Charge
Qg
Total Gate Charge
Qgs
Gate to Source Gate Charge
Qgd
Gate to Drain “Miller” Charge
©2012 Fairchild Semiconductor Corporation
FDMS3686S Rev.C1
Q1:
VDD = 15 V, ID = 13 A, RGEN = 6 Ω
Q2:
VDD = 15 V, ID = 23 A, RGEN = 6 Ω
VGS = 0 V to 10 V Q1
VDD = 15 V,
VGS = 0 V to 4.5 V ID = 13 A
Q2
VDD = 15 V,
ID = 23 A
2
Q1
Q2
8.2
9
16
18
ns
Q1
Q2
2.5
4
10
10
ns
Q1
Q2
20
23
32
36
ns
Q1
Q2
2.2
3
10
10
ns
Q1
Q2
21
27
29
37
nC
Q1
Q2
10
13
14
18
nC
Q1
Q2
3.9
4.6
nC
Q1
Q2
3.1
3.7
nC
www.fairchildsemi.com
FDMS3686S PowerTrench® Power Stage
Electrical Characteristics TJ = 25 °C unless otherwise noted
Symbol
Parameter
Test Conditions
Type
Min
Typ
Max
Units
Q1
Q1
Q2
Q2
0.72
0.82
0.58
0.76
1.2
1.2
1.2
1.2
V
Q1
Q2
25
25
40
39
ns
Q1
Q2
9
23
18
36
nC
Drain-Source Diode Characteristics
VSD
VGS = 0 V, IS = 2 A
V = 0 V, IS = 13 A
Source to Drain Diode Forward Voltage GS
VGS = 0 V, IS = 2 A
VGS = 0 V, IS = 23 A
trr
Reverse Recovery Time
Qrr
Reverse Recovery Charge
(Note 2)
(Note 2)
(Note 2)
(Note 2)
Q1
IF = 13 A, di/dt = 100 A/μs
Q2
IF = 23 A, di/dt = 300 A/μs
Notes:
1. RqJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RqJC is guaranteed by design while RqCA is determined
by the user's board design.
b. 50 °C/W when mounted on
a 1 in2 pad of 2 oz copper
a. 57 °C/W when mounted on
a 1 in2 pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
d. 120 °C/W when mounted on a
minimum pad of 2 oz copper
c. 125 °C/W when mounted on a
minimum pad of 2 oz copper
SS
SF
DS
DF
G
SS
SF
DS
DF
G
2. Pulse Test: Pulse Width < 300 ms, Duty cycle < 2.0%.
3. As an N-ch device, the negative Vgs rating is for low duty cycle pulse ocurrence only. No continuous rating is implied.
4. Q1: EAS of 40 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 9 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 14 A.
Q2: EAS of 60 mJ is based on starting TJ = 25 oC; N-ch: L = 1 mH, IAS = 11 A, VDD = 27 V, VGS = 10 V. 100% test at L= 0.3 mH, IAS = 17 A.
©2012 Fairchild Semiconductor Corporation
FDMS3686S Rev.C1
3
www.fairchildsemi.com
FDMS3686S PowerTrench® Power Stage
Electrical Characteristics TJ = 25 °C unless otherwise noted
4
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
40
ID, DRAIN CURRENT (A)
VGS = 10 V
VGS = 6 V
30
VGS = 4.5 V
VGS = 4 V
20
VGS = 3.5 V
10
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0.0
0.2
0.4
0.6
0.8
3
VGS = 4 V
2
VGS = 4.5 V
VGS = 6 V
1
0
1.0
VGS = 10 V
0
10
20
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 1. On Region Characteristics
rDS(on), DRAIN TO
1.2
1.0
0.8
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
1.4
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
16
ID = 13 A
12
TJ = 125 oC
8
4
TJ = 25 oC
0
-25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (oC)
2
4
6
8
10
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. Normalized On Resistance
vs Junction Temperature
Figure 4. On-Resistance vs Gate to
Source Voltage
40
40
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
IS, REVERSE DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
40
20
ID = 13 A
VGS = 10 V
-50
30
Figure 2. Normalized On-Resistance
vs Drain Current and Gate Voltage
1.6
0.6
-75
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 3.5 V
30
VDS = 5 V
TJ = 150 oC
20
TJ = 25 oC
10
TJ = -55 oC
0
1.5
2.0
2.5
3.0
3.5
1
TJ = 150 oC
TJ = 25 oC
0.1
0.01
TJ = -55 oC
0.001
0.0
4.0
VGS, GATE TO SOURCE VOLTAGE (V)
0.2
0.4
0.6
0.8
1.0
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
©2012 Fairchild Semiconductor Corporation
FDMS3686S Rev.C1
VGS = 0 V
10
Figure 6. Source to Drain Diode
Forward Voltage vs Source Current
4
www.fairchildsemi.com
FDMS3686S PowerTrench® Power Stage
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
VGS, GATE TO SOURCE VOLTAGE (V)
10
2000
ID = 13 A
VDD = 10 V
1000
Ciss
8
CAPACITANCE (pF)
VDD = 15 V
6
VDD = 20 V
4
Coss
100
Crss
2
f = 1 MHz
VGS = 0 V
0
0
5
10
15
20
10
0.1
25
1
Figure 7. Gate Charge Characteristics
60
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
30
Figure 8. Capacitance vs Drain
to Source Voltage
70
TJ = 25 oC
10
TJ
= 100 oC
TJ = 125 oC
50
VGS = 10 V
40
VGS = 4.5 V
30
20
Limited by Package
o
RθJC = 3.5 C/W
10
1
0.001
0.01
0.1
1
10
0
25
100
50
150
P(PK), PEAK TRANSIENT POWER (W)
1000
100us
10
1 ms
10 ms
THIS AREA IS
LIMITED BY rDS(on)
100 ms
1s
SINGLE PULSE
TJ = MAX RATED
10s
o
RθJA = 125 C/W
DC
TA = 25 oC
0.01
0.01
125
Figure 10. Maximum Continuous Drain
Current vs Case Temperature
100
0.1
100
o
Figure 9. Unclamped Inductive
Switching Capability
1
75
TA, AMBIENT TEMPERATURE ( C)
tAV, TIME IN AVALANCHE (ms)
ID, DRAIN CURRENT (A)
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
0.1
1
10
100 200
VDS, DRAIN to SOURCE VOLTAGE (V)
100
TA = 25 oC
10
1
0.1
-4
10
-3
10
-2
10
-1
10
1
100
10
1000
t, PULSE WIDTH (sec)
Figure 11. Forward Bias Safe
Operating Area
©2012 Fairchild Semiconductor Corporation
FDMS3686S Rev.C1
SINGLE PULSE
RθJA = 125 oC/W
Figure 12. Single Pulse Maximum
Power Dissipation
5
www.fairchildsemi.com
FDMS3686S PowerTrench® Power Stage
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
2
NORMALIZED THERMAL
IMPEDANCE, ZθJA
1
0.1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
t1
0.01
t2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
o
RθJA = 125 C/W
(Note 1c)
0.001
-4
10
-3
10
-2
10
-1
10
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 13. Junction-to-Ambient Transient Thermal Response Curve
©2012 Fairchild Semiconductor Corporation
FDMS3686S Rev.C1
6
www.fairchildsemi.com
FDMS3686S PowerTrench® Power Stage
Typical Characteristics (Q1 N-Channel) TJ = 25 °C unless otherwise noted
25 oC unlenss otherwise noted
4
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
100
VGS = 10 V
ID, DRAIN CURRENT (A)
80
VGS = 4.5 V
VGS = 4 V
60
VGS = 3.5 V
40
VGS = 3 V
20
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
0
0.0
0.2
0.4
0.6
0.8
1.0
3
VGS = 3.5 V
2
VGS = 4 V
VGS = 4.5 V
1
VGS = 10 V
0
0
20
40
VDS, DRAIN TO SOURCE VOLTAGE (V)
80
100
Figure 15. Normalized on-Resistance vs Drain
Current and Gate Voltage
1.6
12
ID = 23 A
VGS = 10 V
rDS(on), DRAIN TO
1.4
1.2
1.0
0.8
0.6
-75
-50
-25
0
25
50
75
SOURCE ON-RESISTANCE (mΩ)
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
60
ID, DRAIN CURRENT (A)
Figure 14. On-Region Characteristics
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
9
ID = 23 A
6
TJ = 125 oC
3
TJ = 25 oC
0
100 125 150
2
TJ, JUNCTION TEMPERATURE (oC)
100
IS, REVERSE DRAIN CURRENT (A)
VDS = 5 V
60
40
TJ = 25 oC
20
TJ = -55 oC
2.0
2.5
3.0
3.5
10
VGS = 0 V
10
TJ = 125 oC
1
TJ = 25 oC
0.1
TJ = -55 oC
0.01
0.001
0.0
4.0
VGS, GATE TO SOURCE VOLTAGE (V)
0.2
0.4
0.6
0.8
1.0
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 19. Source to Drain Diode
Forward Voltage vs Source Current
Figure 18. Transfer Characteristics
©2012 Fairchild Semiconductor Corporation
FDMS3686S Rev.C1
8
100
80
0
1.5
6
Figure 17. On-Resistance vs Gate to
Source Voltage
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
TJ = 125 oC
4
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 16. Normalized On-Resistance
vs Junction Temperature
ID, DRAIN CURRENT (A)
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 3 V
7
www.fairchildsemi.com
FDMS3686S PowerTrench® Power Stage
Typical Characteristics (Q2 N-Channel) TJ =
10000
ID = 23 A
Ciss
8
CAPACITANCE (pF)
VGS, GATE TO SOURCE VOLTAGE (V)
10
6
VDD = 10 V
VDD = 15 V
4
VDD = 20 V
1000
Coss
100
2
0
0
5
10
15
20
25
10
0.1
30
1
30
Figure 21. Capacitance vs Drain
to Source Voltage
Figure 20. Gate Charge Characteristics
70
160
ID, DRAIN CURRENT (A)
IAS, AVALANCHE CURRENT (A)
10
VDS, DRAIN TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
TJ = 25 oC
10
TJ = 100 oC
TJ = 125
1
0.001
0.01
oC
0.1
1
10
120
VGS = 10 V
80
VGS = 4.5 V
40
Limited by Package
o
RθJC = 2.0 C/W
0
25
100
50
125
150
Figure 23. Maximun Continuous Drain
Current vs Case Temperature
10000
P(PK), PEAK TRANSIENT POWER (W)
200
100
100 us
10
1 ms
THIS AREA IS
LIMITED BY rDS(on)
10 ms
100 ms
0.1
100
o
Figure 22. Unclamped Inductive
Switching Capability
1
75
TC, CASE TEMPERATURE ( C)
tAV, TIME IN AVALANCHE (ms)
ID, DRAIN CURRENT (A)
Crss
f = 1 MHz
VGS = 0 V
SINGLE PULSE
TJ = MAX RATED
1s
10s
o
RθJA = 120 C/W
DC
TA = 25 oC
0.01
0.01
0.1
1
10
100200
TA = 25 oC
100
10
1
0.1
-4
10
-3
10
-2
10
-1
10
1
10
100
1000
t, PULSE WIDTH (sec)
VDS, DRAIN to SOURCE VOLTAGE (V)
Figure 25. Single Pulse Maximum
Power Dissipation
Figure 24. Forward Bias Safe
Operating Area
©2012 Fairchild Semiconductor Corporation
FDMS3686S Rev.C1
SINGLE PULSE
RθJA = 120 oC/W
1000
8
www.fairchildsemi.com
FDMS3686S PowerTrench® Power Stage
Typical Characteristics (Q2 N-Channel) TJ = 25 oC unless otherwise noted
NORMALIZED THERMAL
IMPEDANCE, ZθJA
2
1
0.1
DUTY CYCLE-DESCENDING ORDER
D = 0.5
0.2
0.1
0.05
0.02
0.01
PDM
0.01
t1
t2
SINGLE PULSE
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
o
RθJA = 120 C/W
0.001
(Note 1d)
0.0001 -4
10
-3
10
-2
10
-1
10
1
10
100
1000
t, RECTANGULAR PULSE DURATION (sec)
Figure 26. Junction-to-Ambient Transient Thermal Response Curve
©2012 Fairchild Semiconductor Corporation
FDMS3686S Rev.C1
9
www.fairchildsemi.com
FDMS3686S PowerTrench® Power Stage
TJ = 25 oC unless otherwise noted
Typical Characteristics (Q2 N-Channel)
SyncFET Schottky body diode
Characteristics
Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power
in the device.
Fairchild’s SyncFET process embeds a Schottky diode in parallel
with PowerTrench MOSFET. This diode exhibits similar
characteristics to a discrete external Schottky diode in parallel
with a MOSFET. Figure 27 shows the reverse recovery
characteristic of the FDMS3686S.
-2
IDSS, REVERSE LEAKAGE CURRENT (A)
25
20
CURRENT (A)
didt = 300 A/μs
15
10
5
0
-5
0
50
100
150
200
TIME (ns)
TJ = 125 oC
-3
10
TJ = 100 oC
-4
10
TJ = 25 oC
-5
10
-6
10
0
5
10
15
20
25
30
VDS, REVERSE VOLTAGE (V)
Figure 28. SyncFET body diode reverse
leakage versus drain-source voltage
Figure 27. FDMS3686S SyncFET body
diode reverse recovery characteristic
©2012 Fairchild Semiconductor Corporation
FDMS3686S Rev.C1
10
10
www.fairchildsemi.com
FDMS3686S PowerTrench® Power Stage
Typical Characteristics (continued)
1. Switch Node Ringing Suppression
Fairchild’s Power Stage products incorporate a proprietary design* that minimizes the peak overshoot, ringing voltage on the switch
node (PHASE) without the need of any external snubbing components in a buck converter. As shown in the figure 29, the Power Stage
solution rings significantly less than competitor solutions under the same set of test conditions.
Competitors solution
Power Stage Device
Figure 29. Power Stage phase node rising edge, High Side Turn on
*Patent Pending
©2012 Fairchild Semiconductor Corporation
FDMS3686S Rev.C1
11
www.fairchildsemi.com
FDMS3686S PowerTrench® Power Stage
Application Information
FDMS3686S PowerTrench® Power Stage
Figure 30. Shows the Power Stage in a buck converter topology
2. Recommended PCB Layout Guidelines
As a PCB designer, it is necessary to address critical issues in layout to minimize losses and optimize the performance of the power
train. Power Stage is a high power density solution and all high current flow paths, such as VIN (D1), PHASE (S1/D2) and GND (S2),
should be short and wide for better and stable current flow, heat radiation and system performance. A recommended layout procedure is discussed below to maximize the electrical and thermal performance of the part.
Figure 31. Recommended PCB Layout
©2012 Fairchild Semiconductor Corporation
FDMS3686S Rev.C1
12
www.fairchildsemi.com
1. Input ceramic bypass capacitors C1 and C2 must be placed close to the D1 and S2 pins of Power Stage to help reduce parasitic
inductance and High Frequency conduction loss induced by switching operation. C1 and C2 show the bypass capacitors placed close
to the part between D1 and S2. Input capacitors should be connected in parallel close to the part. Multiple input caps can be connected
depending upon the application.
2. The PHASE copper trace serves two purposes; In addition to being the current path from the Power Stage package to the output
inductor (L), it also serves as heat sink for the lower FET in the Power Stage package. The trace should be short and wide enough to
present a low resistance path for the high current flow between the Power Stage and the inductor. This is done to minimize conduction
losses and limit temperature rise. Please note that the PHASE node is a high voltage and high frequency switching node with high
noise potential. Care should be taken to minimize coupling to adjacent traces. The reference layout in figure 31 shows a good balance
between the thermal and electrical performance of Power Stage.
3. Output inductor location should be as close as possible to the Power Stage device for lower power loss due to copper trace
resistance. A shorter and wider PHASE trace to the inductor reduces the conduction loss. Preferably the Power Stage should be
directly in line (as shown in figure 31) with the inductor for space savings and compactness.
4. The PowerTrench® Technology MOSFETs used in the Power Stage are effective at minimizing phase node ringing. It allows the
part to operate well within the breakdown voltage limits. This eliminates the need to have an external snubber circuit in most cases. If
the designer chooses to use an RC snubber, it should be placed close to the part between the PHASE pad and S2 pins to dampen
the high-frequency ringing.
5. The driver IC should be placed close to the Power Stage part with the shortest possible paths for the High Side gate and Low Side
gates through a wide trace connection. This eliminates the effect of parasitic inductance and resistance between the driver and the
MOSFET and turns the devices on and off as efficiently as possible. At higher-frequency operation this impedance can limit the gate
current trying to charge the MOSFET input capacitance. This will result in slower rise and fall times and additional switching losses.
Power Stage has both the gate pins on the same side of the package which allows for back mounting of the driver IC to the board. This
provides a very compact path for the drive signals and improves efficiency of the part.
6. S2 pins should be connected to the GND plane with multiple vias for a low impedance grounding. Poor grounding can create a noise
transient offset voltage level between S2 and driver ground. This could lead to faulty operation of the gate driver and MOSFET.
7. Use multiple vias on each copper area to interconnect top, inner and bottom layers to help smooth current flow and heat conduction.
Vias should be relatively large, around 8 mils to 10 mils, and of reasonable inductance. Critical high frequency components such as
ceramic bypass caps should be located close to the part and on the same side of the PCB. If not feasible, they should be connected
from the backside via a network of low inductance vias.
©2012 Fairchild Semiconductor Corporation
FDMS3686S Rev.C1
13
www.fairchildsemi.com
FDMS3686S PowerTrench® Power Stage
Following is a guideline, not a requirement which the PCB designer should consider:
CL
B
PKG
CL
8
A
0.00
(2X)
2.00
5.10
4.90
0.10 C
4.00
5
8
7
6
1.27 TYP
0.65 TYP
5
0.63
6.25
5.90
PKG CL
2.52
1.60
KEEP OUT AREA
2.15
0.00 CL
4.16
1.21
2.13
1
PIN # 1
INDICATOR
4
0.10 C
(2X)
1.18
TOP VIEW
2
1
0.63
SEE
DETAIL A
3
4
2.31
3.15
0.59
3.18
5.10
RECOMMENDED LAND PATTERN
FOR SAWN / PUNCHED TYPE
SIDE VIEW
0.10
0.05
0.45
0.25
3.16
2.80
0.65
0.38
1
2
3
(6X)
C A B
C
0.70
0.36
4
1.34
1.12
0.10 C
8X
0.08 C
1.10
0.90
0.35
0.15
0.66±.05
2.25
2.05
4.08
3.70
0.65
0.38
8
0.44
0.24
7
6
5
1.27
3.81
BOTTOM VIEW
1.02
0.82
0.61 (8X)
0.31
(SCALE: 2X)
0.05
0.00
C
SEATING
PLANE
5.10
4.90
0.10 C
(2X)
SEE
DETAIL B
PKG
CL
8
0.35
0.15
5
0.28
0.08
PKG
6.25
5.90
CL
1
(SCALE: 2X)
0.10 C
(2X)
4
0.41 (8X)
0.21
TOP VIEW
10°
5.90
5.70
5.00
4.80
SEE
DETAIL C
0.10 C
0.35
0.15
8X
0.08 C
C
SIDE VIEW
1.10
0.90
0.45
0.25
(6X)
3.16
2.80
0.65
0.38
1
2
3
0.70
0.36
4
0.10
0.05
0.65
0.38
0.44
0.24
2.25
2.05
8
7
6
5
1.27
3.81
BOTTOM VIEW
C A B
C
1.34
1.12
0.66±.05
4.08
3.70
(SCALE: 2X)
SEATING
PLANE
1.02
0.82
0.61
0.31
(8X)
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC REGISTRATION, MO-240, VARIATION AA.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENSIONS DO NOT INCLUDE BURRS OR
MOLD FLASH. MOLD FLASH OR BURRS DOES
NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) IT IS RECOMMENDED TO HAVE NO TRACES
OR VIAS WITHIN THE KEEP OUT AREA.
F) DRAWING FILE NAME: PQFN08EREV6.
G) FAIRCHILD SEMICONDUCTOR
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