FDMS7578

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This literature is subject to all applicable copyright laws and is not for resale in any manner. FDMS7578 N-Channel Power Trench® MOSFET 25 V,60 A, 5.8 mΩ Features General Description „ Max rDS(on) = 5.8 mΩ at VGS = 10 V, ID = 17 A This N-Channel MOSFET has been designed specifically to improve the overall efficiency and to minimize switch node ringing of DC/DC converters using either synchronous or conventional switching PWM controllers. It has been optimized for low gate charge, low rDS(on), fast switching speed and body diode reverse recovery performance. „ Max rDS(on) = 8 mΩ at VGS = 4.5 V, ID = 14 A „ Advanced Package and Silicon combination for low rDS(on) and high efficiency „ Next generation enhanced body diode technology, engineered for soft recovery Applications „ MSL1 robust package design „ Control MOSFET for Synchronous Buck Converters „ 100% UIL tested „ Notebook „ RoHS Compliant „ Server „ Telecomm „ High Efficiency DC-DC Switch Mode Power Supplies Bottom Top Pin 1 S D D D S S G D 5 4 G D 6 3 S D 7 2 S D 8 1 S D Power 56 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage (Note 4) Drain Current -Continuous TC = 25 °C -Continuous TA = 25 °C ID -Pulsed Single Pulse Avalanche Energy EAS PD TJ, TSTG TC = 25 °C Power Dissipation TA = 25 °C Units V ±20 V 60 (Note 1a) 17 (Note5) 90 (Note 3) Power Dissipation Ratings 25 40 33 (Note 1a) Operating and Storage Junction Temperature Range 2.5 -55 to +150 A mJ W °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient 3.7 (Note 1a) 50 °C/W Package Marking and Ordering Information Device Marking FDMS7578 Device FDMS7578 ©2009 Fairchild Semiconductor Corporation FDMS7578 Rev.C2 Package Power 56 1 Reel Size 13 ’’ Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMS7578 N-Channel Power Trench® MOSFET October 2014 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 20 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current,Forward VGS = 20 V, VDS = 0 V 100 nA 3.0 V 25 V 20 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C rDS(on) Static Drain to Source On Resistance gFS Forward Transconductance 1.0 1.6 -6 mV/°C VGS = 10 V, ID = 17 A 4.6 VGS = 4.5 V, ID = 14 A 6.3 8 VGS = 10 V, ID = 17 A, TJ = 125 °C 6.7 8.5 VDD = 5 V, ID = 17 A 77 5.8 mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 13 V, VGS = 0 V, f = 1 MHz 1221 1625 pF 371 495 pF 54 85 pF 1.2 2.4 Ω ns Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg(TOT) VDD = 13 V, ID = 17 A, VGS = 10 V, RGEN = 6 Ω 8 17 2.6 10 ns 20 33 ns 2.2 10 ns Total Gate Charge VGS = 0 V to 10 V 18 25 nC Total Gate Charge VGS = 0 V to 4.5 V VDD = 13 V ID = 17 A 8 11 3.7 nC 1.7 nC Qgs Total Gate Charge Qgd Gate to Drain “Miller” Charge nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 2 A (Note 2) 0.72 1.1 VGS = 0 V, IS = 17 A (Note 2) 0.83 1.2 20 32 ns 6 12 nC IF = 17 A, di/dt = 100 A/μs IF = 17 A, di/dt = 300 A/μs V 19 34 ns 13 24 nC NOTES: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. a. 50 °C/W when mounted on a 1 in2 pad of 2 oz copper b.125 °C/W when mounted on a minimum pad of 2 oz copper 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %. 3. EAS of 40 mJ is based on starting TJ = 25 °C, L = 1 mH, IAS = 9 A, VDD = 23 V, VGS = 10 V. 100% test at L = 0.3 mH, IAS = 14 A. 4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied. 5. Pulse Id refers to Figure.11 Forward Bias Safe Operation Area. ©2009 Fairchild Semiconductor Corporation FDMS7578 Rev.C2 2 www.fairchildsemi.com FDMS7578 N-Channel Power Trench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted 90 12 75 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) VGS = 10 V VGS = 3.5 V VGS = 4.5 V 60 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 45 VGS = 3 V 30 15 VGS = 2.5 V 0 0 0.5 1.0 1.5 2.0 2.5 10 VGS = 3 V 8 6 VGS = 3.5 V 4 VGS = 4.5 V VGS = 10 V 2 0 3.0 0 15 Figure 1. On-Region Characteristics 60 75 90 20 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 -75 SOURCE ON-RESISTANCE (mΩ) ID = 17 A 1.5 V = 10 V GS rDS(on), DRAIN TO NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 45 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 ID = 17 A PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 15 10 TJ = 125 oC 5 TJ = 25 oC 0 -50 2 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On- Resistance vs Junction Temperature Figure 4. On-Resistance vs Gate to Source Voltage 90 IS, REVERSE DRAIN CURRENT (A) 90 VDS = 5 V 75 ID, DRAIN CURRENT (A) 30 ID, DRAIN CURRENT (A) VDS, DRAIN TO SOURCE VOLTAGE (V) 60 TJ = 25 oC 45 TJ = 150 oC 30 TJ = -55 oC 15 0 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 2.5 V PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 1 2 3 4 10 TJ = 150 oC TJ = 25 oC 1 TJ = -55 oC 0.1 0.01 0.2 5 VGS, GATE TO SOURCE VOLTAGE (V) 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics ©2009 Fairchild Semiconductor Corporation FDMS7578 Rev.C2 VGS = 0 V Figure 6. Source to Drain Diode Forward Voltage vs Source Current 3 www.fairchildsemi.com FDMS7578 N-Channel Power Trench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 5000 ID = 17 A Ciss 8 VDD = 16 V VDD = 10 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 6 VDD = 13 V 4 2 1000 Coss 100 Crss f = 1 MHz VGS = 0 V 0 0 5 10 15 10 0.1 20 1 Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics 80 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 1 0.01 0.1 1 10 60 VGS = 10 V 40 Limited by Package o RθJC = 3.7 C/W 0 25 100 50 75 100 125 150 o TC, CASE TEMPERATURE ( C) Figure 9. Unclamped Inductive Switching Capability Figure 10. Maximum Continuous Drain Current vs Case Temperature 5 500 10 P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) VGS = 4.5 V 20 tAV, TIME IN AVALANCHE (ms) 100 10 THIS AREA IS LIMITED BY rDS(on) 100 μs SINGLE PULSE TJ = MAX RATED 1 ms o RθJC = 3.7 C/W CURVE BENT TO MEASURED DATA TC = 25 oC 0.1 0.1 25 Figure 8. Capacitance vs Drain to Source Voltage 50 1 10 VDS, DRAIN TO SOURCE VOLTAGE (V) 1 10 ms DC 10 100 VDS, DRAIN to SOURCE VOLTAGE (V) TC = 25 oC 4 10 3 10 2 10 1 10 -6 10 -5 10 -4 10 -3 10 -2 10 -1 10 1 t, PULSE WIDTH (sec) Figure 11. Forward Bias Safe Operating Area ©2009 Fairchild Semiconductor Corporation FDMS7578 Rev.C2 SINGLE PULSE RθJC = 3.7 oC/W Figure 12. Single Pulse Maximum Power Dissipation 4 www.fairchildsemi.com FDMS7578 N-Channel Power Trench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 2 NORMALIZED THERMAL IMPEDANCE, ZθJC 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 0.01 t2 SINGLE PULSE NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJC x RθJC + TC o RθJC = 3.7 C/W 0.001 -6 10 -5 10 -4 -3 10 10 -2 10 -1 10 1 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Transient Thermal Response Curve ©2009 Fairchild Semiconductor Corporation FDMS7578 Rev.C2 5 www.fairchildsemi.com FDMS7578 N-Channel Power Trench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted PQFN8 5X6, 1.27P CASE 483AE ISSUE A 5.10 PKG CL 8 5.10 3.91 A SEE DETAIL B B 5 1.27 8 7 6 5 0.77 4.52 PKG CL 5.85 5.65 6.15 3.75 6.61 KEEP OUT AREA 1.27 1 4 1 TOP VIEW 2 3 4 0.61 1.27 3.81 OPTIONAL DRAFT ANGLE MAY APPEAR ON FOUR SIDES OF THE PACKAGE SEE DETAIL C 5.00 4.80 LAND PATTERN RECOMMENDATION 0.35 0.15 0.10 C 0.05 0.00 SIDE VIEW 8X 0.08 C 5.20 4.80 1.10 0.90 3.81 0.35 0.15 DETAIL C SCALE: 2:1 1.27 0.51 (8X) 0.31 (0.34) 0.10 1 2 3 C A B 4 0.76 0.51 (0.52) 6.25 5.90 3.48+0.30 -0.10 (0.50) (0.30) (2X) 8 0.20+0.10 -0.15 (8X) 7 6 3.96 3.61 BOTTOM VIEW 0.30 0.05 5 C SEATING PLANE DETAIL B SCALE: 2:1 NOTES: UNLESS OTHERWISE SPECIFIED A. PACKAGE STANDARD REFERENCE: JEDEC MO-240, ISSUE A, VAR. AA,. B. DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. C. ALL DIMENSIONS ARE IN MILLIMETERS. D. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009. E. IT IS RECOMMENDED TO HAVE NO TRACES OR VIAS WITHIN THE KEEP OUT AREA. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. 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