FDMS7682

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This literature is subject to all applicable copyright laws and is not for resale in any manner. FDMS7682 N-Channel PowerTrench® MOSFET 30 V, 6.3 mΩ Features General Description „ Max rDS(on) = 6.3 mΩ at VGS = 10 V, ID = 14 A This N-Channel MOSFET has been designed specifically to improve the overall efficiency and to minimize switch node ringing of DC/DC converters using either synchronous or conventional switching PWM controllers.It has been optimized for low gate charge, low rDS(on), fast switching speed and body diode reverse recovery performance. „ Max rDS(on) = 10.4 mΩ at VGS = 4.5 V, ID = 11 A „ Advanced Package and Silicon combination for low rDS(on) and high efficiency „ Next generation enhanced engineered for soft recovery body diode technology, Applications „ MSL1 robust package design „ IMVP Vcore Switching for Notebook „ 100% UIL tested „ VRM Vcore Switching for Desktop and server „ RoHS Compliant „ OringFET / Load Switching „ DC-DC Conversion Bottom Top Pin 1 S D D D S S G D 5 4 G D 6 3 S D 7 2 S D 8 1 S D Power 56 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VDSt Drain to Source Transient Voltage ( tTransient < 100 ns) VGS Gate to Source Voltage (Note 4) Drain Current -Continuous (Package limited) ID TC = 25 °C -Continuous (Silicon limited) TC = 25 °C -Continuous TA = 25 °C PD TJ, TSTG Units V 33 V ±20 V 22 59 (Note 1a) -Pulsed 16 A 80 Single Pulse Avalanche Energy EAS Ratings 30 (Note 3) Power Dissipation TC = 25 °C Power Dissipation TA = 25 °C 29 33 (Note 1a) Operating and Storage Junction Temperature Range 2.5 -55 to +150 mJ W °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient 3.7 (Note 1a) 50 °C/W Package Marking and Ordering Information Device Marking FDMS7682 Device FDMS7682 ©2010 Fairchild Semiconductor Corporation FDMS7682 Rev.C3 Package Power 56 1 Reel Size 13 ’’ Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMS7682 N-Channel PowerTrench® MOSFET January 2015 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 24 V, VGS = 0 V IGSS Gate to Source Leakage Current, Forward VGS = ±20 V, VDS = 0 V 30 V 15 mV/°C 1 μA 100 nA 3.0 V On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C rDS(on) Static Drain to Source On Resistance gFS Forward Transconductance 1.25 1.9 -6 mV/°C VGS = 10 V, ID = 14 A 5.2 6.3 VGS = 4.5 V, ID = 11 A 8.0 10.4 VGS = 10 V, ID = 14 A, TJ = 125 °C 7.0 8.5 VDS = 5 V, ID = 14 A 70 mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 15 V, VGS = 0 V, f = 1 MHz 1416 1885 pF 479 640 pF 50 75 pF 0.7 2.4 Ω Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg Total Gate Charge Qg Total Gate Charge Qgs Gate to Source Charge Qgd Gate to Drain “Miller” Charge VDD = 15 V, ID = 14 A, VGS = 10 V, RGEN = 6 Ω 9.4 19 ns 2.7 10 ns 22 35 ns 2.2 10 ns VGS = 0 V to 10 V 21 30 nC VGS = 0 V to 4.5 V VDD = 15 V, ID = 14 A 9.9 14 nC 4.3 nC 2.8 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 2.1 A (Note 2) 0.74 1.2 VGS = 0 V, IS = 14 A (Note 2) 0.83 1.3 IF = 14 A, di/dt = 100 A/μs IF = 14 A, di/dt = 300 A/μs V 27 43 ns 10 21 nC 20 36 ns 17 30 nC Notes: 1. RθJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. a) 50 °C/W when mounted on a 1 in2 pad of 2 oz copper b) 125 °C/W when mounted on a minimum pad of 2 oz copper. 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. EAS of 29 mJ is based on starting TJ = 25 °C, L = 0.3 mH, IAS = 14 A, VDD = 27 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 21 A. 4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied. FDMS7682 Rev.C3 2 www.fairchildsemi.com FDMS7682 N-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted 5 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 80 ID, DRAIN CURRENT (A) VGS = 4.5 V VGS = 4 V 60 VGS = 10 V 40 VGS = 5 V VGS = 3.5 V 20 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 3.5 V 4 VGS = 4 V 3 VGS = 4.5 V 2 1 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 1 2 3 0 20 VDS, DRAIN TO SOURCE VOLTAGE (V) 40 60 80 ID, DRAIN CURRENT (A) Figure 1. On Region Characteristics Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.6 25 ID = 14 A VGS = 10 V 1.5 rDS(on), DRAIN TO 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 -75 -50 -25 0 25 50 75 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 10 V 0 0 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 20 ID = 14 A 15 10 TJ = 125 oC 5 TJ = 25 oC 0 100 125 150 2 4 TJ, JUNCTION TEMPERATURE (oC) 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On Resistance vs Junction Temperature Figure 4. On-Resistance vs Gate to Source Voltage 100 IS, REVERSE DRAIN CURRENT (A) 80 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) VGS = 5 V 60 VDS = 5 V 40 TJ = 150 oC TJ = 25 oC 20 TJ = -55 oC 0 1 2 3 4 10 TJ = 150 oC TJ = 25 oC 1 0.1 TJ = -55 oC 0.01 0.2 5 VGS, GATE TO SOURCE VOLTAGE (V) 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics FDMS7682 Rev.C3 VGS = 0 V Figure 6. Source to Drain Diode Forward Voltage vs Source Current 3 www.fairchildsemi.com FDMS7682 N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 4000 ID = 14 A 8 1000 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 15 V 6 VDD = 20 V VDD = 10 V 4 Ciss Coss 100 f = 1 MHz VGS = 0 V 2 10 0.1 0 0 4 8 12 16 20 24 1 Figure 7. Gate Charge Characteristics 30 Figure 8. Capacitance vs Drain to Source Voltage 60 30 VGS = 10 V 10 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) TJ = 25 oC TJ = 100 oC TJ = 125 oC 45 VGS = 4.5 V 30 15 o RθJC = 3.7 C/W Limited by Package 1 0.01 0.1 1 10 0 25 100 50 P(PK), PEAK TRANSIENT POWER (W) 100 us 1 ms 10 ms 100 ms THIS AREA IS LIMITED BY rDS(on) 1s SINGLE PULSE TJ = MAX RATED 10 s RθJA = 125 oC/W DC TA = 25 oC 0.1 1 10 VGS = 10 V 100200 SINGLE PULSE RθJA = 125 oC/W 100 TA = 25 oC 10 1 0.5 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 11. Forward Bias Safe Operating Area FDMS7682 Rev.C3 150 500 10 0.01 0.01 125 Figure 10. Maximum Continuous Drain Current vs Case Temperature 100 0.1 100 o Figure 9. Unclamped Inductive Switching Capability 1 75 TC, CASE TEMPERATURE ( C) tAV, TIME IN AVALANCHE (ms) ID, DRAIN CURRENT (A) Crss Figure 12. Single Pulse Maximum Power Dissipation 4 www.fairchildsemi.com FDMS7682 N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 125 C/W 0.001 -4 10 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve FDMS7682 Rev.C3 5 www.fairchildsemi.com FDMS7682 N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted PQFN8 5X6, 1.27P CASE 483AE ISSUE A 5.10 PKG CL 8 5.10 3.91 A SEE DETAIL B B 5 1.27 8 7 6 5 0.77 4.52 PKG CL 5.85 5.65 6.15 3.75 6.61 KEEP OUT AREA 1.27 1 4 1 TOP VIEW 2 3 4 0.61 1.27 3.81 OPTIONAL DRAFT ANGLE MAY APPEAR ON FOUR SIDES OF THE PACKAGE SEE DETAIL C 5.00 4.80 LAND PATTERN RECOMMENDATION 0.35 0.15 0.10 C 0.05 0.00 SIDE VIEW 8X 0.08 C 5.20 4.80 1.10 0.90 3.81 0.35 0.15 DETAIL C SCALE: 2:1 1.27 0.51 (8X) 0.31 (0.34) 0.10 1 2 3 C A B 4 0.76 0.51 (0.52) 6.25 5.90 3.48+0.30 -0.10 (0.50) (0.30) (2X) 8 0.20+0.10 -0.15 (8X) 7 6 3.96 3.61 BOTTOM VIEW 0.30 0.05 5 C SEATING PLANE DETAIL B SCALE: 2:1 NOTES: UNLESS OTHERWISE SPECIFIED A. PACKAGE STANDARD REFERENCE: JEDEC MO-240, ISSUE A, VAR. AA,. B. DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. C. ALL DIMENSIONS ARE IN MILLIMETERS. D. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009. E. IT IS RECOMMENDED TO HAVE NO TRACES OR VIAS WITHIN THE KEEP OUT AREA. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. 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