FDMS86255

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This literature is subject to all applicable copyright laws and is not for resale in any manner. FDMS86255 N-Channel Shielded Gate PowerTrench® MOSFET 150 V, 45 A, 12.4 mΩ Features General Description „ Shielded Gate MOSFET Technology This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench® process that incorporates Shielded Gate technology. This process has been optimized for the on-state resistance and yet maintain superior switching performance. „ Max rDS(on) = 12.4 mΩ at VGS = 10 V, ID = 10 A „ Max rDS(on) = 15.5 mΩ at VGS = 6 V, ID = 8 A „ Advanced Package and Silicon combination for low rDS(on) and high efficiency „ Next generation enhanced engineered for soft recovery body diode Applications technology, „ OringFET / Load Switching „ MSL1 robust package design „ Synchronous rectification „ 100% UIL tested „ DC-DC Conversion „ RoHS Compliant Bottom Top Pin 1 S S Pin 1 D D D S G D S D S D S D G D Power 56 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current ID -Continuous TC = 25 °C -Continuous TA = 25 °C -Pulsed Single Pulse Avalanche Energy EAS PD TJ, TSTG Power Dissipation TC = 25 °C Power Dissipation TA = 25 °C Ratings 150 Units V ±20 V 45 (Note 1a) 10 (Note 4) 100 (Note 3) 541 113 (Note 1a) Operating and Storage Junction Temperature Range 2.7 -55 to +150 A mJ W °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case RθJA Thermal Resistance, Junction to Ambient 1.1 (Note 1a) 45 °C/W Package Marking and Ordering Information Device Marking FDMS86255 Device FDMS86255 ©2013 Fairchild Semiconductor Corporation FDMS86255 Rev. 2.0 Package Power 56 Reel Size 13 ’’ 1 Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMS86255 N-Channel Shielded Gate PowerTrench® MOSFET March 2015 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 120 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 4.0 V 150 V 109 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C VGS = 10 V, ID = 10 A 9.5 12.4 rDS(on) Static Drain to Source On Resistance VGS = 6 V, ID = 8 A 11.5 15.5 VGS = 10 V, ID = 10 A, TJ = 125 °C 19 25 VDS = 5 V, ID = 10 A 35 gFS Forward Transconductance 2.0 3.0 -11 mV/°C mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 75 V, VGS = 0 V, f = 1 MHz 0.1 3200 4480 pF 291 410 pF 11 20 pF 0.7 2.1 Ω ns Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time VDD = 75 V, ID = 10 A, VGS = 10 V, RGEN = 6 Ω tf Fall Time Qg Total Gate Charge VGS = 0 V to 10 V Qg Total Gate Charge VGS = 0 V to 6 V Qgs Gate to Source Charge Qgd Gate to Drain “Miller” Charge VDD = 75 V, ID = 10 A 21 34 4.5 10 ns 28 45 ns 6.2 12 ns 45 63 nC 29 41 nC 14 nC 8.8 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 1.9 A (Note 2) 0.7 1.2 VGS = 0 V, IS = 10 A (Note 2) 0.8 1.3 IF = 10 A, di/dt = 100 A/μs V 87 139 ns 165 264 nC Notes: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. a. 45 °C/W when mounted on a 1 in2 pad of 2 oz copper. b. 115 °C/W when mounted on a minimum pad of 2 oz copper. SS SF DS DF G SS SF DS DF G 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. EAS of 541 mJ is based on starting TJ = 25 °C, L = 3 mH, IAS = 19 A, VDD = 150 V, VGS = 10 V. 100% tested at L = 0.1 mH, IAS = 60 A. 4. Pulse Id refers to Figure.11 Forward Bias Safe Operation Area. ©2013 Fairchild Semiconductor Corporation FDMS86255 Rev. 2.0 2 www.fairchildsemi.com FDMS86255 N-Channel Shielded Gate PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted 100 VGS = 10 V 80 ID, DRAIN CURRENT (A) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 4 VGS = 6 V 60 VGS = 5.5 V 40 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS = 5 V 20 VGS = 4.5 V 0 0 1 2 3 4 VGS = 4.5 V 3 VGS = 5 V 2 VGS = 5.5 V 1 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 20 80 100 50 rDS(on), DRAIN TO 2.0 1.5 1.0 SOURCE ON-RESISTANCE (mΩ) ID = 10 A VGS = 10 V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 60 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 2.5 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 40 ID = 10 A 30 TJ = 125 oC 20 TJ = 25 oC 10 0 -30 0 30 60 90 120 TJ, JUNCTION TEMPERATURE (oC) 150 4 IS, REVERSE DRAIN CURRENT (A) 80 VDS = 5 V 60 TJ = 150 oC 40 TJ = 25 oC 20 TJ = -55 oC 0 5 6 VGS = 0 V 10 TJ = 150 oC 1 TJ = 25 oC 0.1 0.01 TJ = -55 oC 0.001 0.0 7 VGS, GATE TO SOURCE VOLTAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics ©2013 Fairchild Semiconductor Corporation FDMS86255 Rev. 2.0 10 100 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 4 8 Figure 4. On-Resistance vs Gate to Source Voltage 100 3 6 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On- Resistance vs Junction Temperature ID, DRAIN CURRENT (A) 40 ID, DRAIN CURRENT (A) Figure 1. On-Region Characteristics 2 VGS = 10 V 0 5 VDS, DRAIN TO SOURCE VOLTAGE (V) 0.5 -60 VGS = 6 V Figure 6. Source to Drain Diode Forward Voltage vs Source Current 3 www.fairchildsemi.com FDMS86255 N-Channel Shielded Gate PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 10000 ID = 10 A Ciss 8 VDD = 75 V CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 6 VDD = 50 V VDD = 100 V 4 2 1000 Coss 100 Crss f = 1 MHz VGS = 0 V 10 0 0 10 20 30 40 5 0.1 50 Qg, GATE CHARGE (nC) 1 Figure 7. Gate Charge Characteristics 100 Figure 8. Capacitance vs Drain to Source Voltage 80 ID, DRAIN CURRENT (A) 100 IAS, AVALANCHE CURRENT (A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 64 48 VGS = 10 V 32 Limited by Package VGS = 6 V 16 o RθJC = 1.1 C/W 1 0.01 0.1 1 10 0 25 100 300 50 75 100 125 150 o tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE ( C) Figure 9. Unclamped Inductive Switching Capability Figure 10. Maximum Continuous Drain Current vs Case Temperature 1000 20000 P(PK), PEAK TRANSIENT POWER (W) ID, DRAIN CURRENT (A) 10000 100 10 μs 10 1 0.1 100 μs THIS AREA IS LIMITED BY rDS(on) RθJC = 1.1 oC/W o TC = 25 C 0.01 0.1 1 ms SINGLE PULSE TJ = MAX RATED 10 ms DC CURVE BENT TO MEASURED DATA 1 10 100 700 TC = 25 oC 1000 100 10 -5 10 -4 10 -3 10 -2 10 -1 10 1 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 11. Forward Bias Safe Operating Area ©2013 Fairchild Semiconductor Corporation FDMS86255 Rev. 2.0 SINGLE PULSE RθJC = 1.1 oC/W Figure 12. Single Pulse Maximum Power Dissipation 4 www.fairchildsemi.com FDMS86255 N-Channel Shielded Gate PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 2 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: ZθJC(t) = r(t) x RθJC SINGLE PULSE 0.001 -5 10 RθJC = 1.1 °C/W Peak TJ = PDM x ZθJC(t) + TC Duty Cycle, D = t1 / t2 -4 10 -3 -2 10 10 -1 10 1 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Transient Thermal Response Curve ©2013 Fairchild Semiconductor Corporation FDMS86255 Rev. 2.0 5 www.fairchildsemi.com FDMS86255 N-Channel Shielded Gate PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 5.10 4.90 A 3.81 PKG CL 8 4.42 B 5 8 7 6 5 1.14 KEEP OUT AREA 3.65 6.25 5.90 PKG CL 6.61 4.79 1.27 1 PIN #1 IDICATOR 4 TOP VIEW 1 2 3 4 1.27 SEE DETAIL A 0.61 3.81 5.10 LAND PATTERN RECOMMENDATION SIDE VIEW 3.81 0.10 1.27 (0.38) 1 C A B 0.47 (8X) 0.37 4 (0.35) 0.65 0.55 PIN #1 INDICATOR 4.66 4.46 8 5 4.33 4.13 0.70 BOTTOM VIEW 0.10 C 1.10 0.90 0.08 C C 0.25 0.15 SCALE: 2:1 0.05 0.00 SEATING PLANE NOTES: UNLESS OTHERWISE SPECIFIED A) PACKAGE STANDARD REFERENCE: JEDEC MO-240, ISSUE A, VAR. AA, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009. E) IT IS RECOMMENDED TO HAVE NO TRACES OR VIAS WITHIN THE KEEP OUT AREA. F) DRAWING FILE NAME: PQFN08JREV3. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 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