FDMS86500DC

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Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. FDMS86500DC N-Channel Dual CoolTM 56 Power Trench® MOSFET 60 V, 108 A, 2.3 mΩ Features „ Dual CoolTM General Description Top Side Cooling PQFN package This N-Channel MOSFET is produced using Fairchild Semiconductor’s advanced Power Trench® process. Advancements in both silicon and Dual CoolTM package technologies have been combined to offer the lowest rDS(on) while maintaining excellent switching performance by extremely low Junction-to-Ambient thermal resistance. „ Max rDS(on) = 2.3 mΩ at VGS = 10 V, ID = 29 A „ Max rDS(on) = 3.3 mΩ at VGS = 8 V, ID = 24 A „ High performance technology for extremely low rDS(on) „ 100% UIL Tested Applications „ RoHS Compliant „ Synchronous Rectifier for DC/DC Converters „ Telecom Secondary Side Rectification „ High End Server/Workstation Vcore Low Side D D D S Pin 1 S D S D S D G D D G TM Top Dual Cool S S Pin 1 S Bottom 56 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current ID -Continuous TC = 25 °C -Continuous TA = 25 °C TJ, TSTG ±20 V (Note 1a) 29 A 200 Single Pulse Avalanche Energy PD Units V 108 -Pulsed EAS Ratings 60 (Note 3) Power Dissipation TC = 25 °C Power Dissipation TA = 25 °C 317 125 (Note 1a) Operating and Storage Junction Temperature Range 3.2 -55 to +150 mJ W °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case (Top Source) 2.8 RθJC Thermal Resistance, Junction to Case (Bottom Drain) 1.0 RθJA Thermal Resistance, Junction to Ambient (Note 1a) 38 RθJA Thermal Resistance, Junction to Ambient (Note 1b) 81 RθJA Thermal Resistance, Junction to Ambient (Note 1i) 16 RθJA Thermal Resistance, Junction to Ambient (Note 1j) 23 RθJA Thermal Resistance, Junction to Ambient (Note 1k) 11 °C/W Package Marking and Ordering Information Device Marking 86500 Device FDMS86500DC ©2012 Fairchild Semiconductor Corporation FDMS86500DC Rev. 1.7 Package Dual CoolTM 56 1 Reel Size 13’’ Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMS86500DC N-Channel Dual CoolTM 56 Power Trench® MOSFET July 2015 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25°C IDSS Zero Gate Voltage Drain Current VDS = 48 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 4.5 V 60 V 30 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C VGS = 10 V, ID = 29 A 1.9 2.3 rDS(on) Static Drain to Source On Resistance VGS = 8 V, ID = 24 A 2.4 3.3 VGS = 10 V, ID = 29 A, TJ = 125 °C 3.0 3.7 VDS = 10 V, ID = 29 A 98 gFS Forward Transconductance 2.5 3.7 -12 mV/°C mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 30 V, VGS = 0 V, f = 1 MHz 0.1 5775 7680 pF 1605 2680 pF 48 95 pF 1 3 Ω 35 56 ns 25 40 ns 34 54 ns 8.2 17 ns 76 107 nC 62 87 Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg(TOT) VDD = 30 V , ID = 29 A, VGS = 10 V, RGEN = 6 Ω Total Gate Charge VGS = 0 V to 10 V Total Gate Charge VGS = 0 V to 8 V Qgs Total Gate Charge Qgd Gate to Drain “Miller” Charge VDD = 30 V ID = 29 A nC 31 nC 15 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge ©2012 Fairchild Semiconductor Corporation FDMS86500DC Rev. 1.7 VGS = 0 V, IS = 2.7 A (Note 2) 0.71 1.2 VGS = 0 V, IS = 29 A (Note 2) 0.79 1.3 IF = 29 A, di/dt = 100 A/μs 2 V 59 95 ns 46 74 nC www.fairchildsemi.com FDMS86500DC N-Channel Dual CoolTM 56 Power Trench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted RθJC Thermal Resistance, Junction to Case (Top Source) 2.8 RθJC Thermal Resistance, Junction to Case (Bottom Drain) 1.0 RθJA Thermal Resistance, Junction to Ambient (Note 1a) 38 RθJA Thermal Resistance, Junction to Ambient (Note 1b) 81 RθJA Thermal Resistance, Junction to Ambient (Note 1c) 27 RθJA Thermal Resistance, Junction to Ambient (Note 1d) 34 RθJA Thermal Resistance, Junction to Ambient (Note 1e) 16 RθJA Thermal Resistance, Junction to Ambient (Note 1f) 19 RθJA Thermal Resistance, Junction to Ambient (Note 1g) 26 RθJA Thermal Resistance, Junction to Ambient (Note 1h) 61 RθJA Thermal Resistance, Junction to Ambient (Note 1i) 16 RθJA Thermal Resistance, Junction to Ambient (Note 1j) 23 RθJA Thermal Resistance, Junction to Ambient (Note 1k) 11 RθJA Thermal Resistance, Junction to Ambient (Note 1l) 13 °C/W NOTES: 1. RθJA is determined with the device mounted on a FR-4 board using a specified pad of 2 oz copper as shown below. RθJC is guaranteed by design while RθCA is determined by the user's board design. b. 81 °C/W when mounted on a minimum pad of 2 oz copper a. 38 °C/W when mounted on a 1 in2 pad of 2 oz copper SS SF DS DF G SS SF DS DF G c. Still air, 20.9x10.4x12.7mm Aluminum Heat Sink, 1 in2 pad of 2 oz copper d. Still air, 20.9x10.4x12.7mm Aluminum Heat Sink, minimum pad of 2 oz copper e. Still air, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, 1 in2 pad of 2 oz copper f. Still air, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, minimum pad of 2 oz copper g. 200FPM Airflow, No Heat Sink,1 in2 pad of 2 oz copper h. 200FPM Airflow, No Heat Sink, minimum pad of 2 oz copper i. 200FPM Airflow, 20.9x10.4x12.7mm Aluminum Heat Sink, 1 in2 pad of 2 oz copper j. 200FPM Airflow, 20.9x10.4x12.7mm Aluminum Heat Sink, minimum pad of 2 oz copper k. 200FPM Airflow, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, 1 in2 pad of 2 oz copper l. 200FPM Airflow, 45.2x41.4x11.7mm Aavid Thermalloy Part # 10-L41B-11 Heat Sink, minimum pad of 2 oz copper 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 3. Starting TJ = 25 oC; N-ch: L = 0.3 mH, IAS = 46 A, VDD = 54 V, VGS = 10 V. ©2012 Fairchild Semiconductor Corporation FDMS86500DC Rev. 1.7 3 www.fairchildsemi.com FDMS86500DC N-Channel Dual CoolTM 56 Power Trench® MOSFET Thermal Characteristics 200 5 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 8 V ID, DRAIN CURRENT (A) VGS = 7 V 150 VGS = 10 V VGS = 6.5 V 100 50 VGS = 6 V PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 0 0 1 2 3 4 VGS = 6 V 4 VGS = 6.5 V 3 VGS = 7 V 2 VGS = 8 V 1 0 5 0 50 100 ID, DRAIN CURRENT (A) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 1. On-Region Characteristics rDS(on), DRAIN TO 1.4 1.2 1.0 0.8 0.6 -75 -50 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 200 10 ID = 29 A VGS = 10 V 1.6 IS, REVERSE DRAIN CURRENT (A) 150 VDS = 5 V 100 TJ = 150 oC TJ = 25 oC 50 TJ = -55 oC 4 5 6 7 8 6 TJ = 125 oC 4 2 TJ = 25 oC 6 7 8 9 200 100 10 TJ = 150 oC 1 TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.001 0.0 8 VGS = 0 V 0.2 0.4 0.6 0.8 1.0 VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current ©2012 Fairchild Semiconductor Corporation FDMS86500DC Rev. 1.7 10 Figure 4. On-Resistance vs Gate to Source Voltage PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 3 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX VGS, GATE TO SOURCE VOLTAGE (V) 200 2 ID = 29 A 0 5 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) Figure 3. Normalized On- Resistance vs Junction Temperature ID, DRAIN CURRENT (A) 150 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 1.8 0 VGS = 10 V PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 4 1.2 www.fairchildsemi.com FDMS86500DC N-Channel Dual CoolTM 56 Power Trench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 10000 ID = 29 A VDD = 30 V Ciss 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 40 V VDD = 20 V 6 4 1000 Coss 100 Crss 2 f = 1 MHz VGS = 0 V 0 0 20 40 60 10 0.1 80 1 Figure 7. Gate Charge Characteristics 180 o RθJC = 1.0 C/W 100 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) 60 Figure 8. Capacitance vs Drain to Source Voltage 200 TJ = 25 oC TJ = 100 oC 10 TJ = 125 oC 150 VGS = 10 V VGS = 8 V 120 90 Limited by Package 60 30 1 0.01 0.1 1 10 100 0 25 500 50 100 125 150 TC, CASE TEMPERATURE ( C) Figure 9. Unclamped Inductive Switching Capability Figure 10. Maximum Continuous Drain Current vs Case Temperature 2000 P(PK), PEAK TRANSIENT POWER (W) 300 100 1 ms 10 10 ms 1 75 o tAV, TIME IN AVALANCHE (ms) ID, DRAIN CURRENT (A) 10 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) THIS AREA IS LIMITED BY rDS(on) 0.1 0.01 0.01 100 ms SINGLE PULSE TJ = MAX RATED 1s RθJA = 81 oC/W 10 s TA = 25 oC DC 0.1 1 10 100 400 TA = 25 oC 100 10 1 -3 10 -2 10 -1 10 1 10 100 1000 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 11. Forward Bias Safe Operating Area ©2012 Fairchild Semiconductor Corporation FDMS86500DC Rev. 1.7 SINGLE PULSE RθJA = 81 oC/W 1000 Figure 12. Single Pulse Maximum Power Dissipation 5 www.fairchildsemi.com FDMS86500DC N-Channel Dual CoolTM 56 Power Trench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 2 NORMALIZED THERMAL IMPEDANCE, ZθJA 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZθJA x RθJA + TA SINGLE PULSE o RθJA = 81 C/W 0.001 -3 10 -2 10 -1 10 1 10 100 1000 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Ambient Transient Thermal Response Curve ©2012 Fairchild Semiconductor Corporation FDMS86500DC Rev. 1.7 6 www.fairchildsemi.com FDMS86500DC N-Channel Dual CoolTM 56 Power Trench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted (2X) A .1 C 4.90 (2X) A (2.60) (0.90) 5.10 .1 C CL 8 0.77 B 5 CL 8 7 6 1.27 5 KEEPOUT 2.04 AREA 2.54 A (3.30) 3.91 5.80 1.22 (2.08) 2.67 (0.82) 1 1.27 4 (1.05) OPTIONAL PIN 1 INDICATOR 1 SEE DETAIL A 2 3 4 0.61 1.27 3.81 LAND PATTERN RECOMMENDATION A 5.00 4.80 OPTIONAL DRAFT ANGLE MAY APPEAR ON FOUR A 0.41 (8X) SIDES OF THE PACKAGE 0.31 0.50 (8X) 0.40 7° 0.10 C A B 3.81 1.27 (0.34) 1 2 3 A 0.71 (4X) 0.44 4 A (1.40) 0.35 0.25 0.40 0.30 CHAMFER CORNER AS PIN #1 IDENT MAY APPEAR AS OPTIONAL 3.58 3.38 1.05 0.95 (0.50) 5.85 A 5.50 (0.20) (8X) 8 7 6 5 0.65 0.45 (4X) 3.86 3.61 0.1 MAX 0.10 C 0.08 C (1.02) 0.30 0.20 SCALE: 2:1 0.05 0.00 C SEATING PLANE NOTES: A) PACKAGE IS NOT FULLY COMPLIANT TO JEDEC MO-240, VARIATION AA. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009. E) IT IS RECOMMENDED TO HAVE NO TRACES OR VIAS WITHIN THE KEEP OUT AREA. F) DRAWING FILE NAME: PQFN08DREV4 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. 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